1 /***************************************************************************
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2 * Copyright (C) 2005 by Dominic Rath *
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3 * Dominic.Rath@gmx.de *
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5 * Copyright (C) 2008 by Spencer Oliver *
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6 * spen@spen-soft.co.uk *
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8 * Copyright (C) 2008 by John McCarthy *
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11 * This program is free software; you can redistribute it and/or modify *
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12 * it under the terms of the GNU General Public License as published by *
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13 * the Free Software Foundation; either version 2 of the License, or *
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14 * (at your option) any later version. *
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16 * This program is distributed in the hope that it will be useful, *
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17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
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18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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19 * GNU General Public License for more details. *
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21 * You should have received a copy of the GNU General Public License *
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22 * along with this program; if not, write to the *
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23 * Free Software Foundation, Inc., *
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24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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25 ***************************************************************************/
\r
26 #ifdef HAVE_CONFIG_H
\r
30 #include "replacements.h"
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32 #include "pic32mx.h"
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37 #include "algorithm.h"
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38 #include "binarybuffer.h"
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44 struct pic32mx_devs_s {
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48 } pic32mx_devs[] = {
\r
49 { 0x78, "460F512L USB", 512 },
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50 { 0x74, "460F256L USB", 256 },
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51 { 0x6D, "440F128L USB", 128 },
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52 { 0x56, "440F512H USB", 512 },
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53 { 0x52, "440F256H USB", 256 },
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54 { 0x4D, "440F128H USB", 128 },
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55 { 0x42, "420F032H USB", 32 },
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56 { 0x38, "360F512L", 512 },
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57 { 0x34, "360F256L", 256 },
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58 { 0x2D, "340F128L", 128 },
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59 { 0x2A, "320F128L", 128 },
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60 { 0x16, "340F512H", 512 },
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61 { 0x12, "340F256H", 256 },
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62 { 0x0D, "340F128H", 128 },
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63 { 0x0A, "320F128H", 128 },
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64 { 0x06, "320F064H", 64 },
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65 { 0x02, "320F032H", 32 },
\r
69 int pic32mx_register_commands(struct command_context_s *cmd_ctx);
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70 int pic32mx_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
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71 int pic32mx_erase(struct flash_bank_s *bank, int first, int last);
\r
72 int pic32mx_protect(struct flash_bank_s *bank, int set, int first, int last);
\r
73 int pic32mx_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
\r
74 int pic32mx_probe(struct flash_bank_s *bank);
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75 int pic32mx_auto_probe(struct flash_bank_s *bank);
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76 int pic32mx_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
\r
77 int pic32mx_protect_check(struct flash_bank_s *bank);
\r
78 int pic32mx_info(struct flash_bank_s *bank, char *buf, int buf_size);
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81 int pic32mx_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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82 int pic32mx_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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84 int pic32mx_handle_chip_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
\r
85 int pic32mx_handle_pgm_word_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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86 int pic32mx_chip_erase(struct flash_bank_s *bank);
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88 flash_driver_t pic32mx_flash =
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91 .register_commands = pic32mx_register_commands,
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92 .flash_bank_command = pic32mx_flash_bank_command,
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93 .erase = pic32mx_erase,
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94 .protect = pic32mx_protect,
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95 .write = pic32mx_write,
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96 .probe = pic32mx_probe,
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97 .auto_probe = pic32mx_auto_probe,
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98 .erase_check = default_flash_mem_blank_check,
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99 .protect_check = pic32mx_protect_check,
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100 .info = pic32mx_info
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103 int pic32mx_register_commands(struct command_context_s *cmd_ctx)
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105 command_t *pic32mx_cmd = register_command(cmd_ctx, NULL, "pic32mx", NULL, COMMAND_ANY, "pic32mx flash specific commands");
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108 register_command(cmd_ctx, pic32mx_cmd, "lock", pic32mx_handle_lock_command, COMMAND_EXEC,
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110 register_command(cmd_ctx, pic32mx_cmd, "unlock", pic32mx_handle_unlock_command, COMMAND_EXEC,
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111 "unlock protected device");
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113 register_command(cmd_ctx, pic32mx_cmd, "chip_erase", pic32mx_handle_chip_erase_command, COMMAND_EXEC,
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115 register_command(cmd_ctx, pic32mx_cmd, "pgm_word", pic32mx_handle_pgm_word_command, COMMAND_EXEC,
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120 /* flash bank pic32mx <base> <size> 0 0 <target#>
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122 int pic32mx_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
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124 pic32mx_flash_bank_t *pic32mx_info;
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128 LOG_WARNING("incomplete flash_bank pic32mx configuration");
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129 return ERROR_FLASH_BANK_INVALID;
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132 pic32mx_info = malloc(sizeof(pic32mx_flash_bank_t));
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133 bank->driver_priv = pic32mx_info;
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135 pic32mx_info->write_algorithm = NULL;
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136 pic32mx_info->probed = 0;
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141 u32 pic32mx_get_flash_status(flash_bank_t *bank)
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143 target_t *target = bank->target;
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146 target_read_u32(target, PIC32MX_NVMCON, &status);
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151 u32 pic32mx_wait_status_busy(flash_bank_t *bank, int timeout)
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155 /* wait for busy to clear */
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156 while (((status = pic32mx_get_flash_status(bank)) & NVMCON_NVMWR) && (timeout-- > 0))
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158 LOG_DEBUG("status: 0x%x", status);
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162 LOG_DEBUG("timeout: status: 0x%x", status);
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167 int pic32mx_nvm_exec(struct flash_bank_s *bank, u32 op, u32 timeout)
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169 target_t *target = bank->target;
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172 target_write_u32(target, PIC32MX_NVMCON, NVMCON_NVMWREN|op);
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174 /* unlock flash registers */
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175 target_write_u32(target, PIC32MX_NVMKEY, NVMKEY1);
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176 target_write_u32(target, PIC32MX_NVMKEY, NVMKEY2);
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178 /* start operation */
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179 target_write_u32(target, PIC32MX_NVMCONSET, NVMCON_NVMWR);
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181 status = pic32mx_wait_status_busy(bank, timeout);
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183 /* lock flash registers */
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184 target_write_u32(target, PIC32MX_NVMCONCLR, NVMCON_NVMWREN);
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189 int pic32mx_protect_check(struct flash_bank_s *bank)
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191 target_t *target = bank->target;
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192 pic32mx_flash_bank_t *pic32mx_info = bank->driver_priv;
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198 if (target->state != TARGET_HALTED)
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200 LOG_ERROR("Target not halted");
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201 return ERROR_TARGET_NOT_HALTED;
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204 target_read_u32(target, PIC32MX_DEVCFG0, &devcfg0);
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205 if((devcfg0 & (1<<28)) == 0) /* code protect bit */
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206 num_pages = 0xffff; /* All pages protected */
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207 else if(bank->base == PIC32MX_KSEG1_BOOT_FLASH)
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209 if(devcfg0 & (1<<24))
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210 num_pages = 0; /* All pages unprotected */
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212 num_pages = 0xffff; /* All pages protected */
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214 else /* pgm flash */
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215 num_pages = (~devcfg0 >> 12) & 0xff;
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216 for (s = 0; s < bank->num_sectors && s < num_pages; s++)
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217 bank->sectors[s].is_protected = 1;
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218 for (; s < bank->num_sectors; s++)
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219 bank->sectors[s].is_protected = 0;
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224 int pic32mx_erase(struct flash_bank_s *bank, int first, int last)
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226 target_t *target = bank->target;
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230 if (bank->target->state != TARGET_HALTED)
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232 LOG_ERROR("Target not halted");
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233 return ERROR_TARGET_NOT_HALTED;
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237 if ((first == 0) && (last == (bank->num_sectors - 1)) && (bank->base == PIC32MX_KSEG0_PGM_FLASH || bank->base == PIC32MX_KSEG1_PGM_FLASH))
\r
239 status = pic32mx_nvm_exec(bank, NVMCON_OP_PFM_ERASE, 50);
\r
240 if( status & NVMCON_NVMERR )
\r
241 return ERROR_FLASH_OPERATION_FAILED;
\r
242 if( status & NVMCON_LVDERR )
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243 return ERROR_FLASH_OPERATION_FAILED;
\r
248 for (i = first; i <= last; i++)
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250 target_write_u32(target, PIC32MX_NVMADDR, bank->base + bank->sectors[i].offset);
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252 status = pic32mx_nvm_exec(bank, NVMCON_OP_PAGE_ERASE, 10);
\r
254 if( status & NVMCON_NVMERR )
\r
255 return ERROR_FLASH_OPERATION_FAILED;
\r
256 if( status & NVMCON_LVDERR )
\r
257 return ERROR_FLASH_OPERATION_FAILED;
\r
258 bank->sectors[i].is_erased = 1;
\r
264 int pic32mx_protect(struct flash_bank_s *bank, int set, int first, int last)
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266 pic32mx_flash_bank_t *pic32mx_info = NULL;
\r
267 target_t *target = bank->target;
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268 u16 prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
\r
273 pic32mx_info = bank->driver_priv;
\r
275 if (target->state != TARGET_HALTED)
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277 LOG_ERROR("Target not halted");
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278 return ERROR_TARGET_NOT_HALTED;
\r
282 if ((first && (first % pic32mx_info->ppage_size)) || ((last + 1) && (last + 1) % pic32mx_info->ppage_size))
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284 LOG_WARNING("sector start/end incorrect - stm32 has %dK sector protection", pic32mx_info->ppage_size);
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285 return ERROR_FLASH_SECTOR_INVALID;
\r
288 /* medium density - each bit refers to a 4bank protection
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289 * high density - each bit refers to a 2bank protection */
\r
290 target_read_u32(target, PIC32MX_FLASH_WRPR, &protection);
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292 prot_reg[0] = (u16)protection;
\r
293 prot_reg[1] = (u16)(protection >> 8);
\r
294 prot_reg[2] = (u16)(protection >> 16);
\r
295 prot_reg[3] = (u16)(protection >> 24);
\r
297 if (pic32mx_info->ppage_size == 2)
\r
299 /* high density flash */
\r
301 /* bit 7 controls sector 62 - 255 protection */
\r
305 prot_reg[3] &= ~(1 << 7);
\r
307 prot_reg[3] |= (1 << 7);
\r
315 for (i = first; i <= last; i++)
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317 reg = (i / pic32mx_info->ppage_size) / 8;
\r
318 bit = (i / pic32mx_info->ppage_size) - (reg * 8);
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321 prot_reg[reg] &= ~(1 << bit);
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323 prot_reg[reg] |= (1 << bit);
\r
328 /* medium density flash */
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329 for (i = first; i <= last; i++)
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331 reg = (i / pic32mx_info->ppage_size) / 8;
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332 bit = (i / pic32mx_info->ppage_size) - (reg * 8);
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335 prot_reg[reg] &= ~(1 << bit);
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337 prot_reg[reg] |= (1 << bit);
\r
341 if ((status = pic32mx_erase_options(bank)) != ERROR_OK)
\r
344 pic32mx_info->option_bytes.protection[0] = prot_reg[0];
\r
345 pic32mx_info->option_bytes.protection[1] = prot_reg[1];
\r
346 pic32mx_info->option_bytes.protection[2] = prot_reg[2];
\r
347 pic32mx_info->option_bytes.protection[3] = prot_reg[3];
\r
349 return pic32mx_write_options(bank);
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355 int pic32mx_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
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357 pic32mx_flash_bank_t *pic32mx_info = bank->driver_priv;
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358 target_t *target = bank->target;
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359 u32 buffer_size = 8192;
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360 working_area_t *source;
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361 u32 address = bank->base + offset;
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362 reg_param_t reg_params[4];
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364 armv7m_algorithm_t armv7m_info;
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365 int retval = ERROR_OK;
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367 u8 pic32mx_flash_write_code[] = {
\r
369 0xDF, 0xF8, 0x24, 0x40, /* ldr r4, PIC32MX_FLASH_CR */
\r
370 0x09, 0x4D, /* ldr r5, PIC32MX_FLASH_SR */
\r
371 0x4F, 0xF0, 0x01, 0x03, /* mov r3, #1 */
\r
372 0x23, 0x60, /* str r3, [r4, #0] */
\r
373 0x30, 0xF8, 0x02, 0x3B, /* ldrh r3, [r0], #2 */
\r
374 0x21, 0xF8, 0x02, 0x3B, /* strh r3, [r1], #2 */
\r
376 0x2B, 0x68, /* ldr r3, [r5, #0] */
\r
377 0x13, 0xF0, 0x01, 0x0F, /* tst r3, #0x01 */
\r
378 0xFB, 0xD0, /* beq busy */
\r
379 0x13, 0xF0, 0x14, 0x0F, /* tst r3, #0x14 */
\r
380 0x01, 0xD1, /* bne exit */
\r
381 0x01, 0x3A, /* subs r2, r2, #1 */
\r
382 0xED, 0xD1, /* bne write */
\r
384 0xFE, 0xE7, /* b exit */
\r
385 0x10, 0x20, 0x02, 0x40, /* PIC32MX_FLASH_CR: .word 0x40022010 */
\r
386 0x0C, 0x20, 0x02, 0x40 /* PIC32MX_FLASH_SR: .word 0x4002200C */
\r
389 /* flash write code */
\r
390 if (target_alloc_working_area(target, sizeof(pic32mx_flash_write_code), &pic32mx_info->write_algorithm) != ERROR_OK)
\r
392 LOG_WARNING("no working area available, can't do block memory writes");
\r
393 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
\r
396 if ((retval=target_write_buffer(target, pic32mx_info->write_algorithm->address, sizeof(pic32mx_flash_write_code), pic32mx_flash_write_code))!=ERROR_OK)
\r
399 /* memory buffer */
\r
400 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
\r
403 if (buffer_size <= 256)
\r
405 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
\r
406 if (pic32mx_info->write_algorithm)
\r
407 target_free_working_area(target, pic32mx_info->write_algorithm);
\r
409 LOG_WARNING("no large enough working area available, can't do block memory writes");
\r
410 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
\r
414 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
\r
415 armv7m_info.core_mode = ARMV7M_MODE_ANY;
\r
417 init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
\r
418 init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
\r
419 init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
\r
420 init_reg_param(®_params[3], "r3", 32, PARAM_IN);
\r
424 u32 thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
\r
426 if ((retval = target_write_buffer(target, source->address, thisrun_count * 2, buffer))!=ERROR_OK)
\r
429 buf_set_u32(reg_params[0].value, 0, 32, source->address);
\r
430 buf_set_u32(reg_params[1].value, 0, 32, address);
\r
431 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
\r
433 if ((retval = target->type->run_algorithm(target, 0, NULL, 4, reg_params, pic32mx_info->write_algorithm->address, \
\r
434 pic32mx_info->write_algorithm->address + (sizeof(pic32mx_flash_write_code) - 10), 10000, &armv7m_info)) != ERROR_OK)
\r
436 LOG_ERROR("error executing pic32mx flash write algorithm");
\r
437 retval = ERROR_FLASH_OPERATION_FAILED;
\r
441 if (buf_get_u32(reg_params[3].value, 0, 32) & 0x14)
\r
443 retval = ERROR_FLASH_OPERATION_FAILED;
\r
447 buffer += thisrun_count * 2;
\r
448 address += thisrun_count * 2;
\r
449 count -= thisrun_count;
\r
452 target_free_working_area(target, source);
\r
453 target_free_working_area(target, pic32mx_info->write_algorithm);
\r
455 destroy_reg_param(®_params[0]);
\r
456 destroy_reg_param(®_params[1]);
\r
457 destroy_reg_param(®_params[2]);
\r
458 destroy_reg_param(®_params[3]);
\r
462 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
\r
466 int pic32mx_write_word(struct flash_bank_s *bank, u32 address, u32 word)
\r
468 target_t *target = bank->target;
\r
470 target_write_u32(target, PIC32MX_NVMADDR, address);
\r
471 target_write_u32(target, PIC32MX_NVMDATA, word);
\r
473 return pic32mx_nvm_exec(bank, NVMCON_OP_WORD_PROG, 5);
\r
476 int pic32mx_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
\r
478 target_t *target = bank->target;
\r
479 u32 words_remaining = (count / 4);
\r
480 u32 bytes_remaining = (count & 0x00000003);
\r
481 u32 address = bank->base + offset;
\r
482 u32 bytes_written = 0;
\r
486 if (bank->target->state != TARGET_HALTED)
\r
488 LOG_ERROR("Target not halted");
\r
489 return ERROR_TARGET_NOT_HALTED;
\r
494 LOG_WARNING("offset 0x%x breaks required 4-byte alignment", offset);
\r
495 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
\r
498 /* multiple words (4-byte) to be programmed? */
\r
499 if (words_remaining > 0)
\r
501 /* try using a block write */
\r
502 if ((retval = pic32mx_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
\r
504 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
\r
506 /* if block write failed (no sufficient working area),
\r
507 * we use normal (slow) single dword accesses */
\r
508 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
\r
510 else if (retval == ERROR_FLASH_OPERATION_FAILED)
\r
512 LOG_ERROR("flash writing failed with error code: 0x%x", retval);
\r
513 return ERROR_FLASH_OPERATION_FAILED;
\r
518 buffer += words_remaining * 4;
\r
519 address += words_remaining * 4;
\r
520 words_remaining = 0;
\r
524 while (words_remaining > 0)
\r
526 status = pic32mx_write_word(bank, address, *(u32*)(buffer + bytes_written));
\r
528 if( status & NVMCON_NVMERR )
\r
529 return ERROR_FLASH_OPERATION_FAILED;
\r
530 if( status & NVMCON_LVDERR )
\r
531 return ERROR_FLASH_OPERATION_FAILED;
\r
533 bytes_written += 4;
\r
538 if (bytes_remaining)
\r
540 u8 last_word[4] = {0xff, 0xff, 0xff, 0xff};
\r
543 while(bytes_remaining > 0)
\r
545 /* Assumes little endian */
\r
546 last_word[i++] = *(buffer + bytes_written);
\r
551 status = pic32mx_write_word(bank, address, *(u32*)last_word);
\r
553 if( status & NVMCON_NVMERR )
\r
554 return ERROR_FLASH_OPERATION_FAILED;
\r
555 if( status & NVMCON_LVDERR )
\r
556 return ERROR_FLASH_OPERATION_FAILED;
\r
562 int pic32mx_probe(struct flash_bank_s *bank)
\r
564 target_t *target = bank->target;
\r
565 pic32mx_flash_bank_t *pic32mx_info = bank->driver_priv;
\r
566 mips32_common_t *mips32 = target->arch_info;
\r
567 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
\r
573 pic32mx_info->probed = 0;
\r
575 device_id = ejtag_info->idcode;
\r
576 LOG_INFO( "device id = 0x%08x (manuf 0x%03x dev 0x%02x, ver 0x%03x)", device_id, (device_id>>1)&0x7ff, (device_id>>12)&0xff, (device_id>>20)&0xfff );
\r
578 if(((device_id>>1)&0x7ff) != PIC32MX_MANUF_ID) {
\r
579 LOG_WARNING( "Cannot identify target as a PIC32MX family." );
\r
580 return ERROR_FLASH_OPERATION_FAILED;
\r
584 if(bank->base == PIC32MX_KSEG1_BOOT_FLASH || bank->base == 1) {
\r
585 /* 0xBFC00000: Boot flash size fixed at 12k */
\r
588 /* 0xBD000000: Program flash size varies with device */
\r
589 for(i=0; pic32mx_devs[i].name != NULL; i++)
\r
590 if(pic32mx_devs[i].devid == ((device_id >> 12) & 0xff)) {
\r
591 num_pages = pic32mx_devs[i].pfm_size;
\r
594 if(pic32mx_devs[i].name == NULL) {
\r
595 LOG_WARNING( "Cannot identify target as a PIC32MX family." );
\r
596 return ERROR_FLASH_OPERATION_FAILED;
\r
601 if (bank->target->state != TARGET_HALTED)
\r
603 LOG_ERROR("Target not halted");
\r
604 return ERROR_TARGET_NOT_HALTED;
\r
607 /* get flash size from target */
\r
608 if (target_read_u16(target, 0x1FFFF7E0, &num_pages) != ERROR_OK)
\r
610 /* failed reading flash size, default to max target family */
\r
611 num_pages = 0xffff;
\r
615 LOG_INFO( "flash size = %dkbytes", num_pages );
\r
617 /* calculate numbers of pages */
\r
618 num_pages /= (page_size / 1024);
\r
620 if(bank->base == 0) bank->base = PIC32MX_KSEG1_PGM_FLASH;
\r
621 if(bank->base == 1) bank->base = PIC32MX_KSEG1_BOOT_FLASH;
\r
622 bank->size = (num_pages * page_size);
\r
623 bank->num_sectors = num_pages;
\r
624 bank->chip_width = 4;
\r
625 bank->bus_width = 4;
\r
626 bank->sectors = malloc(sizeof(flash_sector_t) * num_pages);
\r
628 for (i = 0; i < num_pages; i++)
\r
630 bank->sectors[i].offset = i * page_size;
\r
631 bank->sectors[i].size = page_size;
\r
632 bank->sectors[i].is_erased = -1;
\r
633 bank->sectors[i].is_protected = 1;
\r
636 pic32mx_info->probed = 1;
\r
641 int pic32mx_auto_probe(struct flash_bank_s *bank)
\r
643 pic32mx_flash_bank_t *pic32mx_info = bank->driver_priv;
\r
644 if (pic32mx_info->probed)
\r
646 return pic32mx_probe(bank);
\r
649 int pic32mx_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
\r
654 int pic32mx_info(struct flash_bank_s *bank, char *buf, int buf_size)
\r
656 target_t *target = bank->target;
\r
657 mips32_common_t *mips32 = target->arch_info;
\r
658 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
\r
662 device_id = ejtag_info->idcode;
\r
664 if(((device_id>>1)&0x7ff) != PIC32MX_MANUF_ID) {
\r
665 snprintf(buf, buf_size, "Cannot identify target as a PIC32MX family (manufacturer 0x%03d != 0x%03d)\n", (device_id>>1)&0x7ff, PIC32MX_MANUF_ID);
\r
666 return ERROR_FLASH_OPERATION_FAILED;
\r
668 for(i=0; pic32mx_devs[i].name != NULL; i++)
\r
669 if(pic32mx_devs[i].devid == ((device_id >> 12) & 0xff)) {
\r
670 printed = snprintf(buf, buf_size, "PIC32MX%s", pic32mx_devs[i].name);
\r
673 if(pic32mx_devs[i].name == NULL) {
\r
674 snprintf(buf, buf_size, "Cannot identify target as a PIC32MX family\n");
\r
675 return ERROR_FLASH_OPERATION_FAILED;
\r
678 buf_size -= printed;
\r
679 printed = snprintf(buf, buf_size, " Ver: 0x%03x", (device_id>>20)&0xfff);
\r
685 int pic32mx_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
\r
687 flash_bank_t *bank;
\r
688 target_t *target = NULL;
\r
689 pic32mx_flash_bank_t *pic32mx_info = NULL;
\r
693 command_print(cmd_ctx, "pic32mx lock <bank>");
\r
697 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
\r
700 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
\r
704 pic32mx_info = bank->driver_priv;
\r
706 target = bank->target;
\r
708 if (target->state != TARGET_HALTED)
\r
710 LOG_ERROR("Target not halted");
\r
711 return ERROR_TARGET_NOT_HALTED;
\r
714 if (pic32mx_erase_options(bank) != ERROR_OK)
\r
716 command_print(cmd_ctx, "pic32mx failed to erase options");
\r
720 /* set readout protection */
\r
721 pic32mx_info->option_bytes.RDP = 0;
\r
723 if (pic32mx_write_options(bank) != ERROR_OK)
\r
725 command_print(cmd_ctx, "pic32mx failed to lock device");
\r
729 command_print(cmd_ctx, "pic32mx locked");
\r
734 int pic32mx_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
\r
736 flash_bank_t *bank;
\r
737 target_t *target = NULL;
\r
738 pic32mx_flash_bank_t *pic32mx_info = NULL;
\r
742 command_print(cmd_ctx, "pic32mx unlock <bank>");
\r
746 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
\r
749 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
\r
753 pic32mx_info = bank->driver_priv;
\r
755 target = bank->target;
\r
757 if (target->state != TARGET_HALTED)
\r
759 LOG_ERROR("Target not halted");
\r
760 return ERROR_TARGET_NOT_HALTED;
\r
763 if (pic32mx_erase_options(bank) != ERROR_OK)
\r
765 command_print(cmd_ctx, "pic32mx failed to unlock device");
\r
769 if (pic32mx_write_options(bank) != ERROR_OK)
\r
771 command_print(cmd_ctx, "pic32mx failed to lock device");
\r
775 command_print(cmd_ctx, "pic32mx unlocked");
\r
781 int pic32mx_chip_erase(struct flash_bank_s *bank)
\r
783 target_t *target = bank->target;
\r
786 if (target->state != TARGET_HALTED)
\r
788 LOG_ERROR("Target not halted");
\r
789 return ERROR_TARGET_NOT_HALTED;
\r
792 LOG_INFO("PIC32MX chip erase called");
\r
795 /* unlock option flash registers */
\r
796 target_write_u32(target, PIC32MX_FLASH_KEYR, KEY1);
\r
797 target_write_u32(target, PIC32MX_FLASH_KEYR, KEY2);
\r
799 /* chip erase flash memory */
\r
800 target_write_u32(target, PIC32MX_FLASH_CR, FLASH_MER);
\r
801 target_write_u32(target, PIC32MX_FLASH_CR, FLASH_MER|FLASH_STRT);
\r
803 status = pic32mx_wait_status_busy(bank, 10);
\r
805 target_write_u32(target, PIC32MX_FLASH_CR, FLASH_LOCK);
\r
807 if( status & FLASH_WRPRTERR )
\r
809 LOG_ERROR("pic32mx device protected");
\r
813 if( status & FLASH_PGERR )
\r
815 LOG_ERROR("pic32mx device programming failed");
\r
823 int pic32mx_handle_chip_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
\r
825 flash_bank_t *bank;
\r
831 command_print(cmd_ctx, "pic32mx chip_erase");
\r
835 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
\r
838 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
\r
842 if (pic32mx_chip_erase(bank) == ERROR_OK)
\r
844 /* set all sectors as erased */
\r
845 for (i = 0; i < bank->num_sectors; i++)
\r
847 bank->sectors[i].is_erased = 1;
\r
850 command_print(cmd_ctx, "pic32mx chip erase complete");
\r
854 command_print(cmd_ctx, "pic32mx chip erase failed");
\r
861 int pic32mx_handle_pgm_word_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
\r
863 flash_bank_t *bank;
\r
864 u32 address, value;
\r
870 command_print(cmd_ctx, "pic32mx pgm_word <addr> <value> <bank>");
\r
874 address = strtoul(args[0], NULL, 0);
\r
875 value = strtoul(args[1], NULL, 0);
\r
877 bank = get_flash_bank_by_num(strtoul(args[2], NULL, 0));
\r
880 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[2]);
\r
883 if (address < bank->base || address >= (bank->base+bank->size))
\r
885 command_print(cmd_ctx, "flash address '%s' is out of bounds", args[0]);
\r
890 status = pic32mx_write_word(bank, address, value);
\r
891 if( status & NVMCON_NVMERR )
\r
892 res = ERROR_FLASH_OPERATION_FAILED;
\r
893 if( status & NVMCON_LVDERR )
\r
894 res = ERROR_FLASH_OPERATION_FAILED;
\r
896 if (res == ERROR_OK)
\r
897 command_print(cmd_ctx, "pic32mx pgm word complete");
\r
899 command_print(cmd_ctx, "pic32mx pgm word failed (status=0x%x)", status);
\r