git.sur5r.net Git - openocd/blob - src/flash/s3c2412_nand.c

   1 /* src/flash/s3c2412_nand.c\r
   2  *\r
   3  * S3C2412 OpenOCD NAND Flash controller support.\r
   4  *\r
   5  * Copyright 2007,2008 Ben Dooks <ben@fluff.org>\r
   6  *\r
   7  * This program is free software; you can redistribute it and/or modify\r
   8  * it under the terms of the GNU General Public License as published by\r
   9  * the Free Software Foundation; either version 2 of the License, or\r
  10  * (at your option) any later version.\r
  11  *\r
  12  * Many thanks to Simtec Electronics for sponsoring this work.\r
  13  */\r
  14 \r
  15 #ifdef HAVE_CONFIG_H\r
  16 #include "config.h"\r
  17 #endif\r
  18 \r
  19 #include "replacements.h"\r
  20 #include "log.h"\r
  21 \r
  22 #include <stdlib.h>\r
  23 #include <string.h>\r
  24 \r
  25 #include "nand.h"\r
  26 #include "s3c24xx_nand.h"\r
  27 #include "target.h"\r
  28 \r
  29 int s3c2412_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device);\r
  30 int s3c2412_init(struct nand_device_s *device);\r
  31 \r
  32 nand_flash_controller_t s3c2412_nand_controller =\r
  33 {\r
  34         .name                   = "s3c2412",\r
  35         .nand_device_command    = s3c2412_nand_device_command,\r
  36         .register_commands      = s3c24xx_register_commands,\r
  37         .init                   = s3c2412_init,\r
  38         .reset                  = s3c24xx_reset,\r
  39         .command                = s3c24xx_command,\r
  40         .address                = s3c24xx_address,\r
  41         .write_data             = s3c24xx_write_data,\r
  42         .read_data              = s3c24xx_read_data,\r
  43         .write_page             = s3c24xx_write_page,\r
  44         .read_page              = s3c24xx_read_page,\r
  45         .write_block_data       = s3c2440_write_block_data,\r
  46         .read_block_data        = s3c2440_read_block_data,\r
  47         .controller_ready       = s3c24xx_controller_ready,\r
  48         .nand_ready             = s3c2440_nand_ready,\r
  49 };\r
  50 \r
  51 int s3c2412_nand_device_command(struct command_context_s *cmd_ctx, char *cmd,\r
  52                                 char **args, int argc,\r
  53                                 struct nand_device_s *device)\r
  54 {\r
  55         s3c24xx_nand_controller_t *info;\r
  56 \r
  57         info = s3c24xx_nand_device_command(cmd_ctx, cmd, args, argc, device);\r
  58         if (info == NULL) {\r
  59                 return ERROR_NAND_DEVICE_INVALID;\r
  60         }\r
  61 \r
  62         /* fill in the address fields for the core device */\r
  63         info->cmd = S3C2440_NFCMD;\r
  64         info->addr = S3C2440_NFADDR;\r
  65         info->data = S3C2440_NFDATA;\r
  66         info->nfstat = S3C2412_NFSTAT;\r
  67         \r
  68         return ERROR_OK;\r
  69 }\r
  70 \r
  71 int s3c2412_init(struct nand_device_s *device)\r
  72 {\r
  73         s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;\r
  74         target_t *target = s3c24xx_info->target;\r
  75 \r
  76         target_write_u32(target, S3C2410_NFCONF,\r
  77                          S3C2440_NFCONF_TACLS(3) |\r
  78                          S3C2440_NFCONF_TWRPH0(7) |\r
  79                          S3C2440_NFCONF_TWRPH1(7));\r
  80 \r
  81         target_write_u32(target, S3C2440_NFCONT,\r
  82                          S3C2412_NFCONT_INIT_MAIN_ECC |\r
  83                          S3C2440_NFCONT_ENABLE);\r
  84 \r
  85         return ERROR_OK;\r
  86 }\r