1 /***************************************************************************
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2 * Copyright (C) 2005 by Dominic Rath *
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3 * Dominic.Rath@gmx.de *
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5 * This program is free software; you can redistribute it and/or modify *
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6 * it under the terms of the GNU General Public License as published by *
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7 * the Free Software Foundation; either version 2 of the License, or *
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8 * (at your option) any later version. *
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10 * This program is distributed in the hope that it will be useful, *
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11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
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12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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13 * GNU General Public License for more details. *
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15 * You should have received a copy of the GNU General Public License *
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16 * along with this program; if not, write to the *
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17 * Free Software Foundation, Inc., *
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18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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19 ***************************************************************************/
\r
20 #ifdef HAVE_CONFIG_H
\r
24 #include "replacements.h"
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31 #include "algorithm.h"
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32 #include "binarybuffer.h"
\r
37 int stm32x_register_commands(struct command_context_s *cmd_ctx);
\r
38 int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
\r
39 int stm32x_erase(struct flash_bank_s *bank, int first, int last);
\r
40 int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last);
\r
41 int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
\r
42 int stm32x_probe(struct flash_bank_s *bank);
\r
43 int stm32x_auto_probe(struct flash_bank_s *bank);
\r
44 int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
\r
45 int stm32x_protect_check(struct flash_bank_s *bank);
\r
46 int stm32x_erase_check(struct flash_bank_s *bank);
\r
47 int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size);
\r
49 int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
\r
50 int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
\r
51 int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
\r
52 int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
\r
53 int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
\r
55 flash_driver_t stm32x_flash =
\r
58 .register_commands = stm32x_register_commands,
\r
59 .flash_bank_command = stm32x_flash_bank_command,
\r
60 .erase = stm32x_erase,
\r
61 .protect = stm32x_protect,
\r
62 .write = stm32x_write,
\r
63 .probe = stm32x_probe,
\r
64 .auto_probe = stm32x_auto_probe,
\r
65 .erase_check = stm32x_erase_check,
\r
66 .protect_check = stm32x_protect_check,
\r
70 int stm32x_register_commands(struct command_context_s *cmd_ctx)
\r
72 command_t *stm32x_cmd = register_command(cmd_ctx, NULL, "stm32x", NULL, COMMAND_ANY, "stm32x flash specific commands");
\r
74 register_command(cmd_ctx, stm32x_cmd, "lock", stm32x_handle_lock_command, COMMAND_EXEC,
\r
76 register_command(cmd_ctx, stm32x_cmd, "unlock", stm32x_handle_unlock_command, COMMAND_EXEC,
\r
77 "unlock protected device");
\r
78 register_command(cmd_ctx, stm32x_cmd, "mass_erase", stm32x_handle_mass_erase_command, COMMAND_EXEC,
\r
79 "mass erase device");
\r
80 register_command(cmd_ctx, stm32x_cmd, "options_read", stm32x_handle_options_read_command, COMMAND_EXEC,
\r
81 "read device option bytes");
\r
82 register_command(cmd_ctx, stm32x_cmd, "options_write", stm32x_handle_options_write_command, COMMAND_EXEC,
\r
83 "write device option bytes");
\r
87 /* flash bank stm32x <base> <size> 0 0 <target#>
\r
89 int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
\r
91 stm32x_flash_bank_t *stm32x_info;
\r
95 WARNING("incomplete flash_bank stm32x configuration");
\r
96 return ERROR_FLASH_BANK_INVALID;
\r
99 stm32x_info = malloc(sizeof(stm32x_flash_bank_t));
\r
100 bank->driver_priv = stm32x_info;
\r
102 stm32x_info->write_algorithm = NULL;
\r
103 stm32x_info->probed = 0;
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108 u32 stm32x_get_flash_status(flash_bank_t *bank)
\r
110 target_t *target = bank->target;
\r
113 target_read_u32(target, STM32_FLASH_SR, &status);
\r
118 u32 stm32x_wait_status_busy(flash_bank_t *bank, int timeout)
\r
122 /* wait for busy to clear */
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123 while (((status = stm32x_get_flash_status(bank)) & FLASH_BSY) && (timeout-- > 0))
\r
125 DEBUG("status: 0x%x", status);
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132 int stm32x_read_options(struct flash_bank_s *bank)
\r
135 stm32x_flash_bank_t *stm32x_info = NULL;
\r
136 target_t *target = bank->target;
\r
138 stm32x_info = bank->driver_priv;
\r
140 /* read current option bytes */
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141 target_read_u32(target, STM32_FLASH_OBR, &optiondata);
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143 stm32x_info->option_bytes.user_options = (u16)0xFFF8|((optiondata >> 2) & 0x07);
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144 stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
\r
146 if (optiondata & (1 << OPT_READOUT))
\r
147 INFO("Device Security Bit Set");
\r
149 /* each bit refers to a 4bank protection */
\r
150 target_read_u32(target, STM32_FLASH_WRPR, &optiondata);
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152 stm32x_info->option_bytes.protection[0] = (u16)optiondata;
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153 stm32x_info->option_bytes.protection[1] = (u16)(optiondata >> 8);
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154 stm32x_info->option_bytes.protection[2] = (u16)(optiondata >> 16);
\r
155 stm32x_info->option_bytes.protection[3] = (u16)(optiondata >> 24);
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160 int stm32x_erase_options(struct flash_bank_s *bank)
\r
162 stm32x_flash_bank_t *stm32x_info = NULL;
\r
163 target_t *target = bank->target;
\r
166 stm32x_info = bank->driver_priv;
\r
168 /* read current options */
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169 stm32x_read_options(bank);
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171 /* unlock flash registers */
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172 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
\r
173 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
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175 /* unlock option flash registers */
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176 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
\r
177 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
\r
179 /* erase option bytes */
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180 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_OPTWRE);
\r
181 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_STRT|FLASH_OPTWRE);
\r
183 status = stm32x_wait_status_busy(bank, 10);
\r
185 if( status & FLASH_WRPRTERR )
\r
186 return ERROR_FLASH_OPERATION_FAILED;
\r
187 if( status & FLASH_PGERR )
\r
188 return ERROR_FLASH_OPERATION_FAILED;
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190 /* clear readout protection and complementary option bytes
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191 * this will also force a device unlock if set */
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192 stm32x_info->option_bytes.RDP = 0x5AA5;
\r
197 int stm32x_write_options(struct flash_bank_s *bank)
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199 stm32x_flash_bank_t *stm32x_info = NULL;
\r
200 target_t *target = bank->target;
\r
203 stm32x_info = bank->driver_priv;
\r
205 /* unlock flash registers */
\r
206 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
\r
207 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
\r
209 /* unlock option flash registers */
\r
210 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
\r
211 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
\r
213 /* program option bytes */
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214 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG|FLASH_OPTWRE);
\r
216 /* write user option byte */
\r
217 target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
\r
219 status = stm32x_wait_status_busy(bank, 10);
\r
221 if( status & FLASH_WRPRTERR )
\r
222 return ERROR_FLASH_OPERATION_FAILED;
\r
223 if( status & FLASH_PGERR )
\r
224 return ERROR_FLASH_OPERATION_FAILED;
\r
226 /* write protection byte 1 */
\r
227 target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
\r
229 status = stm32x_wait_status_busy(bank, 10);
\r
231 if( status & FLASH_WRPRTERR )
\r
232 return ERROR_FLASH_OPERATION_FAILED;
\r
233 if( status & FLASH_PGERR )
\r
234 return ERROR_FLASH_OPERATION_FAILED;
\r
236 /* write protection byte 2 */
\r
237 target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
\r
239 status = stm32x_wait_status_busy(bank, 10);
\r
241 if( status & FLASH_WRPRTERR )
\r
242 return ERROR_FLASH_OPERATION_FAILED;
\r
243 if( status & FLASH_PGERR )
\r
244 return ERROR_FLASH_OPERATION_FAILED;
\r
246 /* write protection byte 3 */
\r
247 target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
\r
249 status = stm32x_wait_status_busy(bank, 10);
\r
251 if( status & FLASH_WRPRTERR )
\r
252 return ERROR_FLASH_OPERATION_FAILED;
\r
253 if( status & FLASH_PGERR )
\r
254 return ERROR_FLASH_OPERATION_FAILED;
\r
256 /* write protection byte 4 */
\r
257 target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
\r
259 status = stm32x_wait_status_busy(bank, 10);
\r
261 if( status & FLASH_WRPRTERR )
\r
262 return ERROR_FLASH_OPERATION_FAILED;
\r
263 if( status & FLASH_PGERR )
\r
264 return ERROR_FLASH_OPERATION_FAILED;
\r
266 /* write readout protection bit */
\r
267 target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
\r
269 status = stm32x_wait_status_busy(bank, 10);
\r
271 if( status & FLASH_WRPRTERR )
\r
272 return ERROR_FLASH_OPERATION_FAILED;
\r
273 if( status & FLASH_PGERR )
\r
274 return ERROR_FLASH_OPERATION_FAILED;
\r
276 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
\r
281 int stm32x_blank_check(struct flash_bank_s *bank, int first, int last)
\r
283 target_t *target = bank->target;
\r
288 if ((first < 0) || (last > bank->num_sectors))
\r
289 return ERROR_FLASH_SECTOR_INVALID;
\r
291 if (target->state != TARGET_HALTED)
\r
293 return ERROR_TARGET_NOT_HALTED;
\r
296 buffer = malloc(256);
\r
298 for (i = first; i <= last; i++)
\r
300 bank->sectors[i].is_erased = 1;
\r
302 target->type->read_memory(target, bank->base + bank->sectors[i].offset, 4, 256/4, buffer);
\r
304 for (nBytes = 0; nBytes < 256; nBytes++)
\r
306 if (buffer[nBytes] != 0xFF)
\r
308 bank->sectors[i].is_erased = 0;
\r
319 int stm32x_protect_check(struct flash_bank_s *bank)
\r
321 target_t *target = bank->target;
\r
327 if (target->state != TARGET_HALTED)
\r
329 return ERROR_TARGET_NOT_HALTED;
\r
332 /* each bit refers to a 4bank protection */
\r
333 target_read_u32(target, STM32_FLASH_WRPR, &protection);
\r
335 /* each protection bit is for 4 1K pages */
\r
336 num_bits = (bank->num_sectors / 4);
\r
338 for (i = 0; i < num_bits; i++)
\r
342 if( protection & (1 << i))
\r
345 for (s = 0; s < 4; s++)
\r
346 bank->sectors[(i * 4) + s].is_protected = set;
\r
352 int stm32x_erase(struct flash_bank_s *bank, int first, int last)
\r
354 target_t *target = bank->target;
\r
359 /* unlock flash registers */
\r
360 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
\r
361 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
\r
363 for (i = first; i <= last; i++)
\r
365 target_write_u32(target, STM32_FLASH_CR, FLASH_PER);
\r
366 target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);
\r
367 target_write_u32(target, STM32_FLASH_CR, FLASH_PER|FLASH_STRT);
\r
369 status = stm32x_wait_status_busy(bank, 10);
\r
371 if( status & FLASH_WRPRTERR )
\r
372 return ERROR_FLASH_OPERATION_FAILED;
\r
373 if( status & FLASH_PGERR )
\r
374 return ERROR_FLASH_OPERATION_FAILED;
\r
375 bank->sectors[i].is_erased = 1;
\r
378 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
\r
383 int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last)
\r
385 stm32x_flash_bank_t *stm32x_info = NULL;
\r
386 target_t *target = bank->target;
\r
387 u16 prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
\r
392 stm32x_info = bank->driver_priv;
\r
394 if (target->state != TARGET_HALTED)
\r
396 return ERROR_TARGET_NOT_HALTED;
\r
399 if ((first && (first % 4)) || ((last + 1) && (last + 1) % 4))
\r
401 WARNING("sector start/end incorrect - stm32 has 4K sector protection");
\r
402 return ERROR_FLASH_SECTOR_INVALID;
\r
405 /* each bit refers to a 4bank protection */
\r
406 target_read_u32(target, STM32_FLASH_WRPR, &protection);
\r
408 prot_reg[0] = (u16)protection;
\r
409 prot_reg[1] = (u16)(protection >> 8);
\r
410 prot_reg[2] = (u16)(protection >> 16);
\r
411 prot_reg[3] = (u16)(protection >> 24);
\r
413 for (i = first; i <= last; i++)
\r
416 bit = (i / 4) - (reg * 8);
\r
419 prot_reg[reg] &= ~(1 << bit);
\r
421 prot_reg[reg] |= (1 << bit);
\r
424 if ((status = stm32x_erase_options(bank)) != ERROR_OK)
\r
427 stm32x_info->option_bytes.protection[0] = prot_reg[0];
\r
428 stm32x_info->option_bytes.protection[1] = prot_reg[1];
\r
429 stm32x_info->option_bytes.protection[2] = prot_reg[2];
\r
430 stm32x_info->option_bytes.protection[3] = prot_reg[3];
\r
432 return stm32x_write_options(bank);
\r
435 int stm32x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
\r
437 stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
\r
438 target_t *target = bank->target;
\r
439 u32 buffer_size = 8192;
\r
440 working_area_t *source;
\r
441 u32 address = bank->base + offset;
\r
442 reg_param_t reg_params[4];
\r
443 armv7m_algorithm_t armv7m_info;
\r
444 int retval = ERROR_OK;
\r
446 u8 stm32x_flash_write_code[] = {
\r
448 0xDF, 0xF8, 0x24, 0x40, /* ldr r4, STM32_FLASH_CR */
\r
449 0x09, 0x4D, /* ldr r5, STM32_FLASH_SR */
\r
450 0x4F, 0xF0, 0x01, 0x03, /* mov r3, #1 */
\r
451 0x23, 0x60, /* str r3, [r4, #0] */
\r
452 0x30, 0xF8, 0x02, 0x3B, /* ldrh r3, [r0], #2 */
\r
453 0x21, 0xF8, 0x02, 0x3B, /* strh r3, [r1], #2 */
\r
455 0x2B, 0x68, /* ldr r3, [r5, #0] */
\r
456 0x13, 0xF0, 0x01, 0x0F, /* tst r3, #0x01 */
\r
457 0xFB, 0xD0, /* beq busy */
\r
458 0x13, 0xF0, 0x14, 0x0F, /* tst r3, #0x14 */
\r
459 0x01, 0xD1, /* bne exit */
\r
460 0x01, 0x3A, /* subs r2, r2, #1 */
\r
461 0xED, 0xD1, /* bne write */
\r
463 0xFE, 0xE7, /* b exit */
\r
464 0x10, 0x20, 0x02, 0x40, /* STM32_FLASH_CR: .word 0x40022010 */
\r
465 0x0C, 0x20, 0x02, 0x40 /* STM32_FLASH_SR: .word 0x4002200C */
\r
468 /* flash write code */
\r
469 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code), &stm32x_info->write_algorithm) != ERROR_OK)
\r
471 WARNING("no working area available, can't do block memory writes");
\r
472 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
\r
475 target_write_buffer(target, stm32x_info->write_algorithm->address, sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
\r
477 /* memory buffer */
\r
478 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
\r
481 if (buffer_size <= 256)
\r
483 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
\r
484 if (stm32x_info->write_algorithm)
\r
485 target_free_working_area(target, stm32x_info->write_algorithm);
\r
487 WARNING("no large enough working area available, can't do block memory writes");
\r
488 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
\r
492 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
\r
493 armv7m_info.core_mode = ARMV7M_MODE_ANY;
\r
494 armv7m_info.core_state = ARMV7M_STATE_THUMB;
\r
496 init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
\r
497 init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
\r
498 init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
\r
499 init_reg_param(®_params[3], "r3", 32, PARAM_IN);
\r
503 u32 thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
\r
505 target_write_buffer(target, source->address, thisrun_count * 2, buffer);
\r
507 buf_set_u32(reg_params[0].value, 0, 32, source->address);
\r
508 buf_set_u32(reg_params[1].value, 0, 32, address);
\r
509 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
\r
511 if ((retval = target->type->run_algorithm(target, 0, NULL, 4, reg_params, stm32x_info->write_algorithm->address, \
\r
512 stm32x_info->write_algorithm->address + (sizeof(stm32x_flash_write_code) - 10), 10000, &armv7m_info)) != ERROR_OK)
\r
514 ERROR("error executing str7x flash write algorithm");
\r
518 if (buf_get_u32(reg_params[3].value, 0, 32) & 0x14)
\r
520 retval = ERROR_FLASH_OPERATION_FAILED;
\r
524 buffer += thisrun_count * 2;
\r
525 address += thisrun_count * 2;
\r
526 count -= thisrun_count;
\r
529 target_free_working_area(target, source);
\r
530 target_free_working_area(target, stm32x_info->write_algorithm);
\r
532 destroy_reg_param(®_params[0]);
\r
533 destroy_reg_param(®_params[1]);
\r
534 destroy_reg_param(®_params[2]);
\r
535 destroy_reg_param(®_params[3]);
\r
540 int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
\r
542 target_t *target = bank->target;
\r
543 u32 words_remaining = (count / 2);
\r
544 u32 bytes_remaining = (count & 0x00000001);
\r
545 u32 address = bank->base + offset;
\r
546 u32 bytes_written = 0;
\r
552 WARNING("offset 0x%x breaks required 2-byte alignment", offset);
\r
553 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
\r
556 /* unlock flash registers */
\r
557 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
\r
558 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
\r
560 /* multiple half words (2-byte) to be programmed? */
\r
561 if (words_remaining > 0)
\r
563 /* try using a block write */
\r
564 if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
\r
566 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
\r
568 /* if block write failed (no sufficient working area),
\r
569 * we use normal (slow) single dword accesses */
\r
570 WARNING("couldn't use block writes, falling back to single memory accesses");
\r
572 else if (retval == ERROR_FLASH_OPERATION_FAILED)
\r
574 ERROR("flash writing failed with error code: 0x%x", retval);
\r
575 return ERROR_FLASH_OPERATION_FAILED;
\r
580 buffer += words_remaining * 2;
\r
581 address += words_remaining * 2;
\r
582 words_remaining = 0;
\r
586 while (words_remaining > 0)
\r
588 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
\r
589 target_write_u16(target, address, *(u16*)(buffer + bytes_written));
\r
591 status = stm32x_wait_status_busy(bank, 5);
\r
593 if( status & FLASH_WRPRTERR )
\r
594 return ERROR_FLASH_OPERATION_FAILED;
\r
595 if( status & FLASH_PGERR )
\r
596 return ERROR_FLASH_OPERATION_FAILED;
\r
598 bytes_written += 2;
\r
603 if (bytes_remaining)
\r
605 u8 last_halfword[2] = {0xff, 0xff};
\r
608 while(bytes_remaining > 0)
\r
610 last_halfword[i++] = *(buffer + bytes_written);
\r
615 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
\r
616 target_write_u16(target, address, *(u16*)last_halfword);
\r
618 status = stm32x_wait_status_busy(bank, 5);
\r
620 if( status & FLASH_WRPRTERR )
\r
621 return ERROR_FLASH_OPERATION_FAILED;
\r
622 if( status & FLASH_PGERR )
\r
623 return ERROR_FLASH_OPERATION_FAILED;
\r
626 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
\r
631 int stm32x_probe(struct flash_bank_s *bank)
\r
633 target_t *target = bank->target;
\r
634 stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
\r
639 stm32x_info->probed = 0;
\r
641 /* read stm32 device id register */
\r
642 target_read_u32(target, 0xE0042000, &device_id);
\r
643 INFO( "device id = 0x%08x", device_id );
\r
645 if (!(device_id & 0x410))
\r
647 WARNING( "Cannot identify target as a STM32 family." );
\r
648 return ERROR_FLASH_OPERATION_FAILED;
\r
651 /* get flash size from target */
\r
652 target_read_u16(target, 0x1FFFF7E0, &num_sectors);
\r
654 /* check for early silicon rev A */
\r
655 if ((device_id >> 16) == 0 )
\r
657 /* number of sectors incorrect on revA */
\r
658 WARNING( "STM32 Rev A Silicon detected, probe inaccurate - assuming 128k flash" );
\r
662 INFO( "flash size = %dkbytes", num_sectors );
\r
664 bank->base = 0x08000000;
\r
665 bank->size = num_sectors * 1024;
\r
666 bank->num_sectors = num_sectors;
\r
667 bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
\r
669 for (i = 0; i < num_sectors; i++)
\r
671 bank->sectors[i].offset = i * 1024;
\r
672 bank->sectors[i].size = 1024;
\r
673 bank->sectors[i].is_erased = -1;
\r
674 bank->sectors[i].is_protected = 1;
\r
677 stm32x_info->probed = 1;
\r
682 int stm32x_auto_probe(struct flash_bank_s *bank)
\r
684 stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
\r
685 if (stm32x_info->probed)
\r
687 return stm32x_probe(bank);
\r
690 int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
\r
695 int stm32x_erase_check(struct flash_bank_s *bank)
\r
697 return stm32x_blank_check(bank, 0, bank->num_sectors - 1);
\r
700 int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size)
\r
702 snprintf(buf, buf_size, "stm32x flash driver info" );
\r
706 int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
\r
708 flash_bank_t *bank;
\r
709 target_t *target = NULL;
\r
710 stm32x_flash_bank_t *stm32x_info = NULL;
\r
714 command_print(cmd_ctx, "stm32x lock <bank>");
\r
718 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
\r
721 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
\r
725 stm32x_info = bank->driver_priv;
\r
727 target = bank->target;
\r
729 if (target->state != TARGET_HALTED)
\r
731 return ERROR_TARGET_NOT_HALTED;
\r
734 if (stm32x_erase_options(bank) != ERROR_OK)
\r
736 command_print(cmd_ctx, "stm32x failed to erase options");
\r
740 /* set readout protection */
\r
741 stm32x_info->option_bytes.RDP = 0;
\r
743 if (stm32x_write_options(bank) != ERROR_OK)
\r
745 command_print(cmd_ctx, "stm32x failed to lock device");
\r
749 command_print(cmd_ctx, "stm32x locked");
\r
754 int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
\r
756 flash_bank_t *bank;
\r
757 target_t *target = NULL;
\r
758 stm32x_flash_bank_t *stm32x_info = NULL;
\r
762 command_print(cmd_ctx, "stm32x unlock <bank>");
\r
766 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
\r
769 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
\r
773 stm32x_info = bank->driver_priv;
\r
775 target = bank->target;
\r
777 if (target->state != TARGET_HALTED)
\r
779 return ERROR_TARGET_NOT_HALTED;
\r
782 if (stm32x_erase_options(bank) != ERROR_OK)
\r
784 command_print(cmd_ctx, "stm32x failed to unlock device");
\r
788 if (stm32x_write_options(bank) != ERROR_OK)
\r
790 command_print(cmd_ctx, "stm32x failed to lock device");
\r
794 command_print(cmd_ctx, "stm32x unlocked");
\r
799 int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
\r
801 flash_bank_t *bank;
\r
803 target_t *target = NULL;
\r
804 stm32x_flash_bank_t *stm32x_info = NULL;
\r
808 command_print(cmd_ctx, "stm32x options_read <bank>");
\r
812 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
\r
815 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
\r
819 stm32x_info = bank->driver_priv;
\r
821 target = bank->target;
\r
823 if (target->state != TARGET_HALTED)
\r
825 return ERROR_TARGET_NOT_HALTED;
\r
828 target_read_u32(target, STM32_FLASH_OBR, &optionbyte);
\r
829 command_print(cmd_ctx, "Option Byte: 0x%x", optionbyte);
\r
831 if (buf_get_u32((u8*)&optionbyte, OPT_ERROR, 1))
\r
832 command_print(cmd_ctx, "Option Byte Complement Error");
\r
834 if (buf_get_u32((u8*)&optionbyte, OPT_READOUT, 1))
\r
835 command_print(cmd_ctx, "Readout Protection On");
\r
837 command_print(cmd_ctx, "Readout Protection Off");
\r
839 if (buf_get_u32((u8*)&optionbyte, OPT_RDWDGSW, 1))
\r
840 command_print(cmd_ctx, "Software Watchdog");
\r
842 command_print(cmd_ctx, "Hardware Watchdog");
\r
844 if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTOP, 1))
\r
845 command_print(cmd_ctx, "Stop: No reset generated");
\r
847 command_print(cmd_ctx, "Stop: Reset generated");
\r
849 if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTDBY, 1))
\r
850 command_print(cmd_ctx, "Standby: No reset generated");
\r
852 command_print(cmd_ctx, "Standby: Reset generated");
\r
857 int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
\r
859 flash_bank_t *bank;
\r
860 target_t *target = NULL;
\r
861 stm32x_flash_bank_t *stm32x_info = NULL;
\r
862 u16 optionbyte = 0xF8;
\r
866 command_print(cmd_ctx, "stm32x options_write <bank> <SWWDG|HWWDG> <RSTSTNDBY|NORSTSTNDBY> <RSTSTOP|NORSTSTOP>");
\r
870 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
\r
873 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
\r
877 stm32x_info = bank->driver_priv;
\r
879 target = bank->target;
\r
881 if (target->state != TARGET_HALTED)
\r
883 return ERROR_TARGET_NOT_HALTED;
\r
886 if (strcmp(args[1], "SWWDG") == 0)
\r
888 optionbyte |= (1<<0);
\r
892 optionbyte &= ~(1<<0);
\r
895 if (strcmp(args[2], "NORSTSTNDBY") == 0)
\r
897 optionbyte |= (1<<1);
\r
901 optionbyte &= ~(1<<1);
\r
904 if (strcmp(args[3], "NORSTSTOP") == 0)
\r
906 optionbyte |= (1<<2);
\r
910 optionbyte &= ~(1<<2);
\r
913 if (stm32x_erase_options(bank) != ERROR_OK)
\r
915 command_print(cmd_ctx, "stm32x failed to erase options");
\r
919 stm32x_info->option_bytes.user_options = optionbyte;
\r
921 if (stm32x_write_options(bank) != ERROR_OK)
\r
923 command_print(cmd_ctx, "stm32x failed to write options");
\r
927 command_print(cmd_ctx, "stm32x write options complete");
\r
932 int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
\r
934 target_t *target = NULL;
\r
935 stm32x_flash_bank_t *stm32x_info = NULL;
\r
936 flash_bank_t *bank;
\r
941 command_print(cmd_ctx, "stm32x mass_erase <bank>");
\r
945 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
\r
948 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
\r
952 stm32x_info = bank->driver_priv;
\r
954 target = bank->target;
\r
956 if (target->state != TARGET_HALTED)
\r
958 return ERROR_TARGET_NOT_HALTED;
\r
961 /* unlock option flash registers */
\r
962 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
\r
963 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
\r
965 /* mass erase flash memory */
\r
966 target_write_u32(target, STM32_FLASH_CR, FLASH_MER);
\r
967 target_write_u32(target, STM32_FLASH_CR, FLASH_MER|FLASH_STRT);
\r
969 status = stm32x_wait_status_busy(bank, 10);
\r
971 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
\r
973 if( status & FLASH_WRPRTERR )
\r
975 command_print(cmd_ctx, "stm32x device protected");
\r
979 if( status & FLASH_PGERR )
\r
981 command_print(cmd_ctx, "stm32x device programming failed");
\r
985 command_print(cmd_ctx, "stm32x mass erase complete");
\r