1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "replacements.h"
31 #include "algorithm.h"
32 #include "binarybuffer.h"
37 int stm32x_register_commands(struct command_context_s *cmd_ctx);
38 int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
39 int stm32x_erase(struct flash_bank_s *bank, int first, int last);
40 int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last);
41 int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
42 int stm32x_probe(struct flash_bank_s *bank);
43 int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
44 int stm32x_protect_check(struct flash_bank_s *bank);
45 int stm32x_erase_check(struct flash_bank_s *bank);
46 int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size);
48 int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
49 int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
50 int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
51 int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
52 int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
54 flash_driver_t stm32x_flash =
57 .register_commands = stm32x_register_commands,
58 .flash_bank_command = stm32x_flash_bank_command,
59 .erase = stm32x_erase,
60 .protect = stm32x_protect,
61 .write = stm32x_write,
62 .probe = stm32x_probe,
63 .erase_check = stm32x_erase_check,
64 .protect_check = stm32x_protect_check,
68 int stm32x_register_commands(struct command_context_s *cmd_ctx)
70 command_t *stm32x_cmd = register_command(cmd_ctx, NULL, "stm32x", NULL, COMMAND_ANY, "stm32x flash specific commands");
72 register_command(cmd_ctx, stm32x_cmd, "lock", stm32x_handle_lock_command, COMMAND_EXEC,
74 register_command(cmd_ctx, stm32x_cmd, "unlock", stm32x_handle_unlock_command, COMMAND_EXEC,
75 "unlock protected device");
76 register_command(cmd_ctx, stm32x_cmd, "mass_erase", stm32x_handle_mass_erase_command, COMMAND_EXEC,
78 register_command(cmd_ctx, stm32x_cmd, "options_read", stm32x_handle_options_read_command, COMMAND_EXEC,
79 "read device option bytes");
80 register_command(cmd_ctx, stm32x_cmd, "options_write", stm32x_handle_options_write_command, COMMAND_EXEC,
81 "write device option bytes");
85 int stm32x_build_block_list(struct flash_bank_s *bank)
102 ERROR("BUG: unknown bank->size encountered");
106 bank->num_sectors = num_sectors;
107 bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
109 for (i = 0; i < num_sectors; i++)
111 bank->sectors[i].offset = i * 1024;
112 bank->sectors[i].size = 1024;
113 bank->sectors[i].is_erased = -1;
114 bank->sectors[i].is_protected = 1;
120 /* flash bank stm32x <base> <size> 0 0 <target#>
122 int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
124 stm32x_flash_bank_t *stm32x_info;
128 WARNING("incomplete flash_bank stm32x configuration");
129 return ERROR_FLASH_BANK_INVALID;
132 stm32x_info = malloc(sizeof(stm32x_flash_bank_t));
133 bank->driver_priv = stm32x_info;
135 if (bank->base != 0x08000000)
137 WARNING("overriding flash base address for STM32x device with 0x08000000");
138 bank->base = 0x08000000;
141 stm32x_build_block_list(bank);
143 stm32x_info->write_algorithm = NULL;
148 u32 stm32x_get_flash_status(flash_bank_t *bank)
150 target_t *target = bank->target;
153 target_read_u32(target, STM32_FLASH_SR, &status);
158 u32 stm32x_wait_status_busy(flash_bank_t *bank, int timeout)
162 /* wait for busy to clear */
163 while (((status = stm32x_get_flash_status(bank)) & FLASH_BSY) && (timeout-- > 0))
165 DEBUG("status: 0x%x", status);
172 int stm32x_read_options(struct flash_bank_s *bank)
175 stm32x_flash_bank_t *stm32x_info = NULL;
176 target_t *target = bank->target;
178 stm32x_info = bank->driver_priv;
180 /* read current option bytes */
181 target_read_u32(target, STM32_FLASH_OBR, &optiondata);
183 stm32x_info->option_bytes.user_options = (u16)0xFFF8|((optiondata >> 2) & 0x07);
184 stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
186 if (optiondata & (1 << OPT_READOUT))
187 INFO("Device Security Bit Set");
189 /* each bit refers to a 4bank protection */
190 target_read_u32(target, STM32_FLASH_WRPR, &optiondata);
192 stm32x_info->option_bytes.protection[0] = (u16)optiondata;
193 stm32x_info->option_bytes.protection[1] = (u16)(optiondata >> 8);
194 stm32x_info->option_bytes.protection[2] = (u16)(optiondata >> 16);
195 stm32x_info->option_bytes.protection[3] = (u16)(optiondata >> 24);
200 int stm32x_erase_options(struct flash_bank_s *bank)
202 stm32x_flash_bank_t *stm32x_info = NULL;
203 target_t *target = bank->target;
206 stm32x_info = bank->driver_priv;
208 /* read current options */
209 stm32x_read_options(bank);
211 /* unlock flash registers */
212 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
213 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
215 /* unlock option flash registers */
216 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
217 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
219 /* erase option bytes */
220 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_OPTWRE);
221 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_STRT|FLASH_OPTWRE);
223 status = stm32x_wait_status_busy(bank, 10);
225 if( status & FLASH_WRPRTERR )
226 return ERROR_FLASH_OPERATION_FAILED;
227 if( status & FLASH_PGERR )
228 return ERROR_FLASH_OPERATION_FAILED;
230 /* clear readout protection and complementary option bytes
231 * this will also force a device unlock if set */
232 stm32x_info->option_bytes.RDP = 0x5AA5;
237 int stm32x_write_options(struct flash_bank_s *bank)
239 stm32x_flash_bank_t *stm32x_info = NULL;
240 target_t *target = bank->target;
243 stm32x_info = bank->driver_priv;
245 /* unlock flash registers */
246 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
247 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
249 /* unlock option flash registers */
250 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
251 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
253 /* program option bytes */
254 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG|FLASH_OPTWRE);
256 /* write user option byte */
257 target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
259 status = stm32x_wait_status_busy(bank, 10);
261 if( status & FLASH_WRPRTERR )
262 return ERROR_FLASH_OPERATION_FAILED;
263 if( status & FLASH_PGERR )
264 return ERROR_FLASH_OPERATION_FAILED;
266 /* write protection byte 1 */
267 target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
269 status = stm32x_wait_status_busy(bank, 10);
271 if( status & FLASH_WRPRTERR )
272 return ERROR_FLASH_OPERATION_FAILED;
273 if( status & FLASH_PGERR )
274 return ERROR_FLASH_OPERATION_FAILED;
276 /* write protection byte 2 */
277 target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
279 status = stm32x_wait_status_busy(bank, 10);
281 if( status & FLASH_WRPRTERR )
282 return ERROR_FLASH_OPERATION_FAILED;
283 if( status & FLASH_PGERR )
284 return ERROR_FLASH_OPERATION_FAILED;
286 /* write protection byte 3 */
287 target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
289 status = stm32x_wait_status_busy(bank, 10);
291 if( status & FLASH_WRPRTERR )
292 return ERROR_FLASH_OPERATION_FAILED;
293 if( status & FLASH_PGERR )
294 return ERROR_FLASH_OPERATION_FAILED;
296 /* write protection byte 4 */
297 target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
299 status = stm32x_wait_status_busy(bank, 10);
301 if( status & FLASH_WRPRTERR )
302 return ERROR_FLASH_OPERATION_FAILED;
303 if( status & FLASH_PGERR )
304 return ERROR_FLASH_OPERATION_FAILED;
306 /* write readout protection bit */
307 target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
309 status = stm32x_wait_status_busy(bank, 10);
311 if( status & FLASH_WRPRTERR )
312 return ERROR_FLASH_OPERATION_FAILED;
313 if( status & FLASH_PGERR )
314 return ERROR_FLASH_OPERATION_FAILED;
316 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
321 int stm32x_blank_check(struct flash_bank_s *bank, int first, int last)
323 target_t *target = bank->target;
328 if ((first < 0) || (last > bank->num_sectors))
329 return ERROR_FLASH_SECTOR_INVALID;
331 if (target->state != TARGET_HALTED)
333 return ERROR_TARGET_NOT_HALTED;
336 buffer = malloc(256);
338 for (i = first; i <= last; i++)
340 bank->sectors[i].is_erased = 1;
342 target->type->read_memory(target, bank->base + bank->sectors[i].offset, 4, 256/4, buffer);
344 for (nBytes = 0; nBytes < 256; nBytes++)
346 if (buffer[nBytes] != 0xFF)
348 bank->sectors[i].is_erased = 0;
359 int stm32x_protect_check(struct flash_bank_s *bank)
361 target_t *target = bank->target;
367 if (target->state != TARGET_HALTED)
369 return ERROR_TARGET_NOT_HALTED;
372 /* each bit refers to a 4bank protection */
373 target_read_u32(target, STM32_FLASH_WRPR, &protection);
375 /* each protection bit is for 4 1K pages */
376 num_bits = (bank->num_sectors / 4);
378 for (i = 0; i < num_bits; i++)
382 if( protection & (1 << i))
385 for (s = 0; s < 4; s++)
386 bank->sectors[(i * 4) + s].is_protected = set;
392 int stm32x_erase(struct flash_bank_s *bank, int first, int last)
394 target_t *target = bank->target;
399 if (target->state != TARGET_HALTED)
401 return ERROR_TARGET_NOT_HALTED;
404 /* unlock flash registers */
405 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
406 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
408 for (i = first; i <= last; i++)
410 target_write_u32(target, STM32_FLASH_CR, FLASH_PER);
411 target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);
412 target_write_u32(target, STM32_FLASH_CR, FLASH_PER|FLASH_STRT);
414 status = stm32x_wait_status_busy(bank, 10);
416 if( status & FLASH_WRPRTERR )
417 return ERROR_FLASH_OPERATION_FAILED;
418 if( status & FLASH_PGERR )
419 return ERROR_FLASH_OPERATION_FAILED;
420 bank->sectors[i].is_erased = 1;
423 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
428 int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last)
430 stm32x_flash_bank_t *stm32x_info = NULL;
431 target_t *target = bank->target;
432 u16 prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
437 stm32x_info = bank->driver_priv;
439 if (target->state != TARGET_HALTED)
441 return ERROR_TARGET_NOT_HALTED;
444 if ((first && (first % 4)) || ((last + 1) && (last + 1) % 4))
446 WARNING("sector start/end incorrect - stm32 has 4K sector protection");
447 return ERROR_FLASH_SECTOR_INVALID;
450 /* each bit refers to a 4bank protection */
451 target_read_u32(target, STM32_FLASH_WRPR, &protection);
453 prot_reg[0] = (u16)protection;
454 prot_reg[1] = (u16)(protection >> 8);
455 prot_reg[2] = (u16)(protection >> 16);
456 prot_reg[3] = (u16)(protection >> 24);
458 for (i = first; i <= last; i++)
461 bit = (i / 4) - (reg * 8);
464 prot_reg[reg] &= ~(1 << bit);
466 prot_reg[reg] |= (1 << bit);
469 if ((status = stm32x_erase_options(bank)) != ERROR_OK)
472 stm32x_info->option_bytes.protection[0] = prot_reg[0];
473 stm32x_info->option_bytes.protection[1] = prot_reg[1];
474 stm32x_info->option_bytes.protection[2] = prot_reg[2];
475 stm32x_info->option_bytes.protection[3] = prot_reg[3];
477 return stm32x_write_options(bank);
480 int stm32x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
482 stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
483 target_t *target = bank->target;
484 u32 buffer_size = 8192;
485 working_area_t *source;
486 u32 address = bank->base + offset;
487 reg_param_t reg_params[4];
488 armv7m_algorithm_t armv7m_info;
489 int retval = ERROR_OK;
491 u8 stm32x_flash_write_code[] = {
493 0xDF, 0xF8, 0x24, 0x40, /* ldr r4, STM32_FLASH_CR */
494 0x09, 0x4D, /* ldr r5, STM32_FLASH_SR */
495 0x4F, 0xF0, 0x01, 0x03, /* mov r3, #1 */
496 0x23, 0x60, /* str r3, [r4, #0] */
497 0x30, 0xF8, 0x02, 0x3B, /* ldrh r3, [r0], #2 */
498 0x21, 0xF8, 0x02, 0x3B, /* strh r3, [r1], #2 */
500 0x2B, 0x68, /* ldr r3, [r5, #0] */
501 0x13, 0xF0, 0x01, 0x0F, /* tst r3, #0x01 */
502 0xFB, 0xD0, /* beq busy */
503 0x13, 0xF0, 0x14, 0x0F, /* tst r3, #0x14 */
504 0x01, 0xD1, /* bne exit */
505 0x01, 0x3A, /* subs r2, r2, #1 */
506 0xED, 0xD1, /* bne write */
508 0xFE, 0xE7, /* b exit */
509 0x10, 0x20, 0x02, 0x40, /* STM32_FLASH_CR: .word 0x40022010 */
510 0x0C, 0x20, 0x02, 0x40 /* STM32_FLASH_SR: .word 0x4002200C */
513 /* flash write code */
514 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code), &stm32x_info->write_algorithm) != ERROR_OK)
516 WARNING("no working area available, can't do block memory writes");
517 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
520 target_write_buffer(target, stm32x_info->write_algorithm->address, sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
523 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
526 if (buffer_size <= 256)
528 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
529 if (stm32x_info->write_algorithm)
530 target_free_working_area(target, stm32x_info->write_algorithm);
532 WARNING("no large enough working area available, can't do block memory writes");
533 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
537 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
538 armv7m_info.core_mode = ARMV7M_MODE_ANY;
539 armv7m_info.core_state = ARMV7M_STATE_THUMB;
541 init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
542 init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
543 init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
544 init_reg_param(®_params[3], "r3", 32, PARAM_IN);
548 u32 thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
550 target_write_buffer(target, source->address, thisrun_count * 2, buffer);
552 buf_set_u32(reg_params[0].value, 0, 32, source->address);
553 buf_set_u32(reg_params[1].value, 0, 32, address);
554 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
556 if ((retval = target->type->run_algorithm(target, 0, NULL, 4, reg_params, stm32x_info->write_algorithm->address, \
557 stm32x_info->write_algorithm->address + (sizeof(stm32x_flash_write_code) - 10), 10000, &armv7m_info)) != ERROR_OK)
559 ERROR("error executing str7x flash write algorithm");
563 if (buf_get_u32(reg_params[3].value, 0, 32) & 0x14)
565 retval = ERROR_FLASH_OPERATION_FAILED;
569 buffer += thisrun_count * 2;
570 address += thisrun_count * 2;
571 count -= thisrun_count;
574 target_free_working_area(target, source);
575 target_free_working_area(target, stm32x_info->write_algorithm);
577 destroy_reg_param(®_params[0]);
578 destroy_reg_param(®_params[1]);
579 destroy_reg_param(®_params[2]);
580 destroy_reg_param(®_params[3]);
585 int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
587 target_t *target = bank->target;
588 u32 words_remaining = (count / 2);
589 u32 bytes_remaining = (count & 0x00000001);
590 u32 address = bank->base + offset;
591 u32 bytes_written = 0;
595 if (target->state != TARGET_HALTED)
597 return ERROR_TARGET_NOT_HALTED;
602 WARNING("offset 0x%x breaks required 2-byte alignment", offset);
603 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
606 /* unlock flash registers */
607 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
608 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
610 /* multiple half words (2-byte) to be programmed? */
611 if (words_remaining > 0)
613 /* try using a block write */
614 if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
616 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
618 /* if block write failed (no sufficient working area),
619 * we use normal (slow) single dword accesses */
620 WARNING("couldn't use block writes, falling back to single memory accesses");
622 else if (retval == ERROR_FLASH_OPERATION_FAILED)
624 ERROR("flash writing failed with error code: 0x%x", retval);
625 return ERROR_FLASH_OPERATION_FAILED;
630 buffer += words_remaining * 2;
631 address += words_remaining * 2;
636 while (words_remaining > 0)
638 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
639 target_write_u16(target, address, *(u16*)(buffer + bytes_written));
641 status = stm32x_wait_status_busy(bank, 5);
643 if( status & FLASH_WRPRTERR )
644 return ERROR_FLASH_OPERATION_FAILED;
645 if( status & FLASH_PGERR )
646 return ERROR_FLASH_OPERATION_FAILED;
655 u8 last_halfword[2] = {0xff, 0xff};
658 while(bytes_remaining > 0)
660 last_halfword[i++] = *(buffer + bytes_written);
665 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
666 target_write_u16(target, address, *(u16*)last_halfword);
668 status = stm32x_wait_status_busy(bank, 5);
670 if( status & FLASH_WRPRTERR )
671 return ERROR_FLASH_OPERATION_FAILED;
672 if( status & FLASH_PGERR )
673 return ERROR_FLASH_OPERATION_FAILED;
676 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
681 int stm32x_probe(struct flash_bank_s *bank)
686 int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
691 int stm32x_erase_check(struct flash_bank_s *bank)
693 return stm32x_blank_check(bank, 0, bank->num_sectors - 1);
696 int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size)
698 snprintf(buf, buf_size, "stm32x flash driver info" );
702 int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
705 target_t *target = NULL;
706 stm32x_flash_bank_t *stm32x_info = NULL;
710 command_print(cmd_ctx, "stm32x lock <bank>");
714 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
717 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
721 stm32x_info = bank->driver_priv;
723 target = bank->target;
725 if (target->state != TARGET_HALTED)
727 return ERROR_TARGET_NOT_HALTED;
730 if (stm32x_erase_options(bank) != ERROR_OK)
732 command_print(cmd_ctx, "stm32x failed to erase options");
736 /* set readout protection */
737 stm32x_info->option_bytes.RDP = 0;
739 if (stm32x_write_options(bank) != ERROR_OK)
741 command_print(cmd_ctx, "stm32x failed to lock device");
745 command_print(cmd_ctx, "stm32x locked");
750 int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
753 target_t *target = NULL;
754 stm32x_flash_bank_t *stm32x_info = NULL;
758 command_print(cmd_ctx, "stm32x unlock <bank>");
762 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
765 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
769 stm32x_info = bank->driver_priv;
771 target = bank->target;
773 if (target->state != TARGET_HALTED)
775 return ERROR_TARGET_NOT_HALTED;
778 if (stm32x_erase_options(bank) != ERROR_OK)
780 command_print(cmd_ctx, "stm32x failed to unlock device");
784 if (stm32x_write_options(bank) != ERROR_OK)
786 command_print(cmd_ctx, "stm32x failed to lock device");
790 command_print(cmd_ctx, "stm32x unlocked");
795 int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
799 target_t *target = NULL;
800 stm32x_flash_bank_t *stm32x_info = NULL;
804 command_print(cmd_ctx, "stm32x options_read <bank>");
808 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
811 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
815 stm32x_info = bank->driver_priv;
817 target = bank->target;
819 if (target->state != TARGET_HALTED)
821 return ERROR_TARGET_NOT_HALTED;
824 target_read_u32(target, STM32_FLASH_OBR, &optionbyte);
825 command_print(cmd_ctx, "Option Byte: 0x%x", optionbyte);
827 if (buf_get_u32((u8*)&optionbyte, OPT_ERROR, 1))
828 command_print(cmd_ctx, "Option Byte Complement Error");
830 if (buf_get_u32((u8*)&optionbyte, OPT_READOUT, 1))
831 command_print(cmd_ctx, "Readout Protection On");
833 command_print(cmd_ctx, "Readout Protection Off");
835 if (buf_get_u32((u8*)&optionbyte, OPT_RDWDGSW, 1))
836 command_print(cmd_ctx, "Software Watchdog");
838 command_print(cmd_ctx, "Hardware Watchdog");
840 if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTOP, 1))
841 command_print(cmd_ctx, "Stop: No reset generated");
843 command_print(cmd_ctx, "Stop: Reset generated");
845 if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTDBY, 1))
846 command_print(cmd_ctx, "Standby: No reset generated");
848 command_print(cmd_ctx, "Standby: Reset generated");
853 int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
856 target_t *target = NULL;
857 stm32x_flash_bank_t *stm32x_info = NULL;
858 u16 optionbyte = 0xF8;
862 command_print(cmd_ctx, "stm32x options_write <bank> <SWWDG|HWWDG> <RSTSTNDBY|NORSTSTNDBY> <RSTSTOP|NORSTSTOP>");
866 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
869 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
873 stm32x_info = bank->driver_priv;
875 target = bank->target;
877 if (target->state != TARGET_HALTED)
879 return ERROR_TARGET_NOT_HALTED;
882 if (strcmp(args[1], "SWWDG") == 0)
884 optionbyte |= (1<<0);
888 optionbyte &= ~(1<<0);
891 if (strcmp(args[2], "NORSTSTNDBY") == 0)
893 optionbyte |= (1<<1);
897 optionbyte &= ~(1<<1);
900 if (strcmp(args[3], "NORSTSTOP") == 0)
902 optionbyte |= (1<<2);
906 optionbyte &= ~(1<<2);
909 if (stm32x_erase_options(bank) != ERROR_OK)
911 command_print(cmd_ctx, "stm32x failed to erase options");
915 stm32x_info->option_bytes.user_options = optionbyte;
917 if (stm32x_write_options(bank) != ERROR_OK)
919 command_print(cmd_ctx, "stm32x failed to write options");
923 command_print(cmd_ctx, "stm32x write options complete");
928 int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
930 target_t *target = NULL;
931 stm32x_flash_bank_t *stm32x_info = NULL;
937 command_print(cmd_ctx, "stm32x mass_erase <bank>");
941 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
944 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
948 stm32x_info = bank->driver_priv;
950 target = bank->target;
952 if (target->state != TARGET_HALTED)
954 return ERROR_TARGET_NOT_HALTED;
957 /* unlock option flash registers */
958 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
959 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
961 /* mass erase flash memory */
962 target_write_u32(target, STM32_FLASH_CR, FLASH_MER);
963 target_write_u32(target, STM32_FLASH_CR, FLASH_MER|FLASH_STRT);
965 status = stm32x_wait_status_busy(bank, 10);
967 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
969 if( status & FLASH_WRPRTERR )
971 command_print(cmd_ctx, "stm32x device protected");
975 if( status & FLASH_PGERR )
977 command_print(cmd_ctx, "stm32x device programming failed");
981 command_print(cmd_ctx, "stm32x mass erase complete");