git.sur5r.net Git - openocd/blob - src/flash/stm32x.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "replacements.h"
  25
  26 #include "stm32x.h"
  27 #include "flash.h"
  28 #include "target.h"
  29 #include "log.h"
  30 #include "armv7m.h"
  31 #include "algorithm.h"
  32 #include "binarybuffer.h"
  33
  34 #include <stdlib.h>
  35 #include <string.h>
  36
  37 int stm32x_register_commands(struct command_context_s *cmd_ctx);
  38 int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
  39 int stm32x_erase(struct flash_bank_s *bank, int first, int last);
  40 int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last);
  41 int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
  42 int stm32x_probe(struct flash_bank_s *bank);
  43 int stm32x_auto_probe(struct flash_bank_s *bank);
  44 int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  45 int stm32x_protect_check(struct flash_bank_s *bank);
  46 int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size);
  47
  48 int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  49 int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  50 int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  51 int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  52 int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  53
  54 flash_driver_t stm32x_flash =
  55 {
  56         .name = "stm32x",
  57         .register_commands = stm32x_register_commands,
  58         .flash_bank_command = stm32x_flash_bank_command,
  59         .erase = stm32x_erase,
  60         .protect = stm32x_protect,
  61         .write = stm32x_write,
  62         .probe = stm32x_probe,
  63         .auto_probe = stm32x_auto_probe,
  64         .erase_check = default_flash_blank_check,
  65         .protect_check = stm32x_protect_check,
  66         .info = stm32x_info
  67 };
  68
  69 int stm32x_register_commands(struct command_context_s *cmd_ctx)
  70 {
  71         command_t *stm32x_cmd = register_command(cmd_ctx, NULL, "stm32x", NULL, COMMAND_ANY, "stm32x flash specific commands");
  72
  73         register_command(cmd_ctx, stm32x_cmd, "lock", stm32x_handle_lock_command, COMMAND_EXEC,
  74                                          "lock device");
  75         register_command(cmd_ctx, stm32x_cmd, "unlock", stm32x_handle_unlock_command, COMMAND_EXEC,
  76                                          "unlock protected device");
  77         register_command(cmd_ctx, stm32x_cmd, "mass_erase", stm32x_handle_mass_erase_command, COMMAND_EXEC,
  78                                          "mass erase device");
  79         register_command(cmd_ctx, stm32x_cmd, "options_read", stm32x_handle_options_read_command, COMMAND_EXEC,
  80                                          "read device option bytes");
  81         register_command(cmd_ctx, stm32x_cmd, "options_write", stm32x_handle_options_write_command, COMMAND_EXEC,
  82                                          "write device option bytes");
  83         return ERROR_OK;
  84 }
  85
  86 /* flash bank stm32x <base> <size> 0 0 <target#>
  87  */
  88 int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
  89 {
  90         stm32x_flash_bank_t *stm32x_info;
  91
  92         if (argc < 6)
  93         {
  94                 LOG_WARNING("incomplete flash_bank stm32x configuration");
  95                 return ERROR_FLASH_BANK_INVALID;
  96         }
  97
  98         stm32x_info = malloc(sizeof(stm32x_flash_bank_t));
  99         bank->driver_priv = stm32x_info;
 100
 101         stm32x_info->write_algorithm = NULL;
 102         stm32x_info->probed = 0;
 103
 104         return ERROR_OK;
 105 }
 106
 107 u32 stm32x_get_flash_status(flash_bank_t *bank)
 108 {
 109         target_t *target = bank->target;
 110         u32 status;
 111
 112         target_read_u32(target, STM32_FLASH_SR, &status);
 113
 114         return status;
 115 }
 116
 117 u32 stm32x_wait_status_busy(flash_bank_t *bank, int timeout)
 118 {
 119         u32 status;
 120
 121         /* wait for busy to clear */
 122         while (((status = stm32x_get_flash_status(bank)) & FLASH_BSY) && (timeout-- > 0))
 123         {
 124                 LOG_DEBUG("status: 0x%x", status);
 125                 usleep(1000);
 126         }
 127
 128         return status;
 129 }
 130
 131 int stm32x_read_options(struct flash_bank_s *bank)
 132 {
 133         u32 optiondata;
 134         stm32x_flash_bank_t *stm32x_info = NULL;
 135         target_t *target = bank->target;
 136
 137         stm32x_info = bank->driver_priv;
 138
 139         /* read current option bytes */
 140         target_read_u32(target, STM32_FLASH_OBR, &optiondata);
 141
 142         stm32x_info->option_bytes.user_options = (u16)0xFFF8|((optiondata >> 2) & 0x07);
 143         stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
 144
 145         if (optiondata & (1 << OPT_READOUT))
 146                 LOG_INFO("Device Security Bit Set");
 147
 148         /* each bit refers to a 4bank protection */
 149         target_read_u32(target, STM32_FLASH_WRPR, &optiondata);
 150
 151         stm32x_info->option_bytes.protection[0] = (u16)optiondata;
 152         stm32x_info->option_bytes.protection[1] = (u16)(optiondata >> 8);
 153         stm32x_info->option_bytes.protection[2] = (u16)(optiondata >> 16);
 154         stm32x_info->option_bytes.protection[3] = (u16)(optiondata >> 24);
 155
 156         return ERROR_OK;
 157 }
 158
 159 int stm32x_erase_options(struct flash_bank_s *bank)
 160 {
 161         stm32x_flash_bank_t *stm32x_info = NULL;
 162         target_t *target = bank->target;
 163         u32 status;
 164
 165         stm32x_info = bank->driver_priv;
 166
 167         /* read current options */
 168         stm32x_read_options(bank);
 169
 170         /* unlock flash registers */
 171         target_write_u32(target, STM32_FLASH_KEYR, KEY1);
 172         target_write_u32(target, STM32_FLASH_KEYR, KEY2);
 173
 174         /* unlock option flash registers */
 175         target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
 176         target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
 177
 178         /* erase option bytes */
 179         target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_OPTWRE);
 180         target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_STRT|FLASH_OPTWRE);
 181
 182         status = stm32x_wait_status_busy(bank, 10);
 183
 184         if( status & FLASH_WRPRTERR )
 185                 return ERROR_FLASH_OPERATION_FAILED;
 186         if( status & FLASH_PGERR )
 187                 return ERROR_FLASH_OPERATION_FAILED;
 188
 189         /* clear readout protection and complementary option bytes
 190          * this will also force a device unlock if set */
 191         stm32x_info->option_bytes.RDP = 0x5AA5;
 192
 193         return ERROR_OK;
 194 }
 195
 196 int stm32x_write_options(struct flash_bank_s *bank)
 197 {
 198         stm32x_flash_bank_t *stm32x_info = NULL;
 199         target_t *target = bank->target;
 200         u32 status;
 201
 202         stm32x_info = bank->driver_priv;
 203
 204         /* unlock flash registers */
 205         target_write_u32(target, STM32_FLASH_KEYR, KEY1);
 206         target_write_u32(target, STM32_FLASH_KEYR, KEY2);
 207
 208         /* unlock option flash registers */
 209         target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
 210         target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
 211
 212         /* program option bytes */
 213         target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG|FLASH_OPTWRE);
 214
 215         /* write user option byte */
 216         target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
 217
 218         status = stm32x_wait_status_busy(bank, 10);
 219
 220         if( status & FLASH_WRPRTERR )
 221                 return ERROR_FLASH_OPERATION_FAILED;
 222         if( status & FLASH_PGERR )
 223                 return ERROR_FLASH_OPERATION_FAILED;
 224
 225         /* write protection byte 1 */
 226         target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
 227
 228         status = stm32x_wait_status_busy(bank, 10);
 229
 230         if( status & FLASH_WRPRTERR )
 231                 return ERROR_FLASH_OPERATION_FAILED;
 232         if( status & FLASH_PGERR )
 233                 return ERROR_FLASH_OPERATION_FAILED;
 234
 235         /* write protection byte 2 */
 236         target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
 237
 238         status = stm32x_wait_status_busy(bank, 10);
 239
 240         if( status & FLASH_WRPRTERR )
 241                 return ERROR_FLASH_OPERATION_FAILED;
 242         if( status & FLASH_PGERR )
 243                 return ERROR_FLASH_OPERATION_FAILED;
 244
 245         /* write protection byte 3 */
 246         target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
 247
 248         status = stm32x_wait_status_busy(bank, 10);
 249
 250         if( status & FLASH_WRPRTERR )
 251                 return ERROR_FLASH_OPERATION_FAILED;
 252         if( status & FLASH_PGERR )
 253                 return ERROR_FLASH_OPERATION_FAILED;
 254
 255         /* write protection byte 4 */
 256         target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
 257
 258         status = stm32x_wait_status_busy(bank, 10);
 259
 260         if( status & FLASH_WRPRTERR )
 261                 return ERROR_FLASH_OPERATION_FAILED;
 262         if( status & FLASH_PGERR )
 263                 return ERROR_FLASH_OPERATION_FAILED;
 264
 265         /* write readout protection bit */
 266         target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
 267
 268         status = stm32x_wait_status_busy(bank, 10);
 269
 270         if( status & FLASH_WRPRTERR )
 271                 return ERROR_FLASH_OPERATION_FAILED;
 272         if( status & FLASH_PGERR )
 273                 return ERROR_FLASH_OPERATION_FAILED;
 274
 275         target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
 276
 277         return ERROR_OK;
 278 }
 279
 280
 281 int stm32x_protect_check(struct flash_bank_s *bank)
 282 {
 283         target_t *target = bank->target;
 284
 285         u32 protection;
 286         int i, s;
 287         int num_bits;
 288
 289         if (target->state != TARGET_HALTED)
 290         {
 291                 return ERROR_TARGET_NOT_HALTED;
 292         }
 293
 294         /* each bit refers to a 4bank protection */
 295         target_read_u32(target, STM32_FLASH_WRPR, &protection);
 296
 297         /* each protection bit is for 4 1K pages */
 298         num_bits = (bank->num_sectors / 4);
 299
 300         for (i = 0; i < num_bits; i++)
 301         {
 302                 int set = 1;
 303
 304                 if( protection & (1 << i))
 305                         set = 0;
 306
 307                 for (s = 0; s < 4; s++)
 308                         bank->sectors[(i * 4) + s].is_protected = set;
 309         }
 310
 311         return ERROR_OK;
 312 }
 313
 314 int stm32x_erase(struct flash_bank_s *bank, int first, int last)
 315 {
 316         target_t *target = bank->target;
 317
 318         int i;
 319         u32 status;
 320
 321         if (bank->target->state != TARGET_HALTED)
 322         {
 323                 return ERROR_TARGET_NOT_HALTED;
 324         }
 325
 326         /* unlock flash registers */
 327         target_write_u32(target, STM32_FLASH_KEYR, KEY1);
 328         target_write_u32(target, STM32_FLASH_KEYR, KEY2);
 329
 330         for (i = first; i <= last; i++)
 331         {
 332                 target_write_u32(target, STM32_FLASH_CR, FLASH_PER);
 333                 target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);
 334                 target_write_u32(target, STM32_FLASH_CR, FLASH_PER|FLASH_STRT);
 335
 336                 status = stm32x_wait_status_busy(bank, 10);
 337
 338                 if( status & FLASH_WRPRTERR )
 339                         return ERROR_FLASH_OPERATION_FAILED;
 340                 if( status & FLASH_PGERR )
 341                         return ERROR_FLASH_OPERATION_FAILED;
 342                 bank->sectors[i].is_erased = 1;
 343         }
 344
 345         target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
 346
 347         return ERROR_OK;
 348 }
 349
 350 int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last)
 351 {
 352         stm32x_flash_bank_t *stm32x_info = NULL;
 353         target_t *target = bank->target;
 354         u16 prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
 355         int i, reg, bit;
 356         int status;
 357         u32 protection;
 358
 359         stm32x_info = bank->driver_priv;
 360
 361         if (target->state != TARGET_HALTED)
 362         {
 363                 return ERROR_TARGET_NOT_HALTED;
 364         }
 365
 366         if ((first && (first % 4)) || ((last + 1) && (last + 1) % 4))
 367         {
 368                 LOG_WARNING("sector start/end incorrect - stm32 has 4K sector protection");
 369                 return ERROR_FLASH_SECTOR_INVALID;
 370         }
 371
 372         /* each bit refers to a 4bank protection */
 373         target_read_u32(target, STM32_FLASH_WRPR, &protection);
 374
 375         prot_reg[0] = (u16)protection;
 376         prot_reg[1] = (u16)(protection >> 8);
 377         prot_reg[2] = (u16)(protection >> 16);
 378         prot_reg[3] = (u16)(protection >> 24);
 379
 380         for (i = first; i <= last; i++)
 381         {
 382                 reg = (i / 4) / 8;
 383                 bit = (i / 4) - (reg * 8);
 384
 385                 if( set )
 386                         prot_reg[reg] &= ~(1 << bit);
 387                 else
 388                         prot_reg[reg] |= (1 << bit);
 389         }
 390
 391         if ((status = stm32x_erase_options(bank)) != ERROR_OK)
 392                 return status;
 393
 394         stm32x_info->option_bytes.protection[0] = prot_reg[0];
 395         stm32x_info->option_bytes.protection[1] = prot_reg[1];
 396         stm32x_info->option_bytes.protection[2] = prot_reg[2];
 397         stm32x_info->option_bytes.protection[3] = prot_reg[3];
 398
 399         return stm32x_write_options(bank);
 400 }
 401
 402 int stm32x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
 403 {
 404         stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
 405         target_t *target = bank->target;
 406         u32 buffer_size = 8192;
 407         working_area_t *source;
 408         u32 address = bank->base + offset;
 409         reg_param_t reg_params[4];
 410         armv7m_algorithm_t armv7m_info;
 411         int retval = ERROR_OK;
 412
 413         u8 stm32x_flash_write_code[] = {
 414                                                                         /* write: */
 415                 0xDF, 0xF8, 0x24, 0x40,         /* ldr  r4, STM32_FLASH_CR */
 416                 0x09, 0x4D,                                     /* ldr  r5, STM32_FLASH_SR */
 417                 0x4F, 0xF0, 0x01, 0x03,         /* mov  r3, #1 */
 418                 0x23, 0x60,                                     /* str  r3, [r4, #0] */
 419                 0x30, 0xF8, 0x02, 0x3B,         /* ldrh r3, [r0], #2 */
 420                 0x21, 0xF8, 0x02, 0x3B,         /* strh r3, [r1], #2 */
 421                                                                         /* busy: */
 422                 0x2B, 0x68,                                     /* ldr  r3, [r5, #0] */
 423                 0x13, 0xF0, 0x01, 0x0F,         /* tst  r3, #0x01 */
 424                 0xFB, 0xD0,                                     /* beq  busy */
 425                 0x13, 0xF0, 0x14, 0x0F,         /* tst  r3, #0x14 */
 426                 0x01, 0xD1,                                     /* bne  exit */
 427                 0x01, 0x3A,                                     /* subs r2, r2, #1 */
 428                 0xED, 0xD1,                                     /* bne  write */
 429                                                                         /* exit: */
 430                 0xFE, 0xE7,                                     /* b exit */
 431                 0x10, 0x20, 0x02, 0x40,         /* STM32_FLASH_CR:      .word 0x40022010 */
 432                 0x0C, 0x20, 0x02, 0x40          /* STM32_FLASH_SR:      .word 0x4002200C */
 433         };
 434
 435         /* flash write code */
 436         if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code), &stm32x_info->write_algorithm) != ERROR_OK)
 437         {
 438                 LOG_WARNING("no working area available, can't do block memory writes");
 439                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 440         };
 441
 442         if ((retval=target_write_buffer(target, stm32x_info->write_algorithm->address, sizeof(stm32x_flash_write_code), stm32x_flash_write_code))!=ERROR_OK)
 443                 return retval;
 444
 445         /* memory buffer */
 446         while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
 447         {
 448                 buffer_size /= 2;
 449                 if (buffer_size <= 256)
 450                 {
 451                         /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
 452                         if (stm32x_info->write_algorithm)
 453                                 target_free_working_area(target, stm32x_info->write_algorithm);
 454
 455                         LOG_WARNING("no large enough working area available, can't do block memory writes");
 456                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 457                 }
 458         };
 459
 460         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 461         armv7m_info.core_mode = ARMV7M_MODE_ANY;
 462         armv7m_info.core_state = ARMV7M_STATE_THUMB;
 463
 464         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
 465         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 466         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
 467         init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
 468
 469         while (count > 0)
 470         {
 471                 u32 thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
 472
 473                 if ((retval = target_write_buffer(target, source->address, thisrun_count * 2, buffer))!=ERROR_OK)
 474                         break;
 475
 476                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
 477                 buf_set_u32(reg_params[1].value, 0, 32, address);
 478                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
 479
 480                 if ((retval = target->type->run_algorithm(target, 0, NULL, 4, reg_params, stm32x_info->write_algorithm->address, \
 481                                 stm32x_info->write_algorithm->address + (sizeof(stm32x_flash_write_code) - 10), 10000, &armv7m_info)) != ERROR_OK)
 482                 {
 483                         LOG_ERROR("error executing stm32x flash write algorithm");
 484                         break;
 485                 }
 486
 487                 if (buf_get_u32(reg_params[3].value, 0, 32) & 0x14)
 488                 {
 489                         retval = ERROR_FLASH_OPERATION_FAILED;
 490                         break;
 491                 }
 492
 493                 buffer += thisrun_count * 2;
 494                 address += thisrun_count * 2;
 495                 count -= thisrun_count;
 496         }
 497
 498         target_free_working_area(target, source);
 499         target_free_working_area(target, stm32x_info->write_algorithm);
 500
 501         destroy_reg_param(&reg_params[0]);
 502         destroy_reg_param(&reg_params[1]);
 503         destroy_reg_param(&reg_params[2]);
 504         destroy_reg_param(&reg_params[3]);
 505
 506         return retval;
 507 }
 508
 509 int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
 510 {
 511         target_t *target = bank->target;
 512         u32 words_remaining = (count / 2);
 513         u32 bytes_remaining = (count & 0x00000001);
 514         u32 address = bank->base + offset;
 515         u32 bytes_written = 0;
 516         u8 status;
 517         u32 retval;
 518
 519         if (bank->target->state != TARGET_HALTED)
 520         {
 521                 return ERROR_TARGET_NOT_HALTED;
 522         }
 523
 524         if (offset & 0x1)
 525         {
 526                 LOG_WARNING("offset 0x%x breaks required 2-byte alignment", offset);
 527                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 528         }
 529
 530         /* unlock flash registers */
 531         target_write_u32(target, STM32_FLASH_KEYR, KEY1);
 532         target_write_u32(target, STM32_FLASH_KEYR, KEY2);
 533
 534         /* multiple half words (2-byte) to be programmed? */
 535         if (words_remaining > 0)
 536         {
 537                 /* try using a block write */
 538                 if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
 539                 {
 540                         if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
 541                         {
 542                                 /* if block write failed (no sufficient working area),
 543                                  * we use normal (slow) single dword accesses */
 544                                 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
 545                         }
 546                         else if (retval == ERROR_FLASH_OPERATION_FAILED)
 547                         {
 548                                 LOG_ERROR("flash writing failed with error code: 0x%x", retval);
 549                                 return ERROR_FLASH_OPERATION_FAILED;
 550                         }
 551                 }
 552                 else
 553                 {
 554                         buffer += words_remaining * 2;
 555                         address += words_remaining * 2;
 556                         words_remaining = 0;
 557                 }
 558         }
 559
 560         while (words_remaining > 0)
 561         {
 562                 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
 563                 target_write_u16(target, address, *(u16*)(buffer + bytes_written));
 564
 565                 status = stm32x_wait_status_busy(bank, 5);
 566
 567                 if( status & FLASH_WRPRTERR )
 568                         return ERROR_FLASH_OPERATION_FAILED;
 569                 if( status & FLASH_PGERR )
 570                         return ERROR_FLASH_OPERATION_FAILED;
 571
 572                 bytes_written += 2;
 573                 words_remaining--;
 574                 address += 2;
 575         }
 576
 577         if (bytes_remaining)
 578         {
 579                 u8 last_halfword[2] = {0xff, 0xff};
 580                 int i = 0;
 581
 582                 while(bytes_remaining > 0)
 583                 {
 584                         last_halfword[i++] = *(buffer + bytes_written);
 585                         bytes_remaining--;
 586                         bytes_written++;
 587                 }
 588
 589                 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
 590                 target_write_u16(target, address, *(u16*)last_halfword);
 591
 592                 status = stm32x_wait_status_busy(bank, 5);
 593
 594                 if( status & FLASH_WRPRTERR )
 595                         return ERROR_FLASH_OPERATION_FAILED;
 596                 if( status & FLASH_PGERR )
 597                         return ERROR_FLASH_OPERATION_FAILED;
 598         }
 599
 600         target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
 601
 602         return ERROR_OK;
 603 }
 604
 605 int stm32x_probe(struct flash_bank_s *bank)
 606 {
 607         target_t *target = bank->target;
 608         stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
 609         int i;
 610         u16 num_sectors;
 611         u32 device_id;
 612
 613         if (bank->target->state != TARGET_HALTED)
 614         {
 615                 return ERROR_TARGET_NOT_HALTED;
 616         }
 617
 618         stm32x_info->probed = 0;
 619
 620         /* read stm32 device id register */
 621         target_read_u32(target, 0xE0042000, &device_id);
 622         LOG_INFO( "device id = 0x%08x", device_id );
 623
 624         if (!(device_id & 0x410))
 625     {
 626                 LOG_WARNING( "Cannot identify target as a STM32 family." );
 627                 return ERROR_FLASH_OPERATION_FAILED;
 628     }
 629
 630         /* get flash size from target */
 631         target_read_u16(target, 0x1FFFF7E0, &num_sectors);
 632
 633         /* check for early silicon rev A */
 634         if ((device_id >> 16) == 0 )
 635         {
 636                 /* number of sectors incorrect on revA */
 637                 LOG_WARNING( "STM32 Rev A Silicon detected, probe inaccurate - assuming 128k flash" );
 638                 num_sectors = 128;
 639         }
 640
 641         LOG_INFO( "flash size = %dkbytes", num_sectors );
 642
 643         bank->base = 0x08000000;
 644         bank->size = num_sectors * 1024;
 645         bank->num_sectors = num_sectors;
 646         bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
 647
 648         for (i = 0; i < num_sectors; i++)
 649         {
 650                 bank->sectors[i].offset = i * 1024;
 651                 bank->sectors[i].size = 1024;
 652                 bank->sectors[i].is_erased = -1;
 653                 bank->sectors[i].is_protected = 1;
 654         }
 655
 656         stm32x_info->probed = 1;
 657
 658         return ERROR_OK;
 659 }
 660
 661 int stm32x_auto_probe(struct flash_bank_s *bank)
 662 {
 663         stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
 664         if (stm32x_info->probed)
 665                 return ERROR_OK;
 666         return stm32x_probe(bank);
 667 }
 668
 669 int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 670 {
 671         return ERROR_OK;
 672 }
 673
 674 int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size)
 675 {
 676         snprintf(buf, buf_size, "stm32x flash driver info" );
 677         return ERROR_OK;
 678 }
 679
 680 int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 681 {
 682         flash_bank_t *bank;
 683         target_t *target = NULL;
 684         stm32x_flash_bank_t *stm32x_info = NULL;
 685
 686         if (argc < 1)
 687         {
 688                 command_print(cmd_ctx, "stm32x lock <bank>");
 689                 return ERROR_OK;
 690         }
 691
 692         bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
 693         if (!bank)
 694         {
 695                 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
 696                 return ERROR_OK;
 697         }
 698
 699         stm32x_info = bank->driver_priv;
 700
 701         target = bank->target;
 702
 703         if (target->state != TARGET_HALTED)
 704         {
 705                 return ERROR_TARGET_NOT_HALTED;
 706         }
 707
 708         if (stm32x_erase_options(bank) != ERROR_OK)
 709         {
 710                 command_print(cmd_ctx, "stm32x failed to erase options");
 711                 return ERROR_OK;
 712         }
 713
 714         /* set readout protection */
 715         stm32x_info->option_bytes.RDP = 0;
 716
 717         if (stm32x_write_options(bank) != ERROR_OK)
 718         {
 719                 command_print(cmd_ctx, "stm32x failed to lock device");
 720                 return ERROR_OK;
 721         }
 722
 723         command_print(cmd_ctx, "stm32x locked");
 724
 725         return ERROR_OK;
 726 }
 727
 728 int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 729 {
 730         flash_bank_t *bank;
 731         target_t *target = NULL;
 732         stm32x_flash_bank_t *stm32x_info = NULL;
 733
 734         if (argc < 1)
 735         {
 736                 command_print(cmd_ctx, "stm32x unlock <bank>");
 737                 return ERROR_OK;
 738         }
 739
 740         bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
 741         if (!bank)
 742         {
 743                 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
 744                 return ERROR_OK;
 745         }
 746
 747         stm32x_info = bank->driver_priv;
 748
 749         target = bank->target;
 750
 751         if (target->state != TARGET_HALTED)
 752         {
 753                 return ERROR_TARGET_NOT_HALTED;
 754         }
 755
 756         if (stm32x_erase_options(bank) != ERROR_OK)
 757         {
 758                 command_print(cmd_ctx, "stm32x failed to unlock device");
 759                 return ERROR_OK;
 760         }
 761
 762         if (stm32x_write_options(bank) != ERROR_OK)
 763         {
 764                 command_print(cmd_ctx, "stm32x failed to lock device");
 765                 return ERROR_OK;
 766         }
 767
 768         command_print(cmd_ctx, "stm32x unlocked");
 769
 770         return ERROR_OK;
 771 }
 772
 773 int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 774 {
 775         flash_bank_t *bank;
 776         u32 optionbyte;
 777         target_t *target = NULL;
 778         stm32x_flash_bank_t *stm32x_info = NULL;
 779
 780         if (argc < 1)
 781         {
 782                 command_print(cmd_ctx, "stm32x options_read <bank>");
 783                 return ERROR_OK;
 784         }
 785
 786         bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
 787         if (!bank)
 788         {
 789                 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
 790                 return ERROR_OK;
 791         }
 792
 793         stm32x_info = bank->driver_priv;
 794
 795         target = bank->target;
 796
 797         if (target->state != TARGET_HALTED)
 798         {
 799                 return ERROR_TARGET_NOT_HALTED;
 800         }
 801
 802         target_read_u32(target, STM32_FLASH_OBR, &optionbyte);
 803         command_print(cmd_ctx, "Option Byte: 0x%x", optionbyte);
 804
 805         if (buf_get_u32((u8*)&optionbyte, OPT_ERROR, 1))
 806                 command_print(cmd_ctx, "Option Byte Complement Error");
 807
 808         if (buf_get_u32((u8*)&optionbyte, OPT_READOUT, 1))
 809                 command_print(cmd_ctx, "Readout Protection On");
 810         else
 811                 command_print(cmd_ctx, "Readout Protection Off");
 812
 813         if (buf_get_u32((u8*)&optionbyte, OPT_RDWDGSW, 1))
 814                 command_print(cmd_ctx, "Software Watchdog");
 815         else
 816                 command_print(cmd_ctx, "Hardware Watchdog");
 817
 818         if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTOP, 1))
 819                 command_print(cmd_ctx, "Stop: No reset generated");
 820         else
 821                 command_print(cmd_ctx, "Stop: Reset generated");
 822
 823         if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTDBY, 1))
 824                 command_print(cmd_ctx, "Standby: No reset generated");
 825         else
 826                 command_print(cmd_ctx, "Standby: Reset generated");
 827
 828         return ERROR_OK;
 829 }
 830
 831 int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 832 {
 833         flash_bank_t *bank;
 834         target_t *target = NULL;
 835         stm32x_flash_bank_t *stm32x_info = NULL;
 836         u16 optionbyte = 0xF8;
 837
 838         if (argc < 4)
 839         {
 840                 command_print(cmd_ctx, "stm32x options_write <bank> <SWWDG|HWWDG> <RSTSTNDBY|NORSTSTNDBY> <RSTSTOP|NORSTSTOP>");
 841                 return ERROR_OK;
 842         }
 843
 844         bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
 845         if (!bank)
 846         {
 847                 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
 848                 return ERROR_OK;
 849         }
 850
 851         stm32x_info = bank->driver_priv;
 852
 853         target = bank->target;
 854
 855         if (target->state != TARGET_HALTED)
 856         {
 857                 return ERROR_TARGET_NOT_HALTED;
 858         }
 859
 860         if (strcmp(args[1], "SWWDG") == 0)
 861         {
 862                 optionbyte |= (1<<0);
 863         }
 864         else
 865         {
 866                 optionbyte &= ~(1<<0);
 867         }
 868
 869         if (strcmp(args[2], "NORSTSTNDBY") == 0)
 870         {
 871                 optionbyte |= (1<<1);
 872         }
 873         else
 874         {
 875                 optionbyte &= ~(1<<1);
 876         }
 877
 878         if (strcmp(args[3], "NORSTSTOP") == 0)
 879         {
 880                 optionbyte |= (1<<2);
 881         }
 882         else
 883         {
 884                 optionbyte &= ~(1<<2);
 885         }
 886
 887         if (stm32x_erase_options(bank) != ERROR_OK)
 888         {
 889                 command_print(cmd_ctx, "stm32x failed to erase options");
 890                 return ERROR_OK;
 891         }
 892
 893         stm32x_info->option_bytes.user_options = optionbyte;
 894
 895         if (stm32x_write_options(bank) != ERROR_OK)
 896         {
 897                 command_print(cmd_ctx, "stm32x failed to write options");
 898                 return ERROR_OK;
 899         }
 900
 901         command_print(cmd_ctx, "stm32x write options complete");
 902
 903         return ERROR_OK;
 904 }
 905
 906 int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 907 {
 908         target_t *target = NULL;
 909         stm32x_flash_bank_t *stm32x_info = NULL;
 910         flash_bank_t *bank;
 911         u32 status;
 912
 913         if (argc < 1)
 914         {
 915                 command_print(cmd_ctx, "stm32x mass_erase <bank>");
 916                 return ERROR_OK;
 917         }
 918
 919         bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
 920         if (!bank)
 921         {
 922                 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
 923                 return ERROR_OK;
 924         }
 925
 926         stm32x_info = bank->driver_priv;
 927
 928         target = bank->target;
 929
 930         if (target->state != TARGET_HALTED)
 931         {
 932                 return ERROR_TARGET_NOT_HALTED;
 933         }
 934
 935         /* unlock option flash registers */
 936         target_write_u32(target, STM32_FLASH_KEYR, KEY1);
 937         target_write_u32(target, STM32_FLASH_KEYR, KEY2);
 938
 939         /* mass erase flash memory */
 940         target_write_u32(target, STM32_FLASH_CR, FLASH_MER);
 941         target_write_u32(target, STM32_FLASH_CR, FLASH_MER|FLASH_STRT);
 942
 943         status = stm32x_wait_status_busy(bank, 10);
 944
 945         target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
 946
 947         if( status & FLASH_WRPRTERR )
 948         {
 949                 command_print(cmd_ctx, "stm32x device protected");
 950                 return ERROR_OK;
 951         }
 952
 953         if( status & FLASH_PGERR )
 954         {
 955                 command_print(cmd_ctx, "stm32x device programming failed");
 956                 return ERROR_OK;
 957         }
 958
 959         command_print(cmd_ctx, "stm32x mass erase complete");
 960
 961         return ERROR_OK;
 962 }