1 /***************************************************************************
2 * Copyright (C) 2011 by Martin Schmoelzer *
3 * <martin.schmoelzer@student.tuwien.ac.at> *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
22 #include "reg_ezusb.h"
24 /***************************************************************************
26 ***************************************************************************
27 * TMS ....... Test Mode Select *
28 * TCK ....... Test Clock *
29 * TDI ....... Test Data Input (from device point of view, not JTAG *
30 * adapter point of view!) *
31 * TDO ....... Test Data Output (from device point of view, not JTAG *
32 * adapter point of view!) *
33 * TRST ...... Test Reset: Used to reset the TAP Finite State Machine *
34 * into the Test Logic Reset state *
35 * RTCK ...... Return Test Clock *
36 * OCDSE ..... Enable/Disable OCDS interface (Infineon specific) - shared *
38 * TRAP ...... Trap Condition (Infineon specific) - shared with TSTAT *
39 * BRKIN ..... Hardware Break-In (Infineon specific) *
40 * BRKOUT .... Hardware Break-Out (Infineon specific) *
41 * /JEN ...... JTAG-Enable (STMicroelectronics specific) - shared *
43 * TSTAT ..... JTAG ISP Status (STMicroelectronics specific) - shared *
45 * RESET ..... Chip Reset (STMicroelectronics specific) *
46 * /TERR ..... JTAG ISP Error (STMicroelectronics specific) - shared *
48 ***************************************************************************/
51 #define PIN_U_OE OUTA0
52 /* PA1 Not Connected */
54 /* PA3 Not Connected */
55 #define PIN_RUN_LED OUTA4
57 #define PIN_BRKOUT PINA6
58 #define PIN_COM_LED OUTA7
64 #define PIN_TRST OUTB3
65 #define PIN_BRKIN OUTB4
66 #define PIN_RESET OUTB5
67 #define PIN_OCDSE OUTB6
68 #define PIN_TRAP PINB7
70 /* JTAG Signals with direction 'OUT' on port B */
71 #define MASK_PORTB_DIRECTION_OUT (PIN_TDI | PIN_TMS | PIN_TCK | PIN_TRST | PIN_BRKIN | PIN_RESET | PIN_OCDSE)
74 #define PIN_RXD0 PINC0
75 #define PIN_TXD0 OUTC1
76 #define PIN_RESET_2 PINC2
77 /* PC3 Not Connecte */
78 /* PC4 Not Connected */
79 #define PIN_RTCK PINC5
81 /* PC7 Not Connected */
84 #define SET_RUN_LED() (OUTA &= ~PIN_RUN_LED)
85 #define CLEAR_RUN_LED() (OUTA |= PIN_RUN_LED)
87 #define SET_COM_LED() (OUTA &= ~PIN_COM_LED)
88 #define CLEAR_COM_LED() (OUTA |= PIN_COM_LED)
91 #define GET_TMS() (PINSB & PIN_TMS)
92 #define GET_TCK() (PINSB & PIN_TCK)
94 #define GET_TDO() (PINSA & PIN_TDO)
95 #define GET_BRKOUT() (PINSA & PIN_BRKOUT)
96 #define GET_TRAP() (PINSB & PIN_TRAP)
97 #define GET_RTCK() (PINSC & PIN_RTCK)
99 #define SET_TMS_HIGH() (OUTB |= PIN_TMS)
100 #define SET_TMS_LOW() (OUTB &= ~PIN_TMS)
102 #define SET_TCK_HIGH() (OUTB |= PIN_TCK)
103 #define SET_TCK_LOW() (OUTB &= ~PIN_TCK)
105 #define SET_TDI_HIGH() (OUTB |= PIN_TDI)
106 #define SET_TDI_LOW() (OUTB &= ~PIN_TDI)
108 /* TRST and RESET are low-active and inverted by hardware. SET_HIGH de-asserts
109 * the signal (enabling reset), SET_LOW asserts the signal (disabling reset) */
110 #define SET_TRST_HIGH() (OUTB |= PIN_TRST)
111 #define SET_TRST_LOW() (OUTB &= ~PIN_TRST)
113 #define SET_RESET_HIGH() (OUTB |= PIN_RESET)
114 #define SET_RESET_LOW() (OUTB &= ~PIN_RESET)
116 #define SET_OCDSE_HIGH() (OUTB |= PIN_OCDSE)
117 #define SET_OCDSE_LOW() (OUTB &= ~PIN_OCDSE)
119 #define SET_BRKIN_HIGH() (OUTB |= PIN_BRKIN)
120 #define SET_BRKIN_LOW() (OUTB &= ~PIN_BRKIN)