1 /***************************************************************************
2 * Copyright (C) 2011 by Martin Schmoelzer *
3 * <martin.schmoelzer@student.tuwien.ac.at> *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
19 ***************************************************************************/
26 * All information in this file was taken from the EZ-USB Technical
27 * Reference Manual, Cypress Semiconductor, 3901 North First Street
28 * San Jose, CA 95134 (www.cypress.com).
30 * The EZ-USB Technical Reference Manual is called "EZ-USB TRM" hereafter.
32 * The following bit name definitions differ from those in the EZ-USB TRM:
33 * - All lowercase characters in the EZ-USB TRM bit names have been converted
34 * to capitals (e. g. "WakeSRC" converted to "WAKESRC").
35 * - CPUCS: 8051RES is named "RES8051".
36 * - ISOCTL: Two MBZ ("Must Be Zero") bits are named "MBZ0" and "MBZ1".
37 * - I2CS: STOP and START bits are preceded by "I2C_"
38 * - INxCS, OUTxCS: the busy and stall bits are named "EPBSY" and "EPSTALL".
39 * - TOGCTL: EZ-USB TRM bit names are preceded by "TOG_".
42 /* Compiler-specific definitions of SBIT, SFR, SFRX, ... macros */
43 #include <mcs51/compiler.h>
55 /**************************************************************************
56 ************************ Special Function Registers **********************
57 ***************************************************************************/
59 /* See EZ-USB TRM, pp. A-9 - A-10 */
69 /* Bit 1 read-only, always reads '0' */
70 /* Bit 2 read-only, always reads '0' */
71 /* Bit 3 read-only, always reads '0' */
72 /* Bit 4 read-only, always reads '0' */
73 /* Bit 5 read-only, always reads '0' */
74 /* Bit 6 read-only, always reads '0' */
75 /* Bit 7 read-only, always reads '0' */
82 /* Bit 4 read-only, always reads '1' */
83 /* Bit 5 read-only, always reads '1' */
98 /* Some bits in this register share the same name in the EZ-USB TRM. Therefore,
99 * we add a '0'/'1' to distinguish them */
126 /* Bit 1 read-only, always reads '0' */
127 /* Bit 2 read-only, always reads '0' */
128 /* Bit 3 read-only, always reads '0' */
129 /* Bit 4 read-only, always reads '0' */
130 /* Bit 5 read-only, always reads '0' */
131 /* Bit 6 read-only, always reads '0' */
132 /* Bit 7 read-only, always reads '0' */
135 /* Bit 0 read-only, always reads '0' */
136 /* Bit 1 read-only, always reads '0' */
137 /* Bit 2 read-only, always reads '0' */
138 /* Bit 3 read-only, always reads '1' */
139 #define USBINT bmBit4
140 #define I2CINT bmBit5
144 /* Definition of the _XPAGE register, according to SDCC Compiler User Guide,
145 * Version 3.0.1, Chapter 4, p. 61. Also see EZ-USB TRM, p. 2-4. */
152 SBIT(RB8_0, 0x98, 2);
153 SBIT(TB8_0, 0x98, 3);
154 SBIT(REN_0, 0x98, 4);
155 SBIT(SM2_0, 0x98, 5);
156 SBIT(SM1_0, 0x98, 6);
157 SBIT(SM0_0, 0x98, 7);
179 /* Bit 7 read-only, always reads '1' */
184 SBIT(RB8_1, 0xC0, 2);
185 SBIT(TB8_1, 0xC0, 3);
186 SBIT(REN_1, 0xC0, 4);
187 SBIT(SM2_1, 0xC0, 5);
188 SBIT(SM1_1, 0xC0, 6);
189 SBIT(SM0_1, 0xC0, 7);
194 SBIT(CPRL2, 0xC8, 0);
197 SBIT(EXEN2, 0xC8, 3);
219 /* Bit 0 read-only, always reads '0' */
220 /* Bit 1 read-only, always reads '0' */
221 /* Bit 2 read-only, always reads '0' */
224 SBIT(ERESI, 0xD8, 5);
225 /* Bit 6 read-only, always reads '1' */
226 SBIT(SMOD1, 0xD8, 7);
236 /* Bit 5 read-only, always reads '1' */
237 /* Bit 6 read-only, always reads '1' */
238 /* Bit 7 read-only, always reads '1' */
248 /* Bit 5 read-only, always reads '1' */
249 /* Bit 6 read-only, always reads '1' */
250 /* Bit 7 read-only, always reads '1' */
252 /**************************************************************************
253 ***************************** XDATA Registers ****************************
254 ***************************************************************************/
256 /************************ Endpoint 0-7 Data Buffers ************************/
257 SFRX(OUT7BUF[64], 0x7B40);
258 SFRX(IN7BUF[64], 0x7B80);
259 SFRX(OUT6BUF[64], 0x7BC0);
260 SFRX(IN6BUF[64], 0x7C00);
261 SFRX(OUT5BUF[64], 0x7C40);
262 SFRX(IN5BUF[64], 0x7C80);
263 SFRX(OUT4BUF[64], 0x7CC0);
264 SFRX(IN4BUF[64], 0x7D00);
265 SFRX(OUT3BUF[64], 0x7D40);
266 SFRX(IN3BUF[64], 0x7D80);
267 SFRX(OUT2BUF[64], 0x7DC0);
268 SFRX(IN2BUF[64], 0x7E00);
269 SFRX(OUT1BUF[64], 0x7E40);
270 SFRX(IN1BUF[64], 0x7E80);
271 SFRX(OUT0BUF[64], 0x7EC0);
272 SFRX(IN0BUF[64], 0x7F00);
273 /* 0x7F40 - 0x7F5F reserved */
275 /**************************** Isochronous Data *****************************/
276 SFRX(OUT8DATA, 0x7F60);
277 SFRX(OUT9DATA, 0x7F61);
278 SFRX(OUT10DATA, 0x7F62);
279 SFRX(OUT11DATA, 0x7F63);
280 SFRX(OUT12DATA, 0x7F64);
281 SFRX(OUT13DATA, 0x7F65);
282 SFRX(OUT14DATA, 0x7F66);
283 SFRX(OUT15DATA, 0x7F67);
285 SFRX(IN8DATA, 0x7F68);
286 SFRX(IN9DATA, 0x7F69);
287 SFRX(IN10DATA, 0x7F6A);
288 SFRX(IN11DATA, 0x7F6B);
289 SFRX(IN12DATA, 0x7F6C);
290 SFRX(IN13DATA, 0x7F6D);
291 SFRX(IN14DATA, 0x7F6E);
292 SFRX(IN15DATA, 0x7F6F);
294 /************************* Isochronous Byte Counts *************************/
295 SFRX(OUT8BCH, 0x7F70);
296 SFRX(OUT8BCL, 0x7F71);
297 SFRX(OUT9BCH, 0x7F72);
298 SFRX(OUT9BCL, 0x7F73);
299 SFRX(OUT10BCH, 0x7F74);
300 SFRX(OUT10BCL, 0x7F75);
301 SFRX(OUT11BCH, 0x7F76);
302 SFRX(OUT11BCL, 0x7F77);
303 SFRX(OUT12BCH, 0x7F78);
304 SFRX(OUT12BCL, 0x7F79);
305 SFRX(OUT13BCH, 0x7F7A);
306 SFRX(OUT13BCL, 0x7F7B);
307 SFRX(OUT14BCH, 0x7F7C);
308 SFRX(OUT14BCL, 0x7F7D);
309 SFRX(OUT15BCH, 0x7F7E);
310 SFRX(OUT16BCL, 0x7F7F);
312 /****************************** CPU Registers ******************************/
314 #define RES8051 bmBit0
315 #define CLK24OE bmBit1
316 /* Bit 2 read-only, always reads '0' */
317 /* Bit 3 read-only, always reads '0' */
318 /* Bits 4...7: Chip Revision */
320 SFRX(PORTACFG, 0x7F93);
327 #define RXD0OUT bmBit6
328 #define RXD1OUT bmBit7
330 SFRX(PORTBCFG, 0x7F94);
340 SFRX(PORTCCFG, 0x7F95);
350 /*********************** Input-Output Port Registers ***********************/
441 /* 0x7F9F reserved */
443 /****************** Isochronous Control/Status Registers *******************/
444 SFRX(ISOERR, 0x7FA0);
445 #define ISO8ERR bmBit0
446 #define ISO9ERR bmBit1
447 #define ISO10ERR bmBit2
448 #define ISO11ERR bmBit3
449 #define ISO12ERR bmBit4
450 #define ISO13ERR bmBit5
451 #define ISO14ERR bmBit6
452 #define ISO15ERR bmBit7
454 SFRX(ISOCTL, 0x7FA1);
455 #define ISODISAB bmBit0
458 #define PPSTAT bmBit3
464 SFRX(ZBCOUT, 0x7FA2);
474 /* 0x7FA3 reserved */
475 /* 0x7FA4 reserved */
477 /****************************** I2C Registers ******************************/
484 #define LASTRD bmBit5
485 #define I2C_STOP bmBit6
486 #define I2C_START bmBit7
489 /* 0x7FA7 reserved */
491 /******************************* Interrupts ********************************/
493 /* Bit 0 read-only, always reads '0' */
494 /* Bit 1 read-only, always reads '0' */
500 /* Bit 7 read-only, always reads '0' */
502 SFRX(IN07IRQ, 0x7FA9);
512 SFRX(OUT07IRQ, 0x7FAA);
513 #define OUT0IR bmBit0
514 #define OUT1IR bmBit1
515 #define OUT2IR bmBit2
516 #define OUT3IR bmBit3
517 #define OUT4IR bmBit4
518 #define OUT5IR bmBit5
519 #define OUT6IR bmBit6
520 #define OUT7IR bmBit7
522 SFRX(USBIRQ, 0x7FAB);
523 #define SUDAVIR bmBit0
525 #define SUTOKIR bmBit2
526 #define SUSPIR bmBit3
527 #define URESIR bmBit4
532 SFRX(IN07IEN, 0x7FAC);
533 #define IN0IEN bmBit0
534 #define IN1IEN bmBit1
535 #define IN2IEN bmBit2
536 #define IN3IEN bmBit3
537 #define IN4IEN bmBit4
538 #define IN5IEN bmBit5
539 #define IN6IEN bmBit6
540 #define IN7IEN bmBit7
542 SFRX(OUT07IEN, 0x7FAD);
543 #define OUT0IEN bmBit0
544 #define OUT1IEN bmBit1
545 #define OUT2IEN bmBit2
546 #define OUT3IEN bmBit3
547 #define OUT4IEN bmBit4
548 #define OUT5IEN bmBit5
549 #define OUT6IEN bmBit6
550 #define OUT7IEN bmBit7
552 SFRX(USBIEN, 0x7FAE);
553 #define SUDAVIE bmBit0
555 #define SUTOKIE bmBit2
556 #define SUSPIE bmBit3
557 #define URESIE bmBit4
562 SFRX(USBBAV, 0x7FAF);
565 #define BPPULSE bmBit2
572 /* 0x7FB0 reserved */
573 /* 0x7FB1 reserved */
574 SFRX(BPADDRH, 0x7FB2);
575 SFRX(BPADDRL, 0x7FB3);
577 /****************************** Endpoints 0-7 ******************************/
579 #define EP0STALL bmBit0
581 #define IN0BSY bmBit2
582 #define OUT0BSY bmBit3
603 /* 0x7FC4 reserved */
604 SFRX(OUT0BC, 0x7FC5);
605 SFRX(OUT1CS, 0x7FC6);
606 SFRX(OUT1BC, 0x7FC7);
607 SFRX(OUT2CS, 0x7FC8);
608 SFRX(OUT2BC, 0x7FC9);
609 SFRX(OUT3CS, 0x7FCA);
610 SFRX(OUT3BC, 0x7FCB);
611 SFRX(OUT4CS, 0x7FCC);
612 SFRX(OUT4BC, 0x7FCD);
613 SFRX(OUT5CS, 0x7FCE);
614 SFRX(OUT5BC, 0x7FCF);
615 SFRX(OUT6CS, 0x7FD0);
616 SFRX(OUT6BC, 0x7FD1);
617 SFRX(OUT7CS, 0x7FD2);
618 SFRX(OUT7BC, 0x7FD3);
620 /* The INxSTALL, OUTxSTALL, INxBSY and OUTxBSY bits are the same for all
621 * INxCS/OUTxCS registers. For better readability, we define them only once */
622 #define EPSTALL bmBit0
625 /************************** Global USB Registers ***************************/
626 SFRX(SUDPTRH, 0x7FD4);
627 SFRX(SUDPTRL, 0x7FD5);
630 #define SIGRSUME bmBit0
632 #define DISCOE bmBit2
633 #define DISCON bmBit3
637 #define WAKESRC bmBit7
639 SFRX(TOGCTL, 0x7FD7);
640 #define TOG_EP0 bmBit0
641 #define TOG_EP1 bmBit1
642 #define TOG_EP2 bmBit2
643 /* Bit 3 is read-only, always reads '0' */
644 #define TOG_IO bmBit4
649 SFRX(USBFRAMEL, 0x7FD8);
650 SFRX(USBFRAMEH, 0x7FD9);
651 /* 0x7FDA reserved */
652 SFRX(FNADDR, 0x7FDB);
653 /* 0x7FDC reserved */
655 SFRX(USBPAIR, 0x7FDD);
659 #define PR2OUT bmBit3
660 #define PR4OUT bmBit4
661 #define PR6OUT bmBit5
663 #define ISOSEND0 bmBit7
665 SFRX(IN07VAL, 0x7FDE);
666 /* Bit 0 is read-only, always reads '1' */
667 #define IN1VAL bmBit1
668 #define IN2VAL bmBit2
669 #define IN3VAL bmBit3
670 #define IN4VAL bmBit4
671 #define IN5VAL bmBit5
672 #define IN6VAL bmBit6
673 #define IN7VAL bmBit7
675 SFRX(OUT07VAL, 0x7FDF);
676 /* Bit 0 is read-only, always reads '1' */
677 #define OUT1VAL bmBit1
678 #define OUT2VAL bmBit2
679 #define OUT3VAL bmBit3
680 #define OUT4VAL bmBit4
681 #define OUT5VAL bmBit5
682 #define OUT6VAL bmBit6
683 #define OUT7VAL bmBit7
685 SFRX(INISOVAL, 0x7FE0);
686 #define IN8VAL bmBit0
687 #define IN9VAL bmBit1
688 #define IN10VAL bmBit2
689 #define IN11VAL bmBit3
690 #define IN12VAL bmBit4
691 #define IN13VAL bmBit5
692 #define IN14VAL bmBit6
693 #define IN15VAL bmBit7
695 SFRX(OUTISOVAL, 0x7FE1);
696 #define OUT8VAL bmBit0
697 #define OUT9VAL bmBit1
698 #define OUT10VAL bmBit2
699 #define OUT11VAL bmBit3
700 #define OUT12VAL bmBit4
701 #define OUT13VAL bmBit5
702 #define OUT14VAL bmBit6
703 #define OUT15VAL bmBit7
705 SFRX(FASTXFR, 0x7FE2);
715 SFRX(AUTOPTRH, 0x7FE3);
716 SFRX(AUTOPTRL, 0x7FE4);
717 SFRX(AUTODATA, 0x7FE5);
718 /* 0x7FE6 reserved */
719 /* 0x7FE7 reserved */
721 /******************************* Setup Data ********************************/
722 SFRX(SETUPDAT[8], 0x7FE8);
724 /************************* Isochronous FIFO sizes **************************/
725 SFRX(OUT8ADDR, 0x7FF0);
726 SFRX(OUT9ADDR, 0x7FF1);
727 SFRX(OUT10ADDR, 0x7FF2);
728 SFRX(OUT11ADDR, 0x7FF3);
729 SFRX(OUT12ADDR, 0x7FF4);
730 SFRX(OUT13ADDR, 0x7FF5);
731 SFRX(OUT14ADDR, 0x7FF6);
732 SFRX(OUT15ADDR, 0x7FF7);
734 SFRX(IN8ADDR, 0x7FF8);
735 SFRX(IN9ADDR, 0x7FF9);
736 SFRX(IN10ADDR, 0x7FFA);
737 SFRX(IN11ADDR, 0x7FFB);
738 SFRX(IN12ADDR, 0x7FFC);
739 SFRX(IN13ADDR, 0x7FFD);
740 SFRX(IN14ADDR, 0x7FFE);
741 SFRX(IN15ADDR, 0x7FFF);