1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
18 ***************************************************************************/
32 #define _DEBUG_INSTRUCTION_EXECUTION_
37 #define FNC_INFO DEBUG("-")
43 #define FNC_INFO_NOTIMPLEMENTED do { DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
45 #define FNC_INFO_NOTIMPLEMENTED
48 static void arm11_on_enter_debug_state(arm11_common_t * arm11);
51 int arm11_config_memwrite_burst = 1;
52 int arm11_config_memwrite_error_fatal = 1;
56 #define ARM11_HANDLER(x) \
59 target_type_t arm11_target =
64 ARM11_HANDLER(arch_state),
66 ARM11_HANDLER(target_request_data),
69 ARM11_HANDLER(resume),
72 ARM11_HANDLER(assert_reset),
73 ARM11_HANDLER(deassert_reset),
74 ARM11_HANDLER(soft_reset_halt),
75 ARM11_HANDLER(prepare_reset_halt),
77 ARM11_HANDLER(get_gdb_reg_list),
79 ARM11_HANDLER(read_memory),
80 ARM11_HANDLER(write_memory),
82 ARM11_HANDLER(bulk_write_memory),
84 ARM11_HANDLER(checksum_memory),
86 ARM11_HANDLER(add_breakpoint),
87 ARM11_HANDLER(remove_breakpoint),
88 ARM11_HANDLER(add_watchpoint),
89 ARM11_HANDLER(remove_watchpoint),
91 ARM11_HANDLER(run_algorithm),
93 ARM11_HANDLER(register_commands),
94 ARM11_HANDLER(target_command),
95 ARM11_HANDLER(init_target),
99 int arm11_regs_arch_type = -1;
117 ARM11_REGISTER_SPSR_FIQ,
118 ARM11_REGISTER_SPSR_SVC,
119 ARM11_REGISTER_SPSR_ABT,
120 ARM11_REGISTER_SPSR_IRQ,
121 ARM11_REGISTER_SPSR_UND,
122 ARM11_REGISTER_SPSR_MON,
131 typedef struct arm11_reg_defs_s
136 enum arm11_regtype type;
139 /* update arm11_regcache_ids when changing this */
140 static const arm11_reg_defs_t arm11_reg_defs[] =
142 {"r0", 0, 0, ARM11_REGISTER_CORE},
143 {"r1", 1, 1, ARM11_REGISTER_CORE},
144 {"r2", 2, 2, ARM11_REGISTER_CORE},
145 {"r3", 3, 3, ARM11_REGISTER_CORE},
146 {"r4", 4, 4, ARM11_REGISTER_CORE},
147 {"r5", 5, 5, ARM11_REGISTER_CORE},
148 {"r6", 6, 6, ARM11_REGISTER_CORE},
149 {"r7", 7, 7, ARM11_REGISTER_CORE},
150 {"r8", 8, 8, ARM11_REGISTER_CORE},
151 {"r9", 9, 9, ARM11_REGISTER_CORE},
152 {"r10", 10, 10, ARM11_REGISTER_CORE},
153 {"r11", 11, 11, ARM11_REGISTER_CORE},
154 {"r12", 12, 12, ARM11_REGISTER_CORE},
155 {"sp", 13, 13, ARM11_REGISTER_CORE},
156 {"lr", 14, 14, ARM11_REGISTER_CORE},
157 {"pc", 15, 15, ARM11_REGISTER_CORE},
159 #if ARM11_REGCACHE_FREGS
160 {"f0", 0, 16, ARM11_REGISTER_FX},
161 {"f1", 1, 17, ARM11_REGISTER_FX},
162 {"f2", 2, 18, ARM11_REGISTER_FX},
163 {"f3", 3, 19, ARM11_REGISTER_FX},
164 {"f4", 4, 20, ARM11_REGISTER_FX},
165 {"f5", 5, 21, ARM11_REGISTER_FX},
166 {"f6", 6, 22, ARM11_REGISTER_FX},
167 {"f7", 7, 23, ARM11_REGISTER_FX},
168 {"fps", 0, 24, ARM11_REGISTER_FPS},
171 {"cpsr", 0, 25, ARM11_REGISTER_CPSR},
173 #if ARM11_REGCACHE_MODEREGS
174 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ},
175 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ},
176 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ},
177 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ},
178 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ},
179 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ},
180 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ},
181 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ},
183 {"r13_svc", 13, -1, ARM11_REGISTER_SVC},
184 {"r14_svc", 14, -1, ARM11_REGISTER_SVC},
185 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC},
187 {"r13_abt", 13, -1, ARM11_REGISTER_ABT},
188 {"r14_abt", 14, -1, ARM11_REGISTER_ABT},
189 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT},
191 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ},
192 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ},
193 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ},
195 {"r13_und", 13, -1, ARM11_REGISTER_UND},
196 {"r14_und", 14, -1, ARM11_REGISTER_UND},
197 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND},
200 {"r13_mon", 13, -1, ARM11_REGISTER_MON},
201 {"r14_mon", 14, -1, ARM11_REGISTER_MON},
202 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON},
205 /* Debug Registers */
206 {"dscr", 0, -1, ARM11_REGISTER_DSCR},
207 {"wdtr", 0, -1, ARM11_REGISTER_WDTR},
208 {"rdtr", 0, -1, ARM11_REGISTER_RDTR},
211 enum arm11_regcache_ids
214 ARM11_RC_RX = ARM11_RC_R0,
229 ARM11_RC_SP = ARM11_RC_R13,
231 ARM11_RC_LR = ARM11_RC_R14,
233 ARM11_RC_PC = ARM11_RC_R15,
235 #if ARM11_REGCACHE_FREGS
237 ARM11_RC_FX = ARM11_RC_F0,
250 #if ARM11_REGCACHE_MODEREGS
289 #define ARM11_GDB_REGISTER_COUNT 26
291 u8 arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
293 reg_t arm11_gdb_dummy_fp_reg =
295 "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
298 u8 arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
300 reg_t arm11_gdb_dummy_fps_reg =
302 "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
307 /** Check and if necessary take control of the system
309 * \param arm11 Target state variable.
310 * \param dscr If the current DSCR content is
311 * available a pointer to a word holding the
312 * DSCR can be passed. Otherwise use NULL.
314 void arm11_check_init(arm11_common_t * arm11, u32 * dscr)
318 u32 dscr_local_tmp_copy;
322 dscr = &dscr_local_tmp_copy;
323 *dscr = arm11_read_DSCR(arm11);
326 if (!(*dscr & ARM11_DSCR_MODE_SELECT))
328 DEBUG("Bringing target into debug mode");
330 *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
331 arm11_write_DSCR(arm11, *dscr);
333 /* add further reset initialization here */
335 if (*dscr & ARM11_DSCR_CORE_HALTED)
337 arm11->target->state = TARGET_HALTED;
338 arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
342 arm11->target->state = TARGET_RUNNING;
343 arm11->target->debug_reason = DBG_REASON_NOTHALTED;
346 arm11_sc7_clear_vbw(arm11);
353 (arm11->reg_values[ARM11_RC_##x])
355 /** Save processor state.
357 * This is called when the HALT instruction has succeeded
358 * or on other occasions that stop the processor.
361 static void arm11_on_enter_debug_state(arm11_common_t * arm11)
366 for(i = 0; i < asizeof(arm11->reg_values); i++)
368 arm11->reg_list[i].valid = 1;
369 arm11->reg_list[i].dirty = 0;
374 R(DSCR) = arm11_read_DSCR(arm11);
378 if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
380 arm11_add_debug_SCAN_N(arm11, 0x05, -1);
382 arm11_add_IR(arm11, ARM11_INTEST, -1);
384 scan_field_t chain5_fields[3];
386 arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
387 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
388 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
390 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
394 arm11->reg_list[ARM11_RC_WDTR].valid = 0;
398 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
399 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
400 ARM1136 seems to require this to issue ITR's as well */
402 u32 new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
404 /* this executes JTAG queue: */
406 arm11_write_DSCR(arm11, new_dscr);
408 // jtag_execute_queue();
412 // DEBUG("SAVE DSCR %08x", R(DSCR));
414 // if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
415 // DEBUG("SAVE wDTR %08x", R(WDTR));
419 Before executing any instruction in debug state you have to drain the write buffer.
420 This ensures that no imprecise Data Aborts can return at a later point:*/
422 /** \todo TODO: Test drain write buffer. */
427 /* MRC p14,0,R0,c5,c10,0 */
428 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
430 /* mcr 15, 0, r0, cr7, cr10, {4} */
431 arm11_run_instr_no_data1(arm11, 0xee070f9a);
433 u32 dscr = arm11_read_DSCR(arm11);
435 DEBUG("DRAIN, DSCR %08x", dscr);
437 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
439 arm11_run_instr_no_data1(arm11, 0xe320f000);
441 dscr = arm11_read_DSCR(arm11);
443 DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
451 arm11_run_instr_data_prepare(arm11);
456 /** \todo TODO: handle other mode registers */
459 for (i = 0; i < 15; i++)
461 /* MCR p14,0,R?,c0,c5,0 */
462 arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
468 /* check rDTRfull in DSCR */
470 if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
472 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
473 arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
477 arm11->reg_list[ARM11_RC_RDTR].valid = 0;
482 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
483 arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
487 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
488 arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
490 /* adjust PC depending on ARM state */
492 if (R(CPSR) & ARM11_CPSR_J) /* Java state */
494 arm11->reg_values[ARM11_RC_PC] -= 0;
496 else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */
498 arm11->reg_values[ARM11_RC_PC] -= 4;
502 arm11->reg_values[ARM11_RC_PC] -= 8;
505 // DEBUG("SAVE PC %08x", R(PC));
507 arm11_run_instr_data_finish(arm11);
509 arm11_dump_reg_changes(arm11);
512 void arm11_dump_reg_changes(arm11_common_t * arm11)
515 for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
517 if (!arm11->reg_list[i].valid)
519 if (arm11->reg_history[i].valid)
520 INFO("%8s INVALID (%08x)", arm11_reg_defs[i].name, arm11->reg_history[i].value);
524 if (arm11->reg_history[i].valid)
526 if (arm11->reg_history[i].value != arm11->reg_values[i])
527 INFO("%8s %08x (%08x)", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
531 INFO("%8s %08x (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
538 /** Restore processor state
540 * This is called in preparation for the RESTART function.
543 void arm11_leave_debug_state(arm11_common_t * arm11)
547 arm11_run_instr_data_prepare(arm11);
549 /** \todo TODO: handle other mode registers */
551 /* restore R1 - R14 */
553 for (i = 1; i < 15; i++)
555 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
558 /* MRC p14,0,r?,c0,c5,0 */
559 arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
561 // DEBUG("RESTORE R%d %08x", i, R(RX + i));
564 arm11_run_instr_data_finish(arm11);
567 /* spec says clear wDTR and rDTR; we assume they are clear as
568 otherwise our programming would be sloppy */
571 u32 DSCR = arm11_read_DSCR(arm11);
573 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
575 ERROR("wDTR/rDTR inconsistent (DSCR %08x)", DSCR);
579 arm11_run_instr_data_prepare(arm11);
581 /* restore original wDTR */
583 if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
585 /* MCR p14,0,R0,c0,c5,0 */
586 arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
592 arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
598 arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
603 /* MRC p14,0,r0,c0,c5,0 */
604 arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
606 arm11_run_instr_data_finish(arm11);
611 arm11_write_DSCR(arm11, R(DSCR));
616 if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
618 arm11_add_debug_SCAN_N(arm11, 0x05, -1);
620 arm11_add_IR(arm11, ARM11_EXTEST, -1);
622 scan_field_t chain5_fields[3];
624 u8 Ready = 0; /* ignored */
625 u8 Valid = 0; /* ignored */
627 arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
628 arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
629 arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
631 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
634 arm11_record_register_history(arm11);
637 void arm11_record_register_history(arm11_common_t * arm11)
640 for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
642 arm11->reg_history[i].value = arm11->reg_values[i];
643 arm11->reg_history[i].valid = arm11->reg_list[i].valid;
645 arm11->reg_list[i].valid = 0;
646 arm11->reg_list[i].dirty = 0;
651 /* poll current target status */
652 int arm11_poll(struct target_s *target)
656 arm11_common_t * arm11 = target->arch_info;
658 if (arm11->trst_active)
661 u32 dscr = arm11_read_DSCR(arm11);
663 DEBUG("DSCR %08x", dscr);
665 arm11_check_init(arm11, &dscr);
667 if (dscr & ARM11_DSCR_CORE_HALTED)
669 if (target->state != TARGET_HALTED)
671 enum target_state old_state = target->state;
673 DEBUG("enter TARGET_HALTED");
674 target->state = TARGET_HALTED;
675 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
676 arm11_on_enter_debug_state(arm11);
678 target_call_event_callbacks(target,
679 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
684 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
686 DEBUG("enter TARGET_RUNNING");
687 target->state = TARGET_RUNNING;
688 target->debug_reason = DBG_REASON_NOTHALTED;
694 /* architecture specific status reply */
695 int arm11_arch_state(struct target_s *target)
697 FNC_INFO_NOTIMPLEMENTED;
703 /* target request support */
704 int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer)
706 FNC_INFO_NOTIMPLEMENTED;
713 /* target execution control */
714 int arm11_halt(struct target_s *target)
718 arm11_common_t * arm11 = target->arch_info;
720 DEBUG("target->state: %s", target_state_strings[target->state]);
722 if (target->state == TARGET_HALTED)
724 WARNING("target was already halted");
725 return ERROR_TARGET_ALREADY_HALTED;
728 if (arm11->trst_active)
730 arm11->halt_requested = 1;
734 arm11_add_IR(arm11, ARM11_HALT, TAP_RTI);
736 jtag_execute_queue();
742 dscr = arm11_read_DSCR(arm11);
744 if (dscr & ARM11_DSCR_CORE_HALTED)
748 arm11_on_enter_debug_state(arm11);
750 enum target_state old_state = target->state;
752 target->state = TARGET_HALTED;
753 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
755 target_call_event_callbacks(target,
756 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
762 int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
766 // DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
767 // current, address, handle_breakpoints, debug_execution);
769 arm11_common_t * arm11 = target->arch_info;
771 DEBUG("target->state: %s", target_state_strings[target->state]);
773 if (target->state != TARGET_HALTED)
775 WARNING("target was not halted");
776 return ERROR_TARGET_NOT_HALTED;
782 INFO("RESUME PC %08x", R(PC));
784 /* clear breakpoints/watchpoints and VCR*/
785 arm11_sc7_clear_vbw(arm11);
787 /* Set up breakpoints */
788 if (!debug_execution)
790 /* check if one matches PC and step over it if necessary */
794 for (bp = target->breakpoints; bp; bp = bp->next)
796 if (bp->address == R(PC))
798 DEBUG("must step over %08x", bp->address);
799 arm11_step(target, 1, 0, 0);
804 /* set all breakpoints */
808 for (bp = target->breakpoints; bp; bp = bp->next)
810 arm11_sc7_action_t brp[2];
813 brp[0].address = ARM11_SC7_BVR0 + brp_num;
814 brp[0].value = bp->address;
816 brp[1].address = ARM11_SC7_BCR0 + brp_num;
817 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
819 arm11_sc7_run(arm11, brp, asizeof(brp));
821 DEBUG("Add BP %d at %08x", brp_num, bp->address);
826 arm11_sc7_set_vcr(arm11, arm11_vcr);
830 arm11_leave_debug_state(arm11);
832 arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
834 jtag_execute_queue();
838 u32 dscr = arm11_read_DSCR(arm11);
840 DEBUG("DSCR %08x", dscr);
842 if (dscr & ARM11_DSCR_CORE_RESTARTED)
846 if (!debug_execution)
848 target->state = TARGET_RUNNING;
849 target->debug_reason = DBG_REASON_NOTHALTED;
850 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
854 target->state = TARGET_DEBUG_RUNNING;
855 target->debug_reason = DBG_REASON_NOTHALTED;
856 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
862 int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
866 DEBUG("target->state: %s", target_state_strings[target->state]);
868 if (target->state != TARGET_HALTED)
870 WARNING("target was not halted");
871 return ERROR_TARGET_NOT_HALTED;
874 arm11_common_t * arm11 = target->arch_info;
879 INFO("STEP PC %08x", R(PC));
881 /** \todo TODO: Thumb not supported here */
883 u32 next_instruction;
885 arm11_read_memory_word(arm11, R(PC), &next_instruction);
887 /** skip over BKPT */
888 if ((next_instruction & 0xFFF00070) == 0xe1200070)
891 arm11->reg_list[ARM11_RC_PC].valid = 1;
892 arm11->reg_list[ARM11_RC_PC].dirty = 0;
893 INFO("Skipping BKPT");
895 /* ignore B to self */
896 else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
898 INFO("Not stepping jump to self");
902 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
905 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
906 * the VCR might be something worth looking into. */
909 /* Set up breakpoint for stepping */
911 arm11_sc7_action_t brp[2];
914 brp[0].address = ARM11_SC7_BVR0;
915 brp[0].value = R(PC);
917 brp[1].address = ARM11_SC7_BCR0;
918 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
920 arm11_sc7_run(arm11, brp, asizeof(brp));
924 arm11_leave_debug_state(arm11);
926 arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
928 jtag_execute_queue();
930 /** \todo TODO: add a timeout */
936 u32 dscr = arm11_read_DSCR(arm11);
938 DEBUG("DSCR %08x", dscr);
940 if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
941 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
945 /* clear breakpoint */
946 arm11_sc7_clear_vbw(arm11);
949 arm11_on_enter_debug_state(arm11);
952 // target->state = TARGET_HALTED;
953 target->debug_reason = DBG_REASON_SINGLESTEP;
955 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
961 /* target reset control */
962 int arm11_assert_reset(struct target_s *target)
967 /* assert reset lines */
968 /* resets only the DBGTAP, not the ARM */
970 jtag_add_reset(1, 0);
971 jtag_add_sleep(5000);
973 arm11_common_t * arm11 = target->arch_info;
974 arm11->trst_active = 1;
980 int arm11_deassert_reset(struct target_s *target)
985 DEBUG("target->state: %s", target_state_strings[target->state]);
987 /* deassert reset lines */
988 jtag_add_reset(0, 0);
990 arm11_common_t * arm11 = target->arch_info;
991 arm11->trst_active = false;
993 if (arm11->halt_requested)
994 return arm11_halt(target);
1000 int arm11_soft_reset_halt(struct target_s *target)
1002 FNC_INFO_NOTIMPLEMENTED;
1007 int arm11_prepare_reset_halt(struct target_s *target)
1009 FNC_INFO_NOTIMPLEMENTED;
1015 /* target register access for gdb */
1016 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size)
1020 arm11_common_t * arm11 = target->arch_info;
1022 if (target->state != TARGET_HALTED)
1024 return ERROR_TARGET_NOT_HALTED;
1027 *reg_list_size = ARM11_GDB_REGISTER_COUNT;
1028 *reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
1031 for (i = 16; i < 24; i++)
1033 (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
1036 (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
1040 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1042 if (arm11_reg_defs[i].gdb_num == -1)
1045 (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
1052 /* target memory access
1053 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1054 * count: number of items of <size>
1056 int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1058 /** \todo TODO: check if buffer cast to u32* and u16* might cause alignment problems */
1062 DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
1064 arm11_common_t * arm11 = target->arch_info;
1066 arm11_run_instr_data_prepare(arm11);
1068 /* MRC p14,0,r0,c0,c5,0 */
1069 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1074 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1075 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1079 /* ldrb r1, [r0], #1 */
1080 arm11_run_instr_no_data1(arm11, 0xe4d01001);
1083 /* MCR p14,0,R1,c0,c5,0 */
1084 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1092 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1094 u16 * buf16 = (u16*)buffer;
1098 /* ldrh r1, [r0], #2 */
1099 arm11_run_instr_no_data1(arm11, 0xe0d010b2);
1103 /* MCR p14,0,R1,c0,c5,0 */
1104 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1113 /* LDC p14,c5,[R0],#4 */
1114 arm11_run_instr_data_from_core(arm11, 0xecb05e01, (u32 *)buffer, count);
1118 arm11_run_instr_data_finish(arm11);
1123 int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1127 DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
1129 arm11_common_t * arm11 = target->arch_info;
1131 arm11_run_instr_data_prepare(arm11);
1133 /* MRC p14,0,r0,c0,c5,0 */
1134 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1139 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1143 /* MRC p14,0,r1,c0,c5,0 */
1144 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1146 /* strb r1, [r0], #1 */
1147 arm11_run_instr_no_data1(arm11, 0xe4c01001);
1153 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1155 u16 * buf16 = (u16*)buffer;
1159 /* MRC p14,0,r1,c0,c5,0 */
1160 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buf16++);
1162 /* strh r1, [r0], #2 */
1163 arm11_run_instr_no_data1(arm11, 0xe0c010b2);
1169 /** \todo TODO: check if buffer cast to u32* might cause alignment problems */
1171 if (!arm11_config_memwrite_burst)
1173 /* STC p14,c5,[R0],#4 */
1174 arm11_run_instr_data_to_core(arm11, 0xeca05e01, (u32 *)buffer, count);
1178 /* STC p14,c5,[R0],#4 */
1179 arm11_run_instr_data_to_core_noack(arm11, 0xeca05e01, (u32 *)buffer, count);
1186 /* r0 verification */
1190 /* MCR p14,0,R0,c0,c5,0 */
1191 arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1193 if (address + size * count != r0)
1195 ERROR("Data transfer failed. (%d)", (r0 - address) - size * count);
1197 if (arm11_config_memwrite_burst)
1198 ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1200 if (arm11_config_memwrite_error_fatal)
1207 arm11_run_instr_data_finish(arm11);
1216 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1217 int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer)
1221 return arm11_write_memory(target, address, 4, count, buffer);
1225 int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
1227 FNC_INFO_NOTIMPLEMENTED;
1233 /* target break-/watchpoint control
1234 * rw: 0 = write, 1 = read, 2 = access
1236 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1240 arm11_common_t * arm11 = target->arch_info;
1243 if (breakpoint->type == BKPT_SOFT)
1245 INFO("sw breakpoint requested, but software breakpoints not enabled");
1246 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1250 if (!arm11->free_brps)
1252 INFO("no breakpoint unit available for hardware breakpoint");
1253 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1256 if (breakpoint->length != 4)
1258 INFO("only breakpoints of four bytes length supported");
1259 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1267 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1271 arm11_common_t * arm11 = target->arch_info;
1278 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1280 FNC_INFO_NOTIMPLEMENTED;
1285 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1287 FNC_INFO_NOTIMPLEMENTED;
1293 /* target algorithm support */
1294 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_param, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
1296 FNC_INFO_NOTIMPLEMENTED;
1301 int arm11_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
1307 ERROR("'target arm11' 4th argument <jtag chain pos>");
1311 int chain_pos = strtoul(args[3], NULL, 0);
1313 NEW(arm11_common_t, arm11, 1);
1315 arm11->target = target;
1317 /* prepare JTAG information for the new target */
1318 arm11->jtag_info.chain_pos = chain_pos;
1319 arm11->jtag_info.scann_size = 5;
1321 arm_jtag_setup_connection(&arm11->jtag_info);
1323 jtag_device_t *device = jtag_get_device(chain_pos);
1325 if (device->ir_length != 5)
1327 ERROR("'target arm11' expects 'jtag_device 5 0x01 0x1F 0x1E'");
1331 target->arch_info = arm11;
1336 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
1340 arm11_common_t * arm11 = target->arch_info;
1344 arm11_add_IR(arm11, ARM11_IDCODE, -1);
1346 scan_field_t idcode_field;
1348 arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
1350 arm11_add_dr_scan_vc(1, &idcode_field, TAP_PD);
1354 arm11_add_debug_SCAN_N(arm11, 0x00, -1);
1356 arm11_add_IR(arm11, ARM11_INTEST, -1);
1358 scan_field_t chain0_fields[2];
1360 arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
1361 arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
1363 arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_RTI);
1365 jtag_execute_queue();
1368 switch (arm11->device_id & 0x0FFFF000)
1370 case 0x07B36000: INFO("found ARM1136"); break;
1371 case 0x07B56000: INFO("found ARM1156"); break;
1372 case 0x07B76000: INFO("found ARM1176"); break;
1375 ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1380 arm11->debug_version = (arm11->didr >> 16) & 0x0F;
1382 if (arm11->debug_version != ARM11_DEBUG_V6 &&
1383 arm11->debug_version != ARM11_DEBUG_V61)
1385 ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1390 arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1;
1391 arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1;
1393 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1394 arm11->free_brps = arm11->brp;
1395 arm11->free_wrps = arm11->wrp;
1397 DEBUG("IDCODE %08x IMPLEMENTOR %02x DIDR %08x",
1402 arm11_build_reg_cache(target);
1405 /* as a side-effect this reads DSCR and thus
1406 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1407 * as suggested by the spec.
1410 arm11_check_init(arm11, NULL);
1415 int arm11_quit(void)
1417 FNC_INFO_NOTIMPLEMENTED;
1422 /** Load a register that is marked !valid in the register cache */
1423 int arm11_get_reg(reg_t *reg)
1427 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1429 if (target->state != TARGET_HALTED)
1431 return ERROR_TARGET_NOT_HALTED;
1434 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1437 arm11_common_t *arm11 = target->arch_info;
1438 const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1444 /** Change a value in the register cache */
1445 int arm11_set_reg(reg_t *reg, u8 *buf)
1449 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1450 arm11_common_t *arm11 = target->arch_info;
1451 // const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1453 arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1461 void arm11_build_reg_cache(target_t *target)
1463 arm11_common_t *arm11 = target->arch_info;
1465 NEW(reg_cache_t, cache, 1);
1466 NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT);
1467 NEW(arm11_reg_state_t, arm11_reg_states, ARM11_REGCACHE_COUNT);
1469 if (arm11_regs_arch_type == -1)
1470 arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
1472 arm11->reg_list = reg_list;
1474 /* Build the process context cache */
1475 cache->name = "arm11 registers";
1477 cache->reg_list = reg_list;
1478 cache->num_regs = ARM11_REGCACHE_COUNT;
1480 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
1483 // armv7m->core_cache = cache;
1484 // armv7m->process_context = cache;
1488 /* Not very elegant assertion */
1489 if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
1490 ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
1491 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1493 ERROR("arm11->reg_values inconsistent (%d %d %d %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
1497 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1499 reg_t * r = reg_list + i;
1500 const arm11_reg_defs_t * rd = arm11_reg_defs + i;
1501 arm11_reg_state_t * rs = arm11_reg_states + i;
1505 r->value = (u8 *)(arm11->reg_values + i);
1508 r->bitfield_desc = NULL;
1509 r->num_bitfields = 0;
1510 r->arch_type = arm11_regs_arch_type;
1514 rs->target = target;
1520 int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, int * var, char * name)
1524 INFO("%s is %s.", name, *var ? "enabled" : "disabled");
1529 return ERROR_COMMAND_SYNTAX_ERROR;
1534 case 'f': /* false */
1536 case 'd': /* disable */
1542 case 't': /* true */
1544 case 'e': /* enable */
1550 INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
1556 #define BOOL_WRAPPER(name, print_name) \
1557 int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
1559 return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
1562 #define RC_TOP(name, descr, more) \
1564 command_t * new_cmd = register_command(cmd_ctx, top_cmd, name, NULL, COMMAND_ANY, descr); \
1565 command_t * top_cmd = new_cmd; \
1569 #define RC_FINAL(name, descr, handler) \
1570 register_command(cmd_ctx, top_cmd, name, handler, COMMAND_ANY, descr);
1572 #define RC_FINAL_BOOL(name, descr, var) \
1573 register_command(cmd_ctx, top_cmd, name, arm11_handle_bool_##var, COMMAND_ANY, descr);
1576 BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
1577 BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
1580 int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1584 arm11_vcr = strtoul(args[0], NULL, 0);
1588 return ERROR_COMMAND_SYNTAX_ERROR;
1591 INFO("VCR 0x%08X", arm11_vcr);
1596 int arm11_register_commands(struct command_context_s *cmd_ctx)
1600 command_t * top_cmd = NULL;
1602 RC_TOP( "arm11", "arm11 specific commands",
1604 RC_TOP( "memwrite", "Control memory write transfer mode",
1606 RC_FINAL_BOOL( "burst", "Enable/Disable non-standard but fast burst mode (default: enabled)",
1609 RC_FINAL_BOOL( "error_fatal",
1610 "Terminate program if transfer error was found (default: enabled)",
1611 memwrite_error_fatal)
1614 RC_FINAL( "vcr", "Control (Interrupt) Vector Catch Register",