1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
4 * Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com *
6 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
36 #define _DEBUG_INSTRUCTION_EXECUTION_
40 #define FNC_INFO LOG_DEBUG("-")
46 #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
48 #define FNC_INFO_NOTIMPLEMENTED
51 static void arm11_on_enter_debug_state(arm11_common_t * arm11);
53 bool arm11_config_memwrite_burst = true;
54 bool arm11_config_memwrite_error_fatal = true;
57 #define ARM11_HANDLER(x) \
60 target_type_t arm11_target =
65 ARM11_HANDLER(arch_state),
67 ARM11_HANDLER(target_request_data),
70 ARM11_HANDLER(resume),
73 ARM11_HANDLER(assert_reset),
74 ARM11_HANDLER(deassert_reset),
75 ARM11_HANDLER(soft_reset_halt),
77 ARM11_HANDLER(get_gdb_reg_list),
79 ARM11_HANDLER(read_memory),
80 ARM11_HANDLER(write_memory),
82 ARM11_HANDLER(bulk_write_memory),
84 ARM11_HANDLER(checksum_memory),
86 ARM11_HANDLER(add_breakpoint),
87 ARM11_HANDLER(remove_breakpoint),
88 ARM11_HANDLER(add_watchpoint),
89 ARM11_HANDLER(remove_watchpoint),
91 ARM11_HANDLER(run_algorithm),
93 ARM11_HANDLER(register_commands),
94 ARM11_HANDLER(target_create),
95 ARM11_HANDLER(init_target),
96 ARM11_HANDLER(examine),
100 int arm11_regs_arch_type = -1;
118 ARM11_REGISTER_SPSR_FIQ,
119 ARM11_REGISTER_SPSR_SVC,
120 ARM11_REGISTER_SPSR_ABT,
121 ARM11_REGISTER_SPSR_IRQ,
122 ARM11_REGISTER_SPSR_UND,
123 ARM11_REGISTER_SPSR_MON,
132 typedef struct arm11_reg_defs_s
137 enum arm11_regtype type;
140 /* update arm11_regcache_ids when changing this */
141 static const arm11_reg_defs_t arm11_reg_defs[] =
143 {"r0", 0, 0, ARM11_REGISTER_CORE},
144 {"r1", 1, 1, ARM11_REGISTER_CORE},
145 {"r2", 2, 2, ARM11_REGISTER_CORE},
146 {"r3", 3, 3, ARM11_REGISTER_CORE},
147 {"r4", 4, 4, ARM11_REGISTER_CORE},
148 {"r5", 5, 5, ARM11_REGISTER_CORE},
149 {"r6", 6, 6, ARM11_REGISTER_CORE},
150 {"r7", 7, 7, ARM11_REGISTER_CORE},
151 {"r8", 8, 8, ARM11_REGISTER_CORE},
152 {"r9", 9, 9, ARM11_REGISTER_CORE},
153 {"r10", 10, 10, ARM11_REGISTER_CORE},
154 {"r11", 11, 11, ARM11_REGISTER_CORE},
155 {"r12", 12, 12, ARM11_REGISTER_CORE},
156 {"sp", 13, 13, ARM11_REGISTER_CORE},
157 {"lr", 14, 14, ARM11_REGISTER_CORE},
158 {"pc", 15, 15, ARM11_REGISTER_CORE},
160 #if ARM11_REGCACHE_FREGS
161 {"f0", 0, 16, ARM11_REGISTER_FX},
162 {"f1", 1, 17, ARM11_REGISTER_FX},
163 {"f2", 2, 18, ARM11_REGISTER_FX},
164 {"f3", 3, 19, ARM11_REGISTER_FX},
165 {"f4", 4, 20, ARM11_REGISTER_FX},
166 {"f5", 5, 21, ARM11_REGISTER_FX},
167 {"f6", 6, 22, ARM11_REGISTER_FX},
168 {"f7", 7, 23, ARM11_REGISTER_FX},
169 {"fps", 0, 24, ARM11_REGISTER_FPS},
172 {"cpsr", 0, 25, ARM11_REGISTER_CPSR},
174 #if ARM11_REGCACHE_MODEREGS
175 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ},
176 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ},
177 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ},
178 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ},
179 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ},
180 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ},
181 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ},
182 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ},
184 {"r13_svc", 13, -1, ARM11_REGISTER_SVC},
185 {"r14_svc", 14, -1, ARM11_REGISTER_SVC},
186 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC},
188 {"r13_abt", 13, -1, ARM11_REGISTER_ABT},
189 {"r14_abt", 14, -1, ARM11_REGISTER_ABT},
190 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT},
192 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ},
193 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ},
194 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ},
196 {"r13_und", 13, -1, ARM11_REGISTER_UND},
197 {"r14_und", 14, -1, ARM11_REGISTER_UND},
198 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND},
201 {"r13_mon", 13, -1, ARM11_REGISTER_MON},
202 {"r14_mon", 14, -1, ARM11_REGISTER_MON},
203 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON},
206 /* Debug Registers */
207 {"dscr", 0, -1, ARM11_REGISTER_DSCR},
208 {"wdtr", 0, -1, ARM11_REGISTER_WDTR},
209 {"rdtr", 0, -1, ARM11_REGISTER_RDTR},
212 enum arm11_regcache_ids
215 ARM11_RC_RX = ARM11_RC_R0,
230 ARM11_RC_SP = ARM11_RC_R13,
232 ARM11_RC_LR = ARM11_RC_R14,
234 ARM11_RC_PC = ARM11_RC_R15,
236 #if ARM11_REGCACHE_FREGS
238 ARM11_RC_FX = ARM11_RC_F0,
251 #if ARM11_REGCACHE_MODEREGS
289 #define ARM11_GDB_REGISTER_COUNT 26
291 u8 arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
293 reg_t arm11_gdb_dummy_fp_reg =
295 "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
298 u8 arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
300 reg_t arm11_gdb_dummy_fps_reg =
302 "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
307 /** Check and if necessary take control of the system
309 * \param arm11 Target state variable.
310 * \param dscr If the current DSCR content is
311 * available a pointer to a word holding the
312 * DSCR can be passed. Otherwise use NULL.
314 void arm11_check_init(arm11_common_t * arm11, u32 * dscr)
318 u32 dscr_local_tmp_copy;
322 dscr = &dscr_local_tmp_copy;
323 *dscr = arm11_read_DSCR(arm11);
326 if (!(*dscr & ARM11_DSCR_MODE_SELECT))
328 LOG_DEBUG("Bringing target into debug mode");
330 *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
331 arm11_write_DSCR(arm11, *dscr);
333 /* add further reset initialization here */
335 arm11->simulate_reset_on_next_halt = true;
337 if (*dscr & ARM11_DSCR_CORE_HALTED)
339 /** \todo TODO: this needs further scrutiny because
340 * arm11_on_enter_debug_state() never gets properly called
343 arm11->target->state = TARGET_HALTED;
344 arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
348 arm11->target->state = TARGET_RUNNING;
349 arm11->target->debug_reason = DBG_REASON_NOTHALTED;
352 arm11_sc7_clear_vbw(arm11);
359 (arm11->reg_values[ARM11_RC_##x])
361 /** Save processor state.
363 * This is called when the HALT instruction has succeeded
364 * or on other occasions that stop the processor.
367 static void arm11_on_enter_debug_state(arm11_common_t * arm11)
372 for(i = 0; i < asizeof(arm11->reg_values); i++)
374 arm11->reg_list[i].valid = 1;
375 arm11->reg_list[i].dirty = 0;
380 R(DSCR) = arm11_read_DSCR(arm11);
384 if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
386 arm11_add_debug_SCAN_N(arm11, 0x05, -1);
388 arm11_add_IR(arm11, ARM11_INTEST, -1);
390 scan_field_t chain5_fields[3];
392 arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
393 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
394 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
396 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
400 arm11->reg_list[ARM11_RC_WDTR].valid = 0;
404 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
405 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
406 ARM1136 seems to require this to issue ITR's as well */
408 u32 new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
410 /* this executes JTAG queue: */
412 arm11_write_DSCR(arm11, new_dscr);
416 Before executing any instruction in debug state you have to drain the write buffer.
417 This ensures that no imprecise Data Aborts can return at a later point:*/
419 /** \todo TODO: Test drain write buffer. */
424 /* MRC p14,0,R0,c5,c10,0 */
425 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
427 /* mcr 15, 0, r0, cr7, cr10, {4} */
428 arm11_run_instr_no_data1(arm11, 0xee070f9a);
430 u32 dscr = arm11_read_DSCR(arm11);
432 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
434 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
436 arm11_run_instr_no_data1(arm11, 0xe320f000);
438 dscr = arm11_read_DSCR(arm11);
440 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
447 arm11_run_instr_data_prepare(arm11);
451 /** \todo TODO: handle other mode registers */
454 for (i = 0; i < 15; i++)
456 /* MCR p14,0,R?,c0,c5,0 */
457 arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
462 /* check rDTRfull in DSCR */
464 if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
466 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
467 arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
471 arm11->reg_list[ARM11_RC_RDTR].valid = 0;
476 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
477 arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
481 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
482 arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
484 /* adjust PC depending on ARM state */
486 if (R(CPSR) & ARM11_CPSR_J) /* Java state */
488 arm11->reg_values[ARM11_RC_PC] -= 0;
490 else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */
492 arm11->reg_values[ARM11_RC_PC] -= 4;
496 arm11->reg_values[ARM11_RC_PC] -= 8;
499 if (arm11->simulate_reset_on_next_halt)
501 arm11->simulate_reset_on_next_halt = false;
503 LOG_DEBUG("Reset c1 Control Register");
505 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
507 /* MCR p15,0,R0,c1,c0,0 */
508 arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
512 arm11_run_instr_data_finish(arm11);
514 arm11_dump_reg_changes(arm11);
517 void arm11_dump_reg_changes(arm11_common_t * arm11)
520 for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
522 if (!arm11->reg_list[i].valid)
524 if (arm11->reg_history[i].valid)
525 LOG_INFO("%8s INVALID (%08x)", arm11_reg_defs[i].name, arm11->reg_history[i].value);
529 if (arm11->reg_history[i].valid)
531 if (arm11->reg_history[i].value != arm11->reg_values[i])
532 LOG_INFO("%8s %08x (%08x)", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
536 LOG_INFO("%8s %08x (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
542 /** Restore processor state
544 * This is called in preparation for the RESTART function.
547 void arm11_leave_debug_state(arm11_common_t * arm11)
551 arm11_run_instr_data_prepare(arm11);
553 /** \todo TODO: handle other mode registers */
555 /* restore R1 - R14 */
557 for (i = 1; i < 15; i++)
559 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
562 /* MRC p14,0,r?,c0,c5,0 */
563 arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
565 // LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
568 arm11_run_instr_data_finish(arm11);
570 /* spec says clear wDTR and rDTR; we assume they are clear as
571 otherwise our programming would be sloppy */
574 u32 DSCR = arm11_read_DSCR(arm11);
576 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
578 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08x)", DSCR);
582 arm11_run_instr_data_prepare(arm11);
584 /* restore original wDTR */
586 if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
588 /* MCR p14,0,R0,c0,c5,0 */
589 arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
595 arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
600 arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
604 /* MRC p14,0,r0,c0,c5,0 */
605 arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
607 arm11_run_instr_data_finish(arm11);
611 arm11_write_DSCR(arm11, R(DSCR));
615 if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
617 arm11_add_debug_SCAN_N(arm11, 0x05, -1);
619 arm11_add_IR(arm11, ARM11_EXTEST, -1);
621 scan_field_t chain5_fields[3];
623 u8 Ready = 0; /* ignored */
624 u8 Valid = 0; /* ignored */
626 arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
627 arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
628 arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
630 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
633 arm11_record_register_history(arm11);
636 void arm11_record_register_history(arm11_common_t * arm11)
639 for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
641 arm11->reg_history[i].value = arm11->reg_values[i];
642 arm11->reg_history[i].valid = arm11->reg_list[i].valid;
644 arm11->reg_list[i].valid = 0;
645 arm11->reg_list[i].dirty = 0;
650 /* poll current target status */
651 int arm11_poll(struct target_s *target)
655 arm11_common_t * arm11 = target->arch_info;
657 if (arm11->trst_active)
660 u32 dscr = arm11_read_DSCR(arm11);
662 LOG_DEBUG("DSCR %08x", dscr);
664 arm11_check_init(arm11, &dscr);
666 if (dscr & ARM11_DSCR_CORE_HALTED)
668 if (target->state != TARGET_HALTED)
670 enum target_state old_state = target->state;
672 LOG_DEBUG("enter TARGET_HALTED");
673 target->state = TARGET_HALTED;
674 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
675 arm11_on_enter_debug_state(arm11);
677 target_call_event_callbacks(target,
678 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
683 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
685 LOG_DEBUG("enter TARGET_RUNNING");
686 target->state = TARGET_RUNNING;
687 target->debug_reason = DBG_REASON_NOTHALTED;
693 /* architecture specific status reply */
694 int arm11_arch_state(struct target_s *target)
696 FNC_INFO_NOTIMPLEMENTED;
701 /* target request support */
702 int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer)
704 FNC_INFO_NOTIMPLEMENTED;
709 /* target execution control */
710 int arm11_halt(struct target_s *target)
712 int retval = ERROR_OK;
716 arm11_common_t * arm11 = target->arch_info;
718 LOG_DEBUG("target->state: %s",
719 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
721 if (target->state == TARGET_UNKNOWN)
723 arm11->simulate_reset_on_next_halt = true;
726 if (target->state == TARGET_HALTED)
728 LOG_DEBUG("target was already halted");
732 if (arm11->trst_active)
734 arm11->halt_requested = true;
738 arm11_add_IR(arm11, ARM11_HALT, TAP_RTI);
740 if((retval = jtag_execute_queue()) != ERROR_OK)
749 dscr = arm11_read_DSCR(arm11);
751 if (dscr & ARM11_DSCR_CORE_HALTED)
755 arm11_on_enter_debug_state(arm11);
757 enum target_state old_state = target->state;
759 target->state = TARGET_HALTED;
760 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
762 if((retval = target_call_event_callbacks(target,
763 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED)) != ERROR_OK)
771 int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
773 int retval = ERROR_OK;
777 // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
778 // current, address, handle_breakpoints, debug_execution);
780 arm11_common_t * arm11 = target->arch_info;
782 LOG_DEBUG("target->state: %s",
783 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
786 if (target->state != TARGET_HALTED)
788 LOG_ERROR("Target not halted");
789 return ERROR_TARGET_NOT_HALTED;
795 LOG_INFO("RESUME PC %08x%s", R(PC), !current ? "!" : "");
797 /* clear breakpoints/watchpoints and VCR*/
798 arm11_sc7_clear_vbw(arm11);
800 /* Set up breakpoints */
801 if (!debug_execution)
803 /* check if one matches PC and step over it if necessary */
807 for (bp = target->breakpoints; bp; bp = bp->next)
809 if (bp->address == R(PC))
811 LOG_DEBUG("must step over %08x", bp->address);
812 arm11_step(target, 1, 0, 0);
817 /* set all breakpoints */
821 for (bp = target->breakpoints; bp; bp = bp->next)
823 arm11_sc7_action_t brp[2];
826 brp[0].address = ARM11_SC7_BVR0 + brp_num;
827 brp[0].value = bp->address;
829 brp[1].address = ARM11_SC7_BCR0 + brp_num;
830 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
832 arm11_sc7_run(arm11, brp, asizeof(brp));
834 LOG_DEBUG("Add BP " ZU " at %08x", brp_num, bp->address);
839 arm11_sc7_set_vcr(arm11, arm11_vcr);
842 arm11_leave_debug_state(arm11);
844 arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
846 if((retval = jtag_execute_queue()) != ERROR_OK)
853 u32 dscr = arm11_read_DSCR(arm11);
855 LOG_DEBUG("DSCR %08x", dscr);
857 if (dscr & ARM11_DSCR_CORE_RESTARTED)
861 if (!debug_execution)
863 target->state = TARGET_RUNNING;
864 target->debug_reason = DBG_REASON_NOTHALTED;
865 if((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
872 target->state = TARGET_DEBUG_RUNNING;
873 target->debug_reason = DBG_REASON_NOTHALTED;
874 if((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
883 int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
885 int retval = ERROR_OK;
889 LOG_DEBUG("target->state: %s",
890 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
892 if (target->state != TARGET_HALTED)
894 LOG_WARNING("target was not halted");
895 return ERROR_TARGET_NOT_HALTED;
898 arm11_common_t * arm11 = target->arch_info;
903 LOG_INFO("STEP PC %08x%s", R(PC), !current ? "!" : "");
905 /** \todo TODO: Thumb not supported here */
907 u32 next_instruction;
909 arm11_read_memory_word(arm11, R(PC), &next_instruction);
912 if ((next_instruction & 0xFFF00070) == 0xe1200070)
915 arm11->reg_list[ARM11_RC_PC].valid = 1;
916 arm11->reg_list[ARM11_RC_PC].dirty = 0;
917 LOG_INFO("Skipping BKPT");
919 /* skip over Wait for interrupt / Standby */
920 /* mcr 15, 0, r?, cr7, cr0, {4} */
921 else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
924 arm11->reg_list[ARM11_RC_PC].valid = 1;
925 arm11->reg_list[ARM11_RC_PC].dirty = 0;
926 LOG_INFO("Skipping WFI");
928 /* ignore B to self */
929 else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
931 LOG_INFO("Not stepping jump to self");
935 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
938 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
939 * the VCR might be something worth looking into. */
942 /* Set up breakpoint for stepping */
944 arm11_sc7_action_t brp[2];
947 brp[0].address = ARM11_SC7_BVR0;
948 brp[0].value = R(PC);
950 brp[1].address = ARM11_SC7_BCR0;
951 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
953 arm11_sc7_run(arm11, brp, asizeof(brp));
957 arm11_leave_debug_state(arm11);
959 arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
961 if((retval = jtag_execute_queue()) != ERROR_OK)
966 /** \todo TODO: add a timeout */
972 u32 dscr = arm11_read_DSCR(arm11);
974 LOG_DEBUG("DSCR %08x", dscr);
976 if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
977 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
981 /* clear breakpoint */
982 arm11_sc7_clear_vbw(arm11);
985 arm11_on_enter_debug_state(arm11);
988 // target->state = TARGET_HALTED;
989 target->debug_reason = DBG_REASON_SINGLESTEP;
991 if((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
999 /* target reset control */
1000 int arm11_assert_reset(struct target_s *target)
1005 /* assert reset lines */
1006 /* resets only the DBGTAP, not the ARM */
1008 jtag_add_reset(1, 0);
1009 jtag_add_sleep(5000);
1011 arm11_common_t * arm11 = target->arch_info;
1012 arm11->trst_active = true;
1015 if (target->reset_halt)
1018 if ((retval = target_halt(target))!=ERROR_OK)
1025 int arm11_deassert_reset(struct target_s *target)
1030 LOG_DEBUG("target->state: %s",
1031 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
1034 /* deassert reset lines */
1035 jtag_add_reset(0, 0);
1037 arm11_common_t * arm11 = target->arch_info;
1038 arm11->trst_active = false;
1040 if (arm11->halt_requested)
1041 return arm11_halt(target);
1047 int arm11_soft_reset_halt(struct target_s *target)
1049 FNC_INFO_NOTIMPLEMENTED;
1054 /* target register access for gdb */
1055 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size)
1059 arm11_common_t * arm11 = target->arch_info;
1061 *reg_list_size = ARM11_GDB_REGISTER_COUNT;
1062 *reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
1065 for (i = 16; i < 24; i++)
1067 (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
1070 (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
1073 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1075 if (arm11_reg_defs[i].gdb_num == -1)
1078 (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
1084 /* target memory access
1085 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1086 * count: number of items of <size>
1088 int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1090 /** \todo TODO: check if buffer cast to u32* and u16* might cause alignment problems */
1094 if (target->state != TARGET_HALTED)
1096 LOG_WARNING("target was not halted");
1097 return ERROR_TARGET_NOT_HALTED;
1100 LOG_DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
1102 arm11_common_t * arm11 = target->arch_info;
1104 arm11_run_instr_data_prepare(arm11);
1106 /* MRC p14,0,r0,c0,c5,0 */
1107 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1112 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1113 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1116 for (i = 0; i < count; i++)
1118 /* ldrb r1, [r0], #1 */
1119 arm11_run_instr_no_data1(arm11, 0xe4d01001);
1122 /* MCR p14,0,R1,c0,c5,0 */
1123 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1132 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1134 u16 * buf16 = (u16*)buffer;
1137 for (i = 0; i < count; i++)
1139 /* ldrh r1, [r0], #2 */
1140 arm11_run_instr_no_data1(arm11, 0xe0d010b2);
1144 /* MCR p14,0,R1,c0,c5,0 */
1145 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1155 /* LDC p14,c5,[R0],#4 */
1156 arm11_run_instr_data_from_core(arm11, 0xecb05e01, (u32 *)buffer, count);
1160 arm11_run_instr_data_finish(arm11);
1165 int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1169 if (target->state != TARGET_HALTED)
1171 LOG_WARNING("target was not halted");
1172 return ERROR_TARGET_NOT_HALTED;
1175 LOG_DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
1177 arm11_common_t * arm11 = target->arch_info;
1179 arm11_run_instr_data_prepare(arm11);
1181 /* MRC p14,0,r0,c0,c5,0 */
1182 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1188 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1191 for (i = 0; i < count; i++)
1193 /* MRC p14,0,r1,c0,c5,0 */
1194 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1196 /* strb r1, [r0], #1 */
1197 arm11_run_instr_no_data1(arm11, 0xe4c01001);
1205 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1207 u16 * buf16 = (u16*)buffer;
1210 for (i = 0; i < count; i++)
1212 /* MRC p14,0,r1,c0,c5,0 */
1213 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buf16++);
1215 /* strh r1, [r0], #2 */
1216 arm11_run_instr_no_data1(arm11, 0xe0c010b2);
1223 /** \todo TODO: check if buffer cast to u32* might cause alignment problems */
1225 if (!arm11_config_memwrite_burst)
1227 /* STC p14,c5,[R0],#4 */
1228 arm11_run_instr_data_to_core(arm11, 0xeca05e01, (u32 *)buffer, count);
1232 /* STC p14,c5,[R0],#4 */
1233 arm11_run_instr_data_to_core_noack(arm11, 0xeca05e01, (u32 *)buffer, count);
1240 /* r0 verification */
1244 /* MCR p14,0,R0,c0,c5,0 */
1245 arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1247 if (address + size * count != r0)
1249 LOG_ERROR("Data transfer failed. (%d)", (r0 - address) - size * count);
1251 if (arm11_config_memwrite_burst)
1252 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1254 if (arm11_config_memwrite_error_fatal)
1260 arm11_run_instr_data_finish(arm11);
1266 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1267 int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer)
1271 if (target->state != TARGET_HALTED)
1273 LOG_WARNING("target was not halted");
1274 return ERROR_TARGET_NOT_HALTED;
1277 return arm11_write_memory(target, address, 4, count, buffer);
1280 int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
1282 FNC_INFO_NOTIMPLEMENTED;
1287 /* target break-/watchpoint control
1288 * rw: 0 = write, 1 = read, 2 = access
1290 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1294 arm11_common_t * arm11 = target->arch_info;
1297 if (breakpoint->type == BKPT_SOFT)
1299 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1300 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1304 if (!arm11->free_brps)
1306 LOG_INFO("no breakpoint unit available for hardware breakpoint");
1307 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1310 if (breakpoint->length != 4)
1312 LOG_INFO("only breakpoints of four bytes length supported");
1313 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1321 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1325 arm11_common_t * arm11 = target->arch_info;
1332 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1334 FNC_INFO_NOTIMPLEMENTED;
1339 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1341 FNC_INFO_NOTIMPLEMENTED;
1346 // HACKHACKHACK - FIXME mode/state
1347 /* target algorithm support */
1348 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params,
1349 int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point,
1350 int timeout_ms, void *arch_info)
1352 arm11_common_t *arm11 = target->arch_info;
1353 armv4_5_algorithm_t *arm11_algorithm_info = arch_info;
1354 // enum armv4_5_state core_state = arm11->core_state;
1355 // enum armv4_5_mode core_mode = arm11->core_mode;
1358 int exit_breakpoint_size = 0;
1360 int retval = ERROR_OK;
1361 LOG_DEBUG("Running algorithm");
1363 if (arm11_algorithm_info->common_magic != ARMV4_5_COMMON_MAGIC)
1365 LOG_ERROR("current target isn't an ARMV4/5 target");
1366 return ERROR_TARGET_INVALID;
1369 if (target->state != TARGET_HALTED)
1371 LOG_WARNING("target not halted");
1372 return ERROR_TARGET_NOT_HALTED;
1376 // if (armv4_5_mode_to_number(arm11->core_mode)==-1)
1377 // return ERROR_FAIL;
1380 for (i = 0; i < 16; i++)
1382 context[i] = buf_get_u32((u8*)(&arm11->reg_values[i]),0,32);
1383 LOG_DEBUG("Save %i: 0x%x",i,context[i]);
1386 cpsr = buf_get_u32((u8*)(arm11->reg_values+ARM11_RC_CPSR),0,32);
1387 LOG_DEBUG("Save CPSR: 0x%x", cpsr);
1389 for (i = 0; i < num_mem_params; i++)
1391 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1394 // Set register parameters
1395 for (i = 0; i < num_reg_params; i++)
1397 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1400 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1404 if (reg->size != reg_params[i].size)
1406 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1409 arm11_set_reg(reg,reg_params[i].value);
1410 // printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
1413 exit_breakpoint_size = 4;
1415 /* arm11->core_state = arm11_algorithm_info->core_state;
1416 if (arm11->core_state == ARMV4_5_STATE_ARM)
1417 exit_breakpoint_size = 4;
1418 else if (arm11->core_state == ARMV4_5_STATE_THUMB)
1419 exit_breakpoint_size = 2;
1422 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1426 if (arm11_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
1428 LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info->core_mode);
1429 buf_set_u32(arm11->reg_list[ARM11_RC_CPSR].value, 0, 5, arm11_algorithm_info->core_mode);
1430 arm11->reg_list[ARM11_RC_CPSR].dirty = 1;
1431 arm11->reg_list[ARM11_RC_CPSR].valid = 1;
1434 if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
1436 LOG_ERROR("can't add breakpoint to finish algorithm execution");
1437 retval = ERROR_TARGET_FAILURE;
1441 // no debug, otherwise breakpoint is not set
1442 if((retval = target_resume(target, 0, entry_point, 1, 0)) != ERROR_OK)
1447 if((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK)
1452 if (target->state != TARGET_HALTED)
1454 if ((retval=target_halt(target))!=ERROR_OK)
1456 if ((retval=target_wait_state(target, TARGET_HALTED, 500))!=ERROR_OK)
1460 retval = ERROR_TARGET_TIMEOUT;
1461 goto del_breakpoint;
1464 if (buf_get_u32(arm11->reg_list[15].value, 0, 32) != exit_point)
1466 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4x",
1467 buf_get_u32(arm11->reg_list[15].value, 0, 32));
1468 retval = ERROR_TARGET_TIMEOUT;
1469 goto del_breakpoint;
1472 for (i = 0; i < num_mem_params; i++)
1474 if (mem_params[i].direction != PARAM_OUT)
1475 target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1478 for (i = 0; i < num_reg_params; i++)
1480 if (reg_params[i].direction != PARAM_OUT)
1482 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1485 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1489 if (reg->size != reg_params[i].size)
1491 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1495 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1500 breakpoint_remove(target, exit_point);
1504 for (i = 0; i < 16; i++)
1506 LOG_DEBUG("restoring register %s with value 0x%8.8x",
1507 arm11->reg_list[i].name, context[i]);
1508 arm11_set_reg(&arm11->reg_list[i], (u8*)&context[i]);
1510 LOG_DEBUG("restoring CPSR with value 0x%8.8x", cpsr);
1511 arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (u8*)&cpsr);
1513 // arm11->core_state = core_state;
1514 // arm11->core_mode = core_mode;
1519 int arm11_target_create(struct target_s *target, Jim_Interp *interp)
1521 int retval = ERROR_OK;
1524 NEW(arm11_common_t, arm11, 1);
1526 arm11->target = target;
1528 /* prepare JTAG information for the new target */
1529 arm11->jtag_info.chain_pos = target->chain_position;
1530 arm11->jtag_info.scann_size = 5;
1532 if((retval = arm_jtag_setup_connection(&arm11->jtag_info)) != ERROR_OK)
1537 jtag_device_t *device = jtag_get_device(target->chain_position);
1539 if (device->ir_length != 5)
1541 LOG_ERROR("'target arm11' expects 'jtag_device 5 0x01 0x1F 0x1E'");
1542 return ERROR_COMMAND_SYNTAX_ERROR;
1545 target->arch_info = arm11;
1550 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
1552 /* Initialize anything we can set up without talking to the target */
1553 return arm11_build_reg_cache(target);
1557 /* talk to the target and set things up */
1558 int arm11_examine(struct target_s *target)
1563 arm11_common_t * arm11 = target->arch_info;
1567 arm11_add_IR(arm11, ARM11_IDCODE, -1);
1569 scan_field_t idcode_field;
1571 arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
1573 arm11_add_dr_scan_vc(1, &idcode_field, TAP_PD);
1577 arm11_add_debug_SCAN_N(arm11, 0x00, -1);
1579 arm11_add_IR(arm11, ARM11_INTEST, -1);
1581 scan_field_t chain0_fields[2];
1583 arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
1584 arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
1586 arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_RTI);
1588 if ((retval=jtag_execute_queue())!=ERROR_OK)
1592 switch (arm11->device_id & 0x0FFFF000)
1594 case 0x07B36000: LOG_INFO("found ARM1136"); break;
1595 case 0x07B56000: LOG_INFO("found ARM1156"); break;
1596 case 0x07B76000: LOG_INFO("found ARM1176"); break;
1599 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1604 arm11->debug_version = (arm11->didr >> 16) & 0x0F;
1606 if (arm11->debug_version != ARM11_DEBUG_V6 &&
1607 arm11->debug_version != ARM11_DEBUG_V61)
1609 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1614 arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1;
1615 arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1;
1617 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1618 arm11->free_brps = arm11->brp;
1619 arm11->free_wrps = arm11->wrp;
1621 LOG_DEBUG("IDCODE %08x IMPLEMENTOR %02x DIDR %08x",
1626 /* as a side-effect this reads DSCR and thus
1627 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1628 * as suggested by the spec.
1631 arm11_check_init(arm11, NULL);
1633 target->type->examined = 1;
1638 int arm11_quit(void)
1640 FNC_INFO_NOTIMPLEMENTED;
1645 /** Load a register that is marked !valid in the register cache */
1646 int arm11_get_reg(reg_t *reg)
1650 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1652 if (target->state != TARGET_HALTED)
1654 LOG_WARNING("target was not halted");
1655 return ERROR_TARGET_NOT_HALTED;
1658 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1661 arm11_common_t *arm11 = target->arch_info;
1662 const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1668 /** Change a value in the register cache */
1669 int arm11_set_reg(reg_t *reg, u8 *buf)
1673 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1674 arm11_common_t *arm11 = target->arch_info;
1675 // const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1677 arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1684 int arm11_build_reg_cache(target_t *target)
1686 arm11_common_t *arm11 = target->arch_info;
1688 NEW(reg_cache_t, cache, 1);
1689 NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT);
1690 NEW(arm11_reg_state_t, arm11_reg_states, ARM11_REGCACHE_COUNT);
1692 if (arm11_regs_arch_type == -1)
1693 arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
1695 register_init_dummy(&arm11_gdb_dummy_fp_reg);
1696 register_init_dummy(&arm11_gdb_dummy_fps_reg);
1698 arm11->reg_list = reg_list;
1700 /* Build the process context cache */
1701 cache->name = "arm11 registers";
1703 cache->reg_list = reg_list;
1704 cache->num_regs = ARM11_REGCACHE_COUNT;
1706 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
1709 arm11->core_cache = cache;
1710 // armv7m->process_context = cache;
1714 /* Not very elegant assertion */
1715 if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
1716 ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
1717 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1719 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
1723 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1725 reg_t * r = reg_list + i;
1726 const arm11_reg_defs_t * rd = arm11_reg_defs + i;
1727 arm11_reg_state_t * rs = arm11_reg_states + i;
1731 r->value = (u8 *)(arm11->reg_values + i);
1734 r->bitfield_desc = NULL;
1735 r->num_bitfields = 0;
1736 r->arch_type = arm11_regs_arch_type;
1740 rs->target = target;
1745 int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name)
1749 LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled");
1754 return ERROR_COMMAND_SYNTAX_ERROR;
1759 case 'f': /* false */
1761 case 'd': /* disable */
1767 case 't': /* true */
1769 case 'e': /* enable */
1775 LOG_INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
1780 #define BOOL_WRAPPER(name, print_name) \
1781 int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
1783 return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
1786 #define RC_TOP(name, descr, more) \
1788 command_t * new_cmd = register_command(cmd_ctx, top_cmd, name, NULL, COMMAND_ANY, descr); \
1789 command_t * top_cmd = new_cmd; \
1793 #define RC_FINAL(name, descr, handler) \
1794 register_command(cmd_ctx, top_cmd, name, handler, COMMAND_ANY, descr);
1796 #define RC_FINAL_BOOL(name, descr, var) \
1797 register_command(cmd_ctx, top_cmd, name, arm11_handle_bool_##var, COMMAND_ANY, descr);
1799 BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
1800 BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
1802 int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1806 arm11_vcr = strtoul(args[0], NULL, 0);
1810 return ERROR_COMMAND_SYNTAX_ERROR;
1813 LOG_INFO("VCR 0x%08X", arm11_vcr);
1817 const u32 arm11_coproc_instruction_limits[] =
1819 15, /* coprocessor */
1824 0xFFFFFFFF, /* value */
1827 const char arm11_mrc_syntax[] = "Syntax: mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.";
1828 const char arm11_mcr_syntax[] = "Syntax: mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.";
1830 arm11_common_t * arm11_find_target(const char * arg)
1832 size_t jtag_target = strtoul(arg, NULL, 0);
1835 for (t = all_targets; t; t = t->next)
1837 if (strcmp(t->type->name,"arm11"))
1840 arm11_common_t * arm11 = t->arch_info;
1842 if (arm11->jtag_info.chain_pos != jtag_target)
1851 int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool read)
1853 if (argc != (read ? 6 : 7))
1855 LOG_ERROR("Invalid number of arguments. %s", read ? arm11_mrc_syntax : arm11_mcr_syntax);
1859 arm11_common_t * arm11 = arm11_find_target(args[0]);
1863 LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device. %s",
1864 read ? arm11_mrc_syntax : arm11_mcr_syntax);
1870 if (arm11->target->state != TARGET_HALTED)
1872 LOG_WARNING("target was not halted");
1873 return ERROR_TARGET_NOT_HALTED;
1879 for (i = 0; i < (read ? 5 : 6); i++)
1881 values[i] = strtoul(args[i + 1], NULL, 0);
1883 if (values[i] > arm11_coproc_instruction_limits[i])
1885 LOG_ERROR("Parameter %ld out of bounds (%d max). %s",
1886 (long)(i + 2), arm11_coproc_instruction_limits[i],
1887 read ? arm11_mrc_syntax : arm11_mcr_syntax);
1892 u32 instr = 0xEE000010 |
1900 instr |= 0x00100000;
1902 arm11_run_instr_data_prepare(arm11);
1907 arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
1909 LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08x (%d)",
1910 values[0], values[1], values[2], values[3], values[4], result, result);
1914 arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]);
1916 LOG_INFO("MRC p%d, %d, R0 (#0x%08x), c%d, c%d, %d",
1917 values[0], values[1],
1919 values[2], values[3], values[4]);
1922 arm11_run_instr_data_finish(arm11);
1928 int arm11_handle_mrc(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1930 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, true);
1933 int arm11_handle_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1935 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, false);
1938 int arm11_register_commands(struct command_context_s *cmd_ctx)
1942 command_t * top_cmd = NULL;
1944 RC_TOP( "arm11", "arm11 specific commands",
1946 RC_TOP( "memwrite", "Control memory write transfer mode",
1948 RC_FINAL_BOOL( "burst", "Enable/Disable non-standard but fast burst mode (default: enabled)",
1951 RC_FINAL_BOOL( "error_fatal",
1952 "Terminate program if transfer error was found (default: enabled)",
1953 memwrite_error_fatal)
1956 RC_FINAL( "vcr", "Control (Interrupt) Vector Catch Register",
1959 RC_FINAL( "mrc", "Read Coprocessor register",
1962 RC_FINAL( "mcr", "Write Coprocessor register",