1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
18 ***************************************************************************/
32 #define _DEBUG_INSTRUCTION_EXECUTION_
37 #define FNC_INFO DEBUG("-")
43 #define FNC_INFO_NOTIMPLEMENTED do { DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
45 #define FNC_INFO_NOTIMPLEMENTED
48 static void arm11_on_enter_debug_state(arm11_common_t * arm11);
51 bool arm11_config_memwrite_burst = true;
52 bool arm11_config_memwrite_error_fatal = true;
56 #define ARM11_HANDLER(x) \
59 target_type_t arm11_target =
64 ARM11_HANDLER(arch_state),
66 ARM11_HANDLER(target_request_data),
69 ARM11_HANDLER(resume),
72 ARM11_HANDLER(assert_reset),
73 ARM11_HANDLER(deassert_reset),
74 ARM11_HANDLER(soft_reset_halt),
75 ARM11_HANDLER(prepare_reset_halt),
77 ARM11_HANDLER(get_gdb_reg_list),
79 ARM11_HANDLER(read_memory),
80 ARM11_HANDLER(write_memory),
82 ARM11_HANDLER(bulk_write_memory),
84 ARM11_HANDLER(checksum_memory),
86 ARM11_HANDLER(add_breakpoint),
87 ARM11_HANDLER(remove_breakpoint),
88 ARM11_HANDLER(add_watchpoint),
89 ARM11_HANDLER(remove_watchpoint),
91 ARM11_HANDLER(run_algorithm),
93 ARM11_HANDLER(register_commands),
94 ARM11_HANDLER(target_command),
95 ARM11_HANDLER(init_target),
99 int arm11_regs_arch_type = -1;
117 ARM11_REGISTER_SPSR_FIQ,
118 ARM11_REGISTER_SPSR_SVC,
119 ARM11_REGISTER_SPSR_ABT,
120 ARM11_REGISTER_SPSR_IRQ,
121 ARM11_REGISTER_SPSR_UND,
122 ARM11_REGISTER_SPSR_MON,
131 typedef struct arm11_reg_defs_s
136 enum arm11_regtype type;
139 /* update arm11_regcache_ids when changing this */
140 static const arm11_reg_defs_t arm11_reg_defs[] =
142 {"r0", 0, 0, ARM11_REGISTER_CORE},
143 {"r1", 1, 1, ARM11_REGISTER_CORE},
144 {"r2", 2, 2, ARM11_REGISTER_CORE},
145 {"r3", 3, 3, ARM11_REGISTER_CORE},
146 {"r4", 4, 4, ARM11_REGISTER_CORE},
147 {"r5", 5, 5, ARM11_REGISTER_CORE},
148 {"r6", 6, 6, ARM11_REGISTER_CORE},
149 {"r7", 7, 7, ARM11_REGISTER_CORE},
150 {"r8", 8, 8, ARM11_REGISTER_CORE},
151 {"r9", 9, 9, ARM11_REGISTER_CORE},
152 {"r10", 10, 10, ARM11_REGISTER_CORE},
153 {"r11", 11, 11, ARM11_REGISTER_CORE},
154 {"r12", 12, 12, ARM11_REGISTER_CORE},
155 {"sp", 13, 13, ARM11_REGISTER_CORE},
156 {"lr", 14, 14, ARM11_REGISTER_CORE},
157 {"pc", 15, 15, ARM11_REGISTER_CORE},
159 #if ARM11_REGCACHE_FREGS
160 {"f0", 0, 16, ARM11_REGISTER_FX},
161 {"f1", 1, 17, ARM11_REGISTER_FX},
162 {"f2", 2, 18, ARM11_REGISTER_FX},
163 {"f3", 3, 19, ARM11_REGISTER_FX},
164 {"f4", 4, 20, ARM11_REGISTER_FX},
165 {"f5", 5, 21, ARM11_REGISTER_FX},
166 {"f6", 6, 22, ARM11_REGISTER_FX},
167 {"f7", 7, 23, ARM11_REGISTER_FX},
168 {"fps", 0, 24, ARM11_REGISTER_FPS},
171 {"cpsr", 0, 25, ARM11_REGISTER_CPSR},
173 #if ARM11_REGCACHE_MODEREGS
174 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ},
175 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ},
176 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ},
177 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ},
178 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ},
179 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ},
180 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ},
181 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ},
183 {"r13_svc", 13, -1, ARM11_REGISTER_SVC},
184 {"r14_svc", 14, -1, ARM11_REGISTER_SVC},
185 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC},
187 {"r13_abt", 13, -1, ARM11_REGISTER_ABT},
188 {"r14_abt", 14, -1, ARM11_REGISTER_ABT},
189 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT},
191 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ},
192 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ},
193 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ},
195 {"r13_und", 13, -1, ARM11_REGISTER_UND},
196 {"r14_und", 14, -1, ARM11_REGISTER_UND},
197 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND},
200 {"r13_mon", 13, -1, ARM11_REGISTER_MON},
201 {"r14_mon", 14, -1, ARM11_REGISTER_MON},
202 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON},
205 /* Debug Registers */
206 {"dscr", 0, -1, ARM11_REGISTER_DSCR},
207 {"wdtr", 0, -1, ARM11_REGISTER_WDTR},
208 {"rdtr", 0, -1, ARM11_REGISTER_RDTR},
211 enum arm11_regcache_ids
214 ARM11_RC_RX = ARM11_RC_R0,
229 ARM11_RC_SP = ARM11_RC_R13,
231 ARM11_RC_LR = ARM11_RC_R14,
233 ARM11_RC_PC = ARM11_RC_R15,
235 #if ARM11_REGCACHE_FREGS
237 ARM11_RC_FX = ARM11_RC_F0,
250 #if ARM11_REGCACHE_MODEREGS
288 #define ARM11_GDB_REGISTER_COUNT 26
290 u8 arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
292 reg_t arm11_gdb_dummy_fp_reg =
294 "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
297 u8 arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
299 reg_t arm11_gdb_dummy_fps_reg =
301 "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
306 /** Check and if necessary take control of the system
308 * \param arm11 Target state variable.
309 * \param dscr If the current DSCR content is
310 * available a pointer to a word holding the
311 * DSCR can be passed. Otherwise use NULL.
313 void arm11_check_init(arm11_common_t * arm11, u32 * dscr)
317 u32 dscr_local_tmp_copy;
321 dscr = &dscr_local_tmp_copy;
322 *dscr = arm11_read_DSCR(arm11);
325 if (!(*dscr & ARM11_DSCR_MODE_SELECT))
327 DEBUG("Bringing target into debug mode");
329 *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
330 arm11_write_DSCR(arm11, *dscr);
332 /* add further reset initialization here */
334 arm11->simulate_reset_on_next_halt = true;
336 if (*dscr & ARM11_DSCR_CORE_HALTED)
338 /** \todo TODO: this needs further scrutiny because
339 * arm11_on_enter_debug_state() never gets properly called
342 arm11->target->state = TARGET_HALTED;
343 arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
347 arm11->target->state = TARGET_RUNNING;
348 arm11->target->debug_reason = DBG_REASON_NOTHALTED;
351 arm11_sc7_clear_vbw(arm11);
358 (arm11->reg_values[ARM11_RC_##x])
360 /** Save processor state.
362 * This is called when the HALT instruction has succeeded
363 * or on other occasions that stop the processor.
366 static void arm11_on_enter_debug_state(arm11_common_t * arm11)
371 for(i = 0; i < asizeof(arm11->reg_values); i++)
373 arm11->reg_list[i].valid = 1;
374 arm11->reg_list[i].dirty = 0;
379 R(DSCR) = arm11_read_DSCR(arm11);
383 if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
385 arm11_add_debug_SCAN_N(arm11, 0x05, -1);
387 arm11_add_IR(arm11, ARM11_INTEST, -1);
389 scan_field_t chain5_fields[3];
391 arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
392 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
393 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
395 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
399 arm11->reg_list[ARM11_RC_WDTR].valid = 0;
403 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
404 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
405 ARM1136 seems to require this to issue ITR's as well */
407 u32 new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
409 /* this executes JTAG queue: */
411 arm11_write_DSCR(arm11, new_dscr);
415 Before executing any instruction in debug state you have to drain the write buffer.
416 This ensures that no imprecise Data Aborts can return at a later point:*/
418 /** \todo TODO: Test drain write buffer. */
423 /* MRC p14,0,R0,c5,c10,0 */
424 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
426 /* mcr 15, 0, r0, cr7, cr10, {4} */
427 arm11_run_instr_no_data1(arm11, 0xee070f9a);
429 u32 dscr = arm11_read_DSCR(arm11);
431 DEBUG("DRAIN, DSCR %08x", dscr);
433 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
435 arm11_run_instr_no_data1(arm11, 0xe320f000);
437 dscr = arm11_read_DSCR(arm11);
439 DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
447 arm11_run_instr_data_prepare(arm11);
452 /** \todo TODO: handle other mode registers */
455 for (i = 0; i < 15; i++)
457 /* MCR p14,0,R?,c0,c5,0 */
458 arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
464 /* check rDTRfull in DSCR */
466 if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
468 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
469 arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
473 arm11->reg_list[ARM11_RC_RDTR].valid = 0;
478 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
479 arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
483 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
484 arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
486 /* adjust PC depending on ARM state */
488 if (R(CPSR) & ARM11_CPSR_J) /* Java state */
490 arm11->reg_values[ARM11_RC_PC] -= 0;
492 else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */
494 arm11->reg_values[ARM11_RC_PC] -= 4;
498 arm11->reg_values[ARM11_RC_PC] -= 8;
501 if (arm11->simulate_reset_on_next_halt)
503 arm11->simulate_reset_on_next_halt = false;
505 DEBUG("Reset c1 Control Register");
507 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
509 /* MCR p15,0,R0,c1,c0,0 */
510 arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
516 arm11_run_instr_data_finish(arm11);
518 arm11_dump_reg_changes(arm11);
521 void arm11_dump_reg_changes(arm11_common_t * arm11)
524 for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
526 if (!arm11->reg_list[i].valid)
528 if (arm11->reg_history[i].valid)
529 INFO("%8s INVALID (%08x)", arm11_reg_defs[i].name, arm11->reg_history[i].value);
533 if (arm11->reg_history[i].valid)
535 if (arm11->reg_history[i].value != arm11->reg_values[i])
536 INFO("%8s %08x (%08x)", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
540 INFO("%8s %08x (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
547 /** Restore processor state
549 * This is called in preparation for the RESTART function.
552 void arm11_leave_debug_state(arm11_common_t * arm11)
556 arm11_run_instr_data_prepare(arm11);
558 /** \todo TODO: handle other mode registers */
560 /* restore R1 - R14 */
562 for (i = 1; i < 15; i++)
564 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
567 /* MRC p14,0,r?,c0,c5,0 */
568 arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
570 // DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
573 arm11_run_instr_data_finish(arm11);
576 /* spec says clear wDTR and rDTR; we assume they are clear as
577 otherwise our programming would be sloppy */
580 u32 DSCR = arm11_read_DSCR(arm11);
582 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
584 ERROR("wDTR/rDTR inconsistent (DSCR %08x)", DSCR);
588 arm11_run_instr_data_prepare(arm11);
590 /* restore original wDTR */
592 if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
594 /* MCR p14,0,R0,c0,c5,0 */
595 arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
601 arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
607 arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
612 /* MRC p14,0,r0,c0,c5,0 */
613 arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
615 arm11_run_instr_data_finish(arm11);
620 arm11_write_DSCR(arm11, R(DSCR));
625 if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
627 arm11_add_debug_SCAN_N(arm11, 0x05, -1);
629 arm11_add_IR(arm11, ARM11_EXTEST, -1);
631 scan_field_t chain5_fields[3];
633 u8 Ready = 0; /* ignored */
634 u8 Valid = 0; /* ignored */
636 arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
637 arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
638 arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
640 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
643 arm11_record_register_history(arm11);
646 void arm11_record_register_history(arm11_common_t * arm11)
649 for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
651 arm11->reg_history[i].value = arm11->reg_values[i];
652 arm11->reg_history[i].valid = arm11->reg_list[i].valid;
654 arm11->reg_list[i].valid = 0;
655 arm11->reg_list[i].dirty = 0;
660 /* poll current target status */
661 int arm11_poll(struct target_s *target)
665 arm11_common_t * arm11 = target->arch_info;
667 if (arm11->trst_active)
670 u32 dscr = arm11_read_DSCR(arm11);
672 DEBUG("DSCR %08x", dscr);
674 arm11_check_init(arm11, &dscr);
676 if (dscr & ARM11_DSCR_CORE_HALTED)
678 if (target->state != TARGET_HALTED)
680 enum target_state old_state = target->state;
682 DEBUG("enter TARGET_HALTED");
683 target->state = TARGET_HALTED;
684 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
685 arm11_on_enter_debug_state(arm11);
687 target_call_event_callbacks(target,
688 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
693 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
695 DEBUG("enter TARGET_RUNNING");
696 target->state = TARGET_RUNNING;
697 target->debug_reason = DBG_REASON_NOTHALTED;
703 /* architecture specific status reply */
704 int arm11_arch_state(struct target_s *target)
706 FNC_INFO_NOTIMPLEMENTED;
712 /* target request support */
713 int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer)
715 FNC_INFO_NOTIMPLEMENTED;
722 /* target execution control */
723 int arm11_halt(struct target_s *target)
727 arm11_common_t * arm11 = target->arch_info;
729 DEBUG("target->state: %s", target_state_strings[target->state]);
731 if (target->state == TARGET_UNKNOWN)
733 arm11->simulate_reset_on_next_halt = true;
736 if (target->state == TARGET_HALTED)
738 WARNING("target was already halted");
739 return ERROR_TARGET_ALREADY_HALTED;
742 if (arm11->trst_active)
744 arm11->halt_requested = true;
748 arm11_add_IR(arm11, ARM11_HALT, TAP_RTI);
750 jtag_execute_queue();
756 dscr = arm11_read_DSCR(arm11);
758 if (dscr & ARM11_DSCR_CORE_HALTED)
762 arm11_on_enter_debug_state(arm11);
764 enum target_state old_state = target->state;
766 target->state = TARGET_HALTED;
767 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
769 target_call_event_callbacks(target,
770 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
776 int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
780 // DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
781 // current, address, handle_breakpoints, debug_execution);
783 arm11_common_t * arm11 = target->arch_info;
785 DEBUG("target->state: %s", target_state_strings[target->state]);
787 if (target->state != TARGET_HALTED)
789 WARNING("target was not halted");
790 return ERROR_TARGET_NOT_HALTED;
796 INFO("RESUME PC %08x%s", R(PC), !current ? "!" : "");
798 /* clear breakpoints/watchpoints and VCR*/
799 arm11_sc7_clear_vbw(arm11);
801 /* Set up breakpoints */
802 if (!debug_execution)
804 /* check if one matches PC and step over it if necessary */
808 for (bp = target->breakpoints; bp; bp = bp->next)
810 if (bp->address == R(PC))
812 DEBUG("must step over %08x", bp->address);
813 arm11_step(target, 1, 0, 0);
818 /* set all breakpoints */
822 for (bp = target->breakpoints; bp; bp = bp->next)
824 arm11_sc7_action_t brp[2];
827 brp[0].address = ARM11_SC7_BVR0 + brp_num;
828 brp[0].value = bp->address;
830 brp[1].address = ARM11_SC7_BCR0 + brp_num;
831 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
833 arm11_sc7_run(arm11, brp, asizeof(brp));
835 DEBUG("Add BP " ZU " at %08x", brp_num, bp->address);
840 arm11_sc7_set_vcr(arm11, arm11_vcr);
844 arm11_leave_debug_state(arm11);
846 arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
848 jtag_execute_queue();
852 u32 dscr = arm11_read_DSCR(arm11);
854 DEBUG("DSCR %08x", dscr);
856 if (dscr & ARM11_DSCR_CORE_RESTARTED)
860 if (!debug_execution)
862 target->state = TARGET_RUNNING;
863 target->debug_reason = DBG_REASON_NOTHALTED;
864 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
868 target->state = TARGET_DEBUG_RUNNING;
869 target->debug_reason = DBG_REASON_NOTHALTED;
870 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
876 int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
880 DEBUG("target->state: %s", target_state_strings[target->state]);
882 if (target->state != TARGET_HALTED)
884 WARNING("target was not halted");
885 return ERROR_TARGET_NOT_HALTED;
888 arm11_common_t * arm11 = target->arch_info;
893 INFO("STEP PC %08x%s", R(PC), !current ? "!" : "");
895 /** \todo TODO: Thumb not supported here */
897 u32 next_instruction;
899 arm11_read_memory_word(arm11, R(PC), &next_instruction);
902 if ((next_instruction & 0xFFF00070) == 0xe1200070)
905 arm11->reg_list[ARM11_RC_PC].valid = 1;
906 arm11->reg_list[ARM11_RC_PC].dirty = 0;
907 INFO("Skipping BKPT");
909 /* skip over Wait for interrupt / Standby */
910 /* mcr 15, 0, r?, cr7, cr0, {4} */
911 else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
914 arm11->reg_list[ARM11_RC_PC].valid = 1;
915 arm11->reg_list[ARM11_RC_PC].dirty = 0;
916 INFO("Skipping WFI");
918 /* ignore B to self */
919 else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
921 INFO("Not stepping jump to self");
925 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
928 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
929 * the VCR might be something worth looking into. */
932 /* Set up breakpoint for stepping */
934 arm11_sc7_action_t brp[2];
937 brp[0].address = ARM11_SC7_BVR0;
938 brp[0].value = R(PC);
940 brp[1].address = ARM11_SC7_BCR0;
941 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
943 arm11_sc7_run(arm11, brp, asizeof(brp));
947 arm11_leave_debug_state(arm11);
949 arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
951 jtag_execute_queue();
953 /** \todo TODO: add a timeout */
959 u32 dscr = arm11_read_DSCR(arm11);
961 DEBUG("DSCR %08x", dscr);
963 if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
964 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
968 /* clear breakpoint */
969 arm11_sc7_clear_vbw(arm11);
972 arm11_on_enter_debug_state(arm11);
975 // target->state = TARGET_HALTED;
976 target->debug_reason = DBG_REASON_SINGLESTEP;
978 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
984 /* target reset control */
985 int arm11_assert_reset(struct target_s *target)
990 /* assert reset lines */
991 /* resets only the DBGTAP, not the ARM */
993 jtag_add_reset(1, 0);
994 jtag_add_sleep(5000);
996 arm11_common_t * arm11 = target->arch_info;
997 arm11->trst_active = true;
1003 int arm11_deassert_reset(struct target_s *target)
1008 DEBUG("target->state: %s", target_state_strings[target->state]);
1010 /* deassert reset lines */
1011 jtag_add_reset(0, 0);
1013 arm11_common_t * arm11 = target->arch_info;
1014 arm11->trst_active = false;
1016 if (arm11->halt_requested)
1017 return arm11_halt(target);
1023 int arm11_soft_reset_halt(struct target_s *target)
1025 FNC_INFO_NOTIMPLEMENTED;
1030 int arm11_prepare_reset_halt(struct target_s *target)
1032 FNC_INFO_NOTIMPLEMENTED;
1038 /* target register access for gdb */
1039 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size)
1043 arm11_common_t * arm11 = target->arch_info;
1045 if (target->state != TARGET_HALTED)
1047 return ERROR_TARGET_NOT_HALTED;
1050 *reg_list_size = ARM11_GDB_REGISTER_COUNT;
1051 *reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
1054 for (i = 16; i < 24; i++)
1056 (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
1059 (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
1063 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1065 if (arm11_reg_defs[i].gdb_num == -1)
1068 (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
1075 /* target memory access
1076 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1077 * count: number of items of <size>
1079 int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1081 /** \todo TODO: check if buffer cast to u32* and u16* might cause alignment problems */
1085 DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
1087 arm11_common_t * arm11 = target->arch_info;
1089 arm11_run_instr_data_prepare(arm11);
1091 /* MRC p14,0,r0,c0,c5,0 */
1092 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1097 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1098 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1101 for (i = 0; i < count; i++)
1103 /* ldrb r1, [r0], #1 */
1104 arm11_run_instr_no_data1(arm11, 0xe4d01001);
1107 /* MCR p14,0,R1,c0,c5,0 */
1108 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1117 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1119 u16 * buf16 = (u16*)buffer;
1122 for (i = 0; i < count; i++)
1124 /* ldrh r1, [r0], #2 */
1125 arm11_run_instr_no_data1(arm11, 0xe0d010b2);
1129 /* MCR p14,0,R1,c0,c5,0 */
1130 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1140 /* LDC p14,c5,[R0],#4 */
1141 arm11_run_instr_data_from_core(arm11, 0xecb05e01, (u32 *)buffer, count);
1145 arm11_run_instr_data_finish(arm11);
1150 int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1154 DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
1156 arm11_common_t * arm11 = target->arch_info;
1158 arm11_run_instr_data_prepare(arm11);
1160 /* MRC p14,0,r0,c0,c5,0 */
1161 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1167 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1170 for (i = 0; i < count; i++)
1172 /* MRC p14,0,r1,c0,c5,0 */
1173 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1175 /* strb r1, [r0], #1 */
1176 arm11_run_instr_no_data1(arm11, 0xe4c01001);
1184 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1186 u16 * buf16 = (u16*)buffer;
1189 for (i = 0; i < count; i++)
1191 /* MRC p14,0,r1,c0,c5,0 */
1192 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buf16++);
1194 /* strh r1, [r0], #2 */
1195 arm11_run_instr_no_data1(arm11, 0xe0c010b2);
1202 /** \todo TODO: check if buffer cast to u32* might cause alignment problems */
1204 if (!arm11_config_memwrite_burst)
1206 /* STC p14,c5,[R0],#4 */
1207 arm11_run_instr_data_to_core(arm11, 0xeca05e01, (u32 *)buffer, count);
1211 /* STC p14,c5,[R0],#4 */
1212 arm11_run_instr_data_to_core_noack(arm11, 0xeca05e01, (u32 *)buffer, count);
1219 /* r0 verification */
1223 /* MCR p14,0,R0,c0,c5,0 */
1224 arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1226 if (address + size * count != r0)
1228 ERROR("Data transfer failed. (%d)", (r0 - address) - size * count);
1230 if (arm11_config_memwrite_burst)
1231 ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1233 if (arm11_config_memwrite_error_fatal)
1240 arm11_run_instr_data_finish(arm11);
1249 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1250 int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer)
1254 return arm11_write_memory(target, address, 4, count, buffer);
1258 int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
1260 FNC_INFO_NOTIMPLEMENTED;
1266 /* target break-/watchpoint control
1267 * rw: 0 = write, 1 = read, 2 = access
1269 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1273 arm11_common_t * arm11 = target->arch_info;
1276 if (breakpoint->type == BKPT_SOFT)
1278 INFO("sw breakpoint requested, but software breakpoints not enabled");
1279 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1283 if (!arm11->free_brps)
1285 INFO("no breakpoint unit available for hardware breakpoint");
1286 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1289 if (breakpoint->length != 4)
1291 INFO("only breakpoints of four bytes length supported");
1292 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1300 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1304 arm11_common_t * arm11 = target->arch_info;
1311 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1313 FNC_INFO_NOTIMPLEMENTED;
1318 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1320 FNC_INFO_NOTIMPLEMENTED;
1326 /* target algorithm support */
1327 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_param, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
1329 FNC_INFO_NOTIMPLEMENTED;
1334 int arm11_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
1340 ERROR("'target arm11' 4th argument <jtag chain pos>");
1344 int chain_pos = strtoul(args[3], NULL, 0);
1346 NEW(arm11_common_t, arm11, 1);
1348 arm11->target = target;
1350 /* prepare JTAG information for the new target */
1351 arm11->jtag_info.chain_pos = chain_pos;
1352 arm11->jtag_info.scann_size = 5;
1354 arm_jtag_setup_connection(&arm11->jtag_info);
1356 jtag_device_t *device = jtag_get_device(chain_pos);
1358 if (device->ir_length != 5)
1360 ERROR("'target arm11' expects 'jtag_device 5 0x01 0x1F 0x1E'");
1364 target->arch_info = arm11;
1369 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
1373 arm11_common_t * arm11 = target->arch_info;
1377 arm11_add_IR(arm11, ARM11_IDCODE, -1);
1379 scan_field_t idcode_field;
1381 arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
1383 arm11_add_dr_scan_vc(1, &idcode_field, TAP_PD);
1387 arm11_add_debug_SCAN_N(arm11, 0x00, -1);
1389 arm11_add_IR(arm11, ARM11_INTEST, -1);
1391 scan_field_t chain0_fields[2];
1393 arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
1394 arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
1396 arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_RTI);
1398 jtag_execute_queue();
1401 switch (arm11->device_id & 0x0FFFF000)
1403 case 0x07B36000: INFO("found ARM1136"); break;
1404 case 0x07B56000: INFO("found ARM1156"); break;
1405 case 0x07B76000: INFO("found ARM1176"); break;
1408 ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1413 arm11->debug_version = (arm11->didr >> 16) & 0x0F;
1415 if (arm11->debug_version != ARM11_DEBUG_V6 &&
1416 arm11->debug_version != ARM11_DEBUG_V61)
1418 ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1423 arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1;
1424 arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1;
1426 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1427 arm11->free_brps = arm11->brp;
1428 arm11->free_wrps = arm11->wrp;
1430 DEBUG("IDCODE %08x IMPLEMENTOR %02x DIDR %08x",
1435 arm11_build_reg_cache(target);
1438 /* as a side-effect this reads DSCR and thus
1439 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1440 * as suggested by the spec.
1443 arm11_check_init(arm11, NULL);
1448 int arm11_quit(void)
1450 FNC_INFO_NOTIMPLEMENTED;
1455 /** Load a register that is marked !valid in the register cache */
1456 int arm11_get_reg(reg_t *reg)
1460 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1462 if (target->state != TARGET_HALTED)
1464 return ERROR_TARGET_NOT_HALTED;
1467 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1470 arm11_common_t *arm11 = target->arch_info;
1471 const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1477 /** Change a value in the register cache */
1478 int arm11_set_reg(reg_t *reg, u8 *buf)
1482 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1483 arm11_common_t *arm11 = target->arch_info;
1484 // const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1486 arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1494 void arm11_build_reg_cache(target_t *target)
1496 arm11_common_t *arm11 = target->arch_info;
1498 NEW(reg_cache_t, cache, 1);
1499 NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT);
1500 NEW(arm11_reg_state_t, arm11_reg_states, ARM11_REGCACHE_COUNT);
1502 if (arm11_regs_arch_type == -1)
1503 arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
1505 arm11->reg_list = reg_list;
1507 /* Build the process context cache */
1508 cache->name = "arm11 registers";
1510 cache->reg_list = reg_list;
1511 cache->num_regs = ARM11_REGCACHE_COUNT;
1513 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
1516 // armv7m->core_cache = cache;
1517 // armv7m->process_context = cache;
1521 /* Not very elegant assertion */
1522 if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
1523 ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
1524 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1526 ERROR("arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
1530 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1532 reg_t * r = reg_list + i;
1533 const arm11_reg_defs_t * rd = arm11_reg_defs + i;
1534 arm11_reg_state_t * rs = arm11_reg_states + i;
1538 r->value = (u8 *)(arm11->reg_values + i);
1541 r->bitfield_desc = NULL;
1542 r->num_bitfields = 0;
1543 r->arch_type = arm11_regs_arch_type;
1547 rs->target = target;
1553 int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name)
1557 INFO("%s is %s.", name, *var ? "enabled" : "disabled");
1562 return ERROR_COMMAND_SYNTAX_ERROR;
1567 case 'f': /* false */
1569 case 'd': /* disable */
1575 case 't': /* true */
1577 case 'e': /* enable */
1583 INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
1589 #define BOOL_WRAPPER(name, print_name) \
1590 int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
1592 return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
1595 #define RC_TOP(name, descr, more) \
1597 command_t * new_cmd = register_command(cmd_ctx, top_cmd, name, NULL, COMMAND_ANY, descr); \
1598 command_t * top_cmd = new_cmd; \
1602 #define RC_FINAL(name, descr, handler) \
1603 register_command(cmd_ctx, top_cmd, name, handler, COMMAND_ANY, descr);
1605 #define RC_FINAL_BOOL(name, descr, var) \
1606 register_command(cmd_ctx, top_cmd, name, arm11_handle_bool_##var, COMMAND_ANY, descr);
1609 BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
1610 BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
1613 int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1617 arm11_vcr = strtoul(args[0], NULL, 0);
1621 return ERROR_COMMAND_SYNTAX_ERROR;
1624 INFO("VCR 0x%08X", arm11_vcr);
1629 int arm11_register_commands(struct command_context_s *cmd_ctx)
1633 command_t * top_cmd = NULL;
1635 RC_TOP( "arm11", "arm11 specific commands",
1637 RC_TOP( "memwrite", "Control memory write transfer mode",
1639 RC_FINAL_BOOL( "burst", "Enable/Disable non-standard but fast burst mode (default: enabled)",
1642 RC_FINAL_BOOL( "error_fatal",
1643 "Terminate program if transfer error was found (default: enabled)",
1644 memwrite_error_fatal)
1647 RC_FINAL( "vcr", "Control (Interrupt) Vector Catch Register",