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   1 /***************************************************************************
   2  *   Copyright (C) 2008 digenius technology GmbH.                          *
   3  *   Michael Bruck                                                         *
   4  *                                                                         *
   5  *   Copyright (C) 2008 Georg Acher <acher@in.tum.de>                      *
   6  *                                                                         *
   7  *   This program is free software; you can redistribute it and/or modify  *
   8  *   it under the terms of the GNU General Public License as published by  *
   9  *   the Free Software Foundation; either version 2 of the License, or     *
  10  *   (at your option) any later version.                                   *
  11  *                                                                         *
  12  *   This program is distributed in the hope that it will be useful,       *
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  14  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  15  *   GNU General Public License for more details.                          *
  16  *                                                                         *
  17  *   You should have received a copy of the GNU General Public License     *
  18  *   along with this program; if not, write to the                         *
  19  *   Free Software Foundation, Inc.,                                       *
  20  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  21  ***************************************************************************/
  22
  23 #ifndef ARM11_H
  24 #define ARM11_H
  25
  26 #include "armv4_5.h"
  27
  28 #define NEW(type, variable, items)                      \
  29         type * variable = calloc(1, sizeof(type) * items)
  30
  31 /* TEMPORARY -- till we switch to the shared infrastructure */
  32 #define ARM11_REGCACHE_COUNT            20
  33
  34 #define ARM11_TAP_DEFAULT                       TAP_INVALID
  35
  36
  37 #define CHECK_RETVAL(action)                                                            \
  38 do {                                                                                                            \
  39         int __retval = (action);                                                                \
  40                                                                                                                         \
  41         if (__retval != ERROR_OK)                                                               \
  42         {                                                                                                               \
  43                 LOG_DEBUG("error while calling \"" # action "\"");      \
  44                 return __retval;                                                                        \
  45         }                                                                                                               \
  46                                                                                                                         \
  47 } while (0)
  48
  49
  50 struct arm11_register_history
  51 {
  52         uint32_t                value;
  53         uint8_t         valid;
  54 };
  55
  56 enum arm11_debug_version
  57 {
  58         ARM11_DEBUG_V6                  = 0x01,
  59         ARM11_DEBUG_V61                 = 0x02,
  60         ARM11_DEBUG_V7                  = 0x03,
  61         ARM11_DEBUG_V7_CP14             = 0x04,
  62 };
  63
  64 struct arm11_common
  65 {
  66         struct arm      arm;
  67         struct target * target;         /**< Reference back to the owner */
  68
  69         /** \name Processor type detection */
  70         /*@{*/
  71
  72         uint32_t                device_id;              /**< IDCODE readout                             */
  73         uint32_t                didr;                   /**< DIDR readout (debug capabilities)  */
  74         uint8_t         implementor;    /**< DIDR Implementor readout           */
  75
  76         size_t  brp;                    /**< Number of Breakpoint Register Pairs from DIDR      */
  77         size_t  wrp;                    /**< Number of Watchpoint Register Pairs from DIDR      */
  78
  79         enum arm11_debug_version
  80                 debug_version;          /**< ARM debug architecture from DIDR   */
  81         /*@}*/
  82
  83         uint32_t                last_dscr;              /**< Last retrieved DSCR value;
  84                                                              Use only for debug message generation              */
  85
  86         bool    simulate_reset_on_next_halt;    /**< Perform cleanups of the ARM state on next halt */
  87
  88         /** \name Shadow registers to save processor state */
  89         /*@{*/
  90
  91         struct reg *    reg_list;                                                       /**< target register list */
  92         uint32_t                reg_values[ARM11_REGCACHE_COUNT];       /**< data for registers */
  93
  94         /*@}*/
  95
  96         struct arm11_register_history
  97                 reg_history[ARM11_REGCACHE_COUNT];      /**< register state before last resume */
  98
  99         size_t  free_brps;                              /**< keep track of breakpoints allocated by arm11_add_breakpoint() */
 100         size_t  free_wrps;                              /**< keep track of breakpoints allocated by arm11_add_watchpoint() */
 101
 102         // GA
 103         struct reg_cache *core_cache;
 104
 105         struct arm_jtag jtag_info;
 106 };
 107
 108 static inline struct arm11_common *target_to_arm11(struct target *target)
 109 {
 110         return container_of(target->arch_info, struct arm11_common,
 111                         arm);
 112 }
 113
 114 /**
 115  * ARM11 DBGTAP instructions
 116  *
 117  * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/I1006229.html
 118  */
 119 enum arm11_instructions
 120 {
 121         ARM11_EXTEST    = 0x00,
 122         ARM11_SCAN_N    = 0x02,
 123         ARM11_RESTART   = 0x04,
 124         ARM11_HALT          = 0x08,
 125         ARM11_INTEST    = 0x0C,
 126         ARM11_ITRSEL    = 0x1D,
 127         ARM11_IDCODE    = 0x1E,
 128         ARM11_BYPASS    = 0x1F,
 129 };
 130
 131 enum arm11_dscr
 132 {
 133         ARM11_DSCR_CORE_HALTED                                                                  = 1 << 0,
 134         ARM11_DSCR_CORE_RESTARTED                                                               = 1 << 1,
 135
 136         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK                                   = 0x0F << 2,
 137         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT                                   = 0x00 << 2,
 138         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT                             = 0x01 << 2,
 139         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT                             = 0x02 << 2,
 140         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION               = 0x03 << 2,
 141         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ                                 = 0x04 << 2,
 142         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH                   = 0x05 << 2,
 143
 144         ARM11_DSCR_STICKY_PRECISE_DATA_ABORT                                    = 1 << 6,
 145         ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT                                  = 1 << 7,
 146         ARM11_DSCR_INTERRUPTS_DISABLE                                                   = 1 << 11,
 147         ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE                               = 1 << 13,
 148         ARM11_DSCR_MODE_SELECT                                                                  = 1 << 14,
 149         ARM11_DSCR_WDTR_FULL                                                                    = 1 << 29,
 150         ARM11_DSCR_RDTR_FULL                                                                    = 1 << 30,
 151 };
 152
 153 enum arm11_cpsr
 154 {
 155         ARM11_CPSR_T                            = 1 << 5,
 156         ARM11_CPSR_J                            = 1 << 24,
 157 };
 158
 159 enum arm11_sc7
 160 {
 161         ARM11_SC7_NULL                          = 0,
 162         ARM11_SC7_VCR                           = 7,
 163         ARM11_SC7_PC                            = 8,
 164         ARM11_SC7_BVR0                          = 64,
 165         ARM11_SC7_BCR0                          = 80,
 166         ARM11_SC7_WVR0                          = 96,
 167         ARM11_SC7_WCR0                          = 112,
 168 };
 169
 170 struct arm11_reg_state
 171 {
 172         uint32_t                                def_index;
 173         struct target *                 target;
 174 };
 175
 176 #endif /* ARM11_H */