1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
5 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
28 #define NEW(type, variable, items) \
29 type * variable = calloc(1, sizeof(type) * items)
31 /* For MinGW use 'I' prefix to print size_t (instead of 'z') */
32 /* Except if __USE_MINGW_ANSI_STDIO is defined with MinGW */
34 #if (!defined(__MSVCRT__) || defined(__USE_MINGW_ANSI_STDIO))
41 /* TEMPORARY -- till we switch to the shared infrastructure */
42 #define ARM11_REGCACHE_COUNT 20
44 #define ARM11_TAP_DEFAULT TAP_INVALID
47 #define CHECK_RETVAL(action) \
49 int __retval = (action); \
51 if (__retval != ERROR_OK) \
53 LOG_DEBUG("error while calling \"" # action "\""); \
60 struct arm11_register_history
66 enum arm11_debug_version
68 ARM11_DEBUG_V6 = 0x01,
69 ARM11_DEBUG_V61 = 0x02,
70 ARM11_DEBUG_V7 = 0x03,
71 ARM11_DEBUG_V7_CP14 = 0x04,
77 struct target * target; /**< Reference back to the owner */
79 /** \name Processor type detection */
82 uint32_t device_id; /**< IDCODE readout */
83 uint32_t didr; /**< DIDR readout (debug capabilities) */
84 uint8_t implementor; /**< DIDR Implementor readout */
86 size_t brp; /**< Number of Breakpoint Register Pairs from DIDR */
87 size_t wrp; /**< Number of Watchpoint Register Pairs from DIDR */
89 enum arm11_debug_version
90 debug_version; /**< ARM debug architecture from DIDR */
93 uint32_t last_dscr; /**< Last retrieved DSCR value;
94 Use only for debug message generation */
96 bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt */
98 /** \name Shadow registers to save processor state */
101 struct reg * reg_list; /**< target register list */
102 uint32_t reg_values[ARM11_REGCACHE_COUNT]; /**< data for registers */
106 struct arm11_register_history
107 reg_history[ARM11_REGCACHE_COUNT]; /**< register state before last resume */
109 size_t free_brps; /**< keep track of breakpoints allocated by arm11_add_breakpoint() */
110 size_t free_wrps; /**< keep track of breakpoints allocated by arm11_add_watchpoint() */
113 struct reg_cache *core_cache;
115 struct arm_jtag jtag_info;
118 static inline struct arm11_common *target_to_arm11(struct target *target)
120 return container_of(target->arch_info, struct arm11_common,
125 * ARM11 DBGTAP instructions
127 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/I1006229.html
129 enum arm11_instructions
133 ARM11_RESTART = 0x04,
143 ARM11_DSCR_CORE_HALTED = 1 << 0,
144 ARM11_DSCR_CORE_RESTARTED = 1 << 1,
146 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK = 0x0F << 2,
147 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT = 0x00 << 2,
148 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT = 0x01 << 2,
149 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT = 0x02 << 2,
150 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION = 0x03 << 2,
151 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ = 0x04 << 2,
152 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH = 0x05 << 2,
154 ARM11_DSCR_STICKY_PRECISE_DATA_ABORT = 1 << 6,
155 ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT = 1 << 7,
156 ARM11_DSCR_INTERRUPTS_DISABLE = 1 << 11,
157 ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE = 1 << 13,
158 ARM11_DSCR_MODE_SELECT = 1 << 14,
159 ARM11_DSCR_WDTR_FULL = 1 << 29,
160 ARM11_DSCR_RDTR_FULL = 1 << 30,
165 ARM11_CPSR_T = 1 << 5,
166 ARM11_CPSR_J = 1 << 24,
177 ARM11_SC7_WCR0 = 112,
180 struct arm11_reg_state
183 struct target * target;