git.sur5r.net Git - openocd/blob - src/target/arm11.h

   1 /***************************************************************************
   2  *   Copyright (C) 2008 digenius technology GmbH.                          *
   3  *   Michael Bruck                                                         *
   4  *                                                                         *
   5  *   Copyright (C) 2008 Georg Acher <acher@in.tum.de>                      *
   6  *                                                                         *
   7  *   This program is free software; you can redistribute it and/or modify  *
   8  *   it under the terms of the GNU General Public License as published by  *
   9  *   the Free Software Foundation; either version 2 of the License, or     *
  10  *   (at your option) any later version.                                   *
  11  *                                                                         *
  12  *   This program is distributed in the hope that it will be useful,       *
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  14  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  15  *   GNU General Public License for more details.                          *
  16  *                                                                         *
  17  *   You should have received a copy of the GNU General Public License     *
  18  *   along with this program; if not, write to the                         *
  19  *   Free Software Foundation, Inc.,                                       *
  20  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  21  ***************************************************************************/
  22
  23 #ifndef ARM11_H
  24 #define ARM11_H
  25
  26 #include "armv4_5.h"
  27 #include "arm_dpm.h"
  28
  29 #define ARM11_REGCACHE_COUNT            3
  30
  31 #define ARM11_TAP_DEFAULT                       TAP_INVALID
  32
  33 #define CHECK_RETVAL(action)                    \
  34         do {                                    \
  35                 int __retval = (action);        \
  36                 if (__retval != ERROR_OK) {     \
  37                         LOG_DEBUG("error while calling \"%s\"", \
  38                                 # action );     \
  39                         return __retval;        \
  40                 }                               \
  41         } while (0)
  42
  43 enum arm11_debug_version
  44 {
  45         ARM11_DEBUG_V6                  = 0x01,
  46         ARM11_DEBUG_V61                 = 0x02,
  47         ARM11_DEBUG_V7                  = 0x03,
  48         ARM11_DEBUG_V7_CP14             = 0x04,
  49 };
  50
  51 struct arm11_common
  52 {
  53         struct arm      arm;
  54         struct target * target;         /**< Reference back to the owner */
  55
  56         /** Debug module state. */
  57         struct arm_dpm dpm;
  58
  59         /** \name Processor type detection */
  60         /*@{*/
  61
  62         size_t  brp;                    /**< Number of Breakpoint Register Pairs from DIDR      */
  63         size_t  wrp;                    /**< Number of Watchpoint Register Pairs from DIDR      */
  64
  65         /*@}*/
  66
  67         uint32_t                last_dscr;              /**< Last retrieved DSCR value;
  68                                                              Use only for debug message generation              */
  69
  70         bool    simulate_reset_on_next_halt;    /**< Perform cleanups of the ARM state on next halt */
  71
  72         /** \name Shadow registers to save debug state */
  73         /*@{*/
  74
  75         struct reg *    reg_list;                                                       /**< target register list */
  76         uint32_t                reg_values[ARM11_REGCACHE_COUNT];       /**< data for registers */
  77
  78         /*@}*/
  79
  80         size_t  free_brps;                              /**< keep track of breakpoints allocated by arm11_add_breakpoint() */
  81         size_t  free_wrps;                              /**< keep track of breakpoints allocated by arm11_add_watchpoint() */
  82
  83         // GA
  84         struct reg_cache *core_cache;
  85
  86         struct arm_jtag jtag_info;
  87 };
  88
  89 static inline struct arm11_common *target_to_arm11(struct target *target)
  90 {
  91         return container_of(target->arch_info, struct arm11_common,
  92                         arm);
  93 }
  94
  95 /**
  96  * ARM11 DBGTAP instructions
  97  *
  98  * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/I1006229.html
  99  */
 100 enum arm11_instructions
 101 {
 102         ARM11_EXTEST    = 0x00,
 103         ARM11_SCAN_N    = 0x02,
 104         ARM11_RESTART   = 0x04,
 105         ARM11_HALT          = 0x08,
 106         ARM11_INTEST    = 0x0C,
 107         ARM11_ITRSEL    = 0x1D,
 108         ARM11_IDCODE    = 0x1E,
 109         ARM11_BYPASS    = 0x1F,
 110 };
 111
 112 enum arm11_dscr
 113 {
 114         ARM11_DSCR_CORE_HALTED                                                                  = 1 << 0,
 115         ARM11_DSCR_CORE_RESTARTED                                                               = 1 << 1,
 116
 117         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK                                   = 0x0F << 2,
 118         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT                                   = 0x00 << 2,
 119         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT                             = 0x01 << 2,
 120         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT                             = 0x02 << 2,
 121         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION               = 0x03 << 2,
 122         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ                                 = 0x04 << 2,
 123         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH                   = 0x05 << 2,
 124
 125         ARM11_DSCR_STICKY_PRECISE_DATA_ABORT                                    = 1 << 6,
 126         ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT                                  = 1 << 7,
 127         ARM11_DSCR_INTERRUPTS_DISABLE                                                   = 1 << 11,
 128         ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE                               = 1 << 13,
 129         ARM11_DSCR_MODE_SELECT                                                                  = 1 << 14,
 130         ARM11_DSCR_WDTR_FULL                                                                    = 1 << 29,
 131         ARM11_DSCR_RDTR_FULL                                                                    = 1 << 30,
 132 };
 133
 134 enum arm11_cpsr
 135 {
 136         ARM11_CPSR_T                            = 1 << 5,
 137         ARM11_CPSR_J                            = 1 << 24,
 138 };
 139
 140 enum arm11_sc7
 141 {
 142         ARM11_SC7_NULL                          = 0,
 143         ARM11_SC7_VCR                           = 7,
 144         ARM11_SC7_PC                            = 8,
 145         ARM11_SC7_BVR0                          = 64,
 146         ARM11_SC7_BCR0                          = 80,
 147         ARM11_SC7_WVR0                          = 96,
 148         ARM11_SC7_WCR0                          = 112,
 149 };
 150
 151 struct arm11_reg_state
 152 {
 153         uint32_t                                def_index;
 154         struct target *                 target;
 155 };
 156
 157 #endif /* ARM11_H */