1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
4 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
20 ***************************************************************************/
27 #include "embeddedice.h"
32 #define asizeof(x) (sizeof(x) / sizeof((x)[0]))
34 #define NEW(type, variable, items) \
35 type * variable = calloc(1, sizeof(type) * items)
38 /* For MinGW use 'I' prefix to print size_t (instead of 'z') */
47 #define ARM11_REGCACHE_MODEREGS 0
48 #define ARM11_REGCACHE_FREGS 0
50 #define ARM11_REGCACHE_COUNT (20 + \
51 23 * ARM11_REGCACHE_MODEREGS + \
52 9 * ARM11_REGCACHE_FREGS)
55 typedef struct arm11_register_history_s
59 }arm11_register_history_t;
61 enum arm11_debug_version
63 ARM11_DEBUG_V6 = 0x01,
64 ARM11_DEBUG_V61 = 0x02,
65 ARM11_DEBUG_V7 = 0x03,
66 ARM11_DEBUG_V7_CP14 = 0x04,
69 typedef struct arm11_common_s
75 /** \name Processor type detection */
78 u32 device_id; /**< IDCODE readout */
79 u32 didr; /**< DIDR readout (debug capabilities) */
80 u8 implementor; /**< DIDR Implementor readout */
82 size_t brp; /**< Number of Breakpoint Register Pairs from DIDR */
83 size_t wrp; /**< Number of Watchpoint Register Pairs from DIDR */
85 enum arm11_debug_version
86 debug_version; /**< ARM debug architecture from DIDR */
90 u32 last_dscr; /**< Last retrieved DSCR value;
91 * Can be used to detect changes */
95 bool simulate_reset_on_next_halt;
97 /** \name Shadow registers to save processor state */
100 reg_t * reg_list; /**< target register list */
101 u32 reg_values[ARM11_REGCACHE_COUNT]; /**< data for registers */
105 arm11_register_history_t
106 reg_history[ARM11_REGCACHE_COUNT]; /**< register state before last resume */
109 size_t free_brps; /**< keep track of breakpoints allocated by arm11_add_breakpoint() */
110 size_t free_wrps; /**< keep track of breakpoints allocated by arm11_add_watchpoint() */
113 reg_cache_t *core_cache;
118 * ARM11 DBGTAP instructions
120 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/I1006229.html
122 enum arm11_instructions
126 ARM11_RESTART = 0x04,
136 ARM11_DSCR_CORE_HALTED = 1 << 0,
137 ARM11_DSCR_CORE_RESTARTED = 1 << 1,
139 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK = 0x0F << 2,
140 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT = 0x00 << 2,
141 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT = 0x01 << 2,
142 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT = 0x02 << 2,
143 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION = 0x03 << 2,
144 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ = 0x04 << 2,
145 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH = 0x05 << 2,
147 ARM11_DSCR_STICKY_PRECISE_DATA_ABORT = 1 << 6,
148 ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT = 1 << 7,
149 ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE = 1 << 13,
150 ARM11_DSCR_MODE_SELECT = 1 << 14,
151 ARM11_DSCR_WDTR_FULL = 1 << 29,
152 ARM11_DSCR_RDTR_FULL = 1 << 30,
157 ARM11_CPSR_T = 1 << 5,
158 ARM11_CPSR_J = 1 << 24,
169 ARM11_SC7_WCR0 = 112,
174 typedef struct arm11_reg_state_s
183 /* poll current target status */
184 int arm11_poll(struct target_s *target);
185 /* architecture specific status reply */
186 int arm11_arch_state(struct target_s *target);
188 /* target request support */
189 int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer);
191 /* target execution control */
192 int arm11_halt(struct target_s *target);
193 int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
194 int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
195 int arm11_examine(struct target_s *target);
197 /* target reset control */
198 int arm11_assert_reset(struct target_s *target);
199 int arm11_deassert_reset(struct target_s *target);
200 int arm11_soft_reset_halt(struct target_s *target);
202 /* target register access for gdb */
203 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size);
205 /* target memory access
206 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
207 * count: number of items of <size>
209 int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
210 int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
212 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
213 int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer);
215 int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum);
217 /* target break-/watchpoint control
218 * rw: 0 = write, 1 = read, 2 = access
220 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
221 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
222 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
223 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
225 /* target algorithm support */
226 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_param, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info);
228 int arm11_register_commands(struct command_context_s *cmd_ctx);
229 int arm11_target_create(struct target_s *target, Jim_Interp *interp);
230 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
231 int arm11_quit(void);
235 void arm11_build_reg_cache(target_t *target);
237 void arm11_record_register_history(arm11_common_t * arm11);
238 void arm11_dump_reg_changes(arm11_common_t * arm11);
243 void arm11_setup_field (arm11_common_t * arm11, int num_bits, void * in_data, void * out_data, scan_field_t * field);
244 void arm11_add_IR (arm11_common_t * arm11, u8 instr, enum tap_state state);
245 void arm11_add_debug_SCAN_N (arm11_common_t * arm11, u8 chain, enum tap_state state);
246 void arm11_add_debug_INST (arm11_common_t * arm11, u32 inst, u8 * flag, enum tap_state state);
247 u32 arm11_read_DSCR (arm11_common_t * arm11);
248 void arm11_write_DSCR (arm11_common_t * arm11, u32 dscr);
250 enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr);
252 void arm11_run_instr_data_prepare (arm11_common_t * arm11);
253 void arm11_run_instr_data_finish (arm11_common_t * arm11);
254 void arm11_run_instr_no_data (arm11_common_t * arm11, u32 * opcode, size_t count);
255 void arm11_run_instr_no_data1 (arm11_common_t * arm11, u32 opcode);
256 void arm11_run_instr_data_to_core (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
257 void arm11_run_instr_data_to_core_noack (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
258 void arm11_run_instr_data_to_core1 (arm11_common_t * arm11, u32 opcode, u32 data);
259 void arm11_run_instr_data_from_core (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
260 void arm11_run_instr_data_from_core_via_r0 (arm11_common_t * arm11, u32 opcode, u32 * data);
261 void arm11_run_instr_data_to_core_via_r0 (arm11_common_t * arm11, u32 opcode, u32 data);
263 int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, enum tap_state state);
264 int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, enum tap_state state);
267 /** Used to make a list of read/write commands for scan chain 7
269 * Use with arm11_sc7_run()
271 typedef struct arm11_sc7_action_s
273 bool write; /**< Access mode: true for write, false for read. */
274 u8 address; /**< Register address mode. Use enum #arm11_sc7 */
275 u32 value; /**< If write then set this to value to be written.
276 In read mode this receives the read value when the
278 } arm11_sc7_action_t;
280 void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count);
282 /* Mid-level helper functions */
283 void arm11_sc7_clear_vbw(arm11_common_t * arm11);
284 void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value);
286 void arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result);