1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
5 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
29 #define ARM11_REGCACHE_COUNT 3
31 #define ARM11_TAP_DEFAULT TAP_INVALID
33 #define CHECK_RETVAL(action) \
35 int __retval = (action); \
36 if (__retval != ERROR_OK) { \
37 LOG_DEBUG("error while calling \"%s\"", \
43 enum arm11_debug_version
45 ARM11_DEBUG_V6 = 0x01,
46 ARM11_DEBUG_V61 = 0x02,
47 ARM11_DEBUG_V7 = 0x03,
48 ARM11_DEBUG_V7_CP14 = 0x04,
55 /** Debug module state. */
58 size_t brp; /**< Number of Breakpoint Register Pairs from DIDR */
59 size_t wrp; /**< Number of Watchpoint Register Pairs from DIDR */
60 size_t free_brps; /**< Number of breakpoints allocated */
62 uint32_t last_dscr; /**< Last retrieved DSCR value;
63 Use only for debug message generation */
65 bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt */
67 /** \name Shadow registers to save debug state */
70 struct reg * reg_list; /**< target register list */
71 uint32_t reg_values[ARM11_REGCACHE_COUNT]; /**< data for registers */
77 struct reg_cache *core_cache;
79 struct arm_jtag jtag_info;
82 static inline struct arm11_common *target_to_arm11(struct target *target)
84 return container_of(target->arch_info, struct arm11_common,
89 * ARM11 DBGTAP instructions
91 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/I1006229.html
93 enum arm11_instructions
107 ARM11_DSCR_CORE_HALTED = 1 << 0,
108 ARM11_DSCR_CORE_RESTARTED = 1 << 1,
110 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK = 0x0F << 2,
111 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT = 0x00 << 2,
112 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT = 0x01 << 2,
113 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT = 0x02 << 2,
114 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION = 0x03 << 2,
115 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ = 0x04 << 2,
116 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH = 0x05 << 2,
118 ARM11_DSCR_STICKY_PRECISE_DATA_ABORT = 1 << 6,
119 ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT = 1 << 7,
120 ARM11_DSCR_INTERRUPTS_DISABLE = 1 << 11,
121 ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE = 1 << 13,
122 ARM11_DSCR_MODE_SELECT = 1 << 14,
123 ARM11_DSCR_WDTR_FULL = 1 << 29,
124 ARM11_DSCR_RDTR_FULL = 1 << 30,
129 ARM11_CPSR_T = 1 << 5,
130 ARM11_CPSR_J = 1 << 24,
141 ARM11_SC7_WCR0 = 112,
144 struct arm11_reg_state
147 struct target * target;