1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
18 ***************************************************************************/
25 #include "embeddedice.h"
33 #define asizeof(x) (sizeof(x) / sizeof((x)[0]))
35 #define NEW(type, variable, items) \
36 type * variable = malloc(sizeof(type) * items)
39 #define ARM11_REGCACHE_MODEREGS 0
40 #define ARM11_REGCACHE_FREGS 0
42 #define ARM11_REGCACHE_COUNT (20 + \
43 23 * ARM11_REGCACHE_MODEREGS + \
44 9 * ARM11_REGCACHE_FREGS)
47 typedef struct arm11_register_history_s
51 }arm11_register_history_t;
55 typedef struct arm11_common_s
61 /** \name Processor type detection */
64 u32 device_id; /**< IDCODE readout */
65 u32 didr; /**< DIDR readout (debug capabilities) */
66 u8 implementor; /**< DIDR Implementor readout */
68 size_t brp; /**< Number of Breakpoint Register Pairs */
69 size_t wrp; /**< Number of Watchpoint Register Pairs */
74 u32 last_dscr; /**< Last retrieved DSCR value;
75 * Can be used to detect changes */
80 /** \name Shadow registers to save processor state */
83 reg_t * reg_list; /**< target register list */
84 u32 reg_values[ARM11_REGCACHE_COUNT]; /**< data for registers */
88 arm11_register_history_t
89 reg_history[ARM11_REGCACHE_COUNT]; /**< register state before last resume */
96 * ARM11 DBGTAP instructions
98 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/I1006229.html
100 enum arm11_instructions
104 ARM11_RESTART = 0x04,
114 ARM11_DSCR_CORE_HALTED = 1 << 0,
115 ARM11_DSCR_CORE_RESTARTED = 1 << 1,
117 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK = 0x0F << 2,
118 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT = 0x00 << 2,
119 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT = 0x01 << 2,
120 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT = 0x02 << 2,
121 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION = 0x03 << 2,
122 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ = 0x04 << 2,
123 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH = 0x05 << 2,
125 ARM11_DSCR_STICKY_PRECISE_DATA_ABORT = 1 << 6,
126 ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT = 1 << 7,
127 ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE = 1 << 13,
128 ARM11_DSCR_MODE_SELECT = 1 << 14,
129 ARM11_DSCR_WDTR_FULL = 1 << 29,
130 ARM11_DSCR_RDTR_FULL = 1 << 30,
135 ARM11_CPSR_T = 1 << 5,
136 ARM11_CPSR_J = 1 << 24,
147 ARM11_SC7_WCR0 = 112,
152 typedef struct arm11_reg_state_s
161 /* poll current target status */
162 int arm11_poll(struct target_s *target);
163 /* architecture specific status reply */
164 int arm11_arch_state(struct target_s *target);
166 /* target request support */
167 int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer);
169 /* target execution control */
170 int arm11_halt(struct target_s *target);
171 int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
172 int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
174 /* target reset control */
175 int arm11_assert_reset(struct target_s *target);
176 int arm11_deassert_reset(struct target_s *target);
177 int arm11_soft_reset_halt(struct target_s *target);
178 int arm11_prepare_reset_halt(struct target_s *target);
180 /* target register access for gdb */
181 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size);
183 /* target memory access
184 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
185 * count: number of items of <size>
187 int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
188 int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
190 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
191 int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer);
193 int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum);
195 /* target break-/watchpoint control
196 * rw: 0 = write, 1 = read, 2 = access
198 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
199 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
200 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
201 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
203 /* target algorithm support */
204 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_param, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info);
206 int arm11_register_commands(struct command_context_s *cmd_ctx);
207 int arm11_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
208 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
209 int arm11_quit(void);
213 void arm11_build_reg_cache(target_t *target);
218 void arm11_setup_field (arm11_common_t * arm11, int num_bits, void * in_data, void * out_data, scan_field_t * field);
219 void arm11_add_IR (arm11_common_t * arm11, u8 instr, enum tap_state state);
220 void arm11_add_debug_SCAN_N (arm11_common_t * arm11, u8 chain, enum tap_state state);
221 void arm11_add_debug_INST (arm11_common_t * arm11, u32 inst, u8 * flag, enum tap_state state);
222 u32 arm11_read_DSCR (arm11_common_t * arm11);
223 void arm11_write_DSCR (arm11_common_t * arm11, u32 dscr);
225 enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr);
227 void arm11_run_instr_data_prepare (arm11_common_t * arm11);
228 void arm11_run_instr_data_finish (arm11_common_t * arm11);
229 void arm11_run_instr_no_data (arm11_common_t * arm11, u32 * opcode, size_t count);
230 void arm11_run_instr_no_data1 (arm11_common_t * arm11, u32 opcode);
231 void arm11_run_instr_data_to_core (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
232 void arm11_run_instr_data_to_core1 (arm11_common_t * arm11, u32 opcode, u32 data);
233 void arm11_run_instr_data_from_core (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
234 void arm11_run_instr_data_from_core_via_r0 (arm11_common_t * arm11, u32 opcode, u32 * data);
235 void arm11_run_instr_data_to_core_via_r0 (arm11_common_t * arm11, u32 opcode, u32 data);
238 typedef struct arm11_sc7_action_s
243 } arm11_sc7_action_t;
245 void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count);
246 void arm11_sc7_clear_bw(arm11_common_t * arm11);