1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
4 * Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
20 ***************************************************************************/
34 #define JTAG_DEBUG(expr ...) DEBUG(expr)
36 #define JTAG_DEBUG(expr ...) do {} while(0)
39 tap_state_t arm11_move_pi_to_si_via_ci[] =
41 TAP_IREXIT2, TAP_IRUPDATE, TAP_DRSELECT, TAP_IRSELECT, TAP_IRCAPTURE, TAP_IRSHIFT
45 int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state)
47 if (cmd_queue_cur_state == TAP_IRPAUSE)
48 jtag_add_pathmove(asizeof(arm11_move_pi_to_si_via_ci), arm11_move_pi_to_si_via_ci);
50 jtag_add_ir_scan(num_fields, fields, state);
54 tap_state_t arm11_move_pd_to_sd_via_cd[] =
56 TAP_DREXIT2, TAP_DRUPDATE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT
59 int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state)
61 if (cmd_queue_cur_state == TAP_DRPAUSE)
62 jtag_add_pathmove(asizeof(arm11_move_pd_to_sd_via_cd), arm11_move_pd_to_sd_via_cd);
64 jtag_add_dr_scan(num_fields, fields, state);
69 /** Code de-clutter: Construct scan_field_t to write out a value
71 * \param arm11 Target state variable.
72 * \param num_bits Length of the data field
73 * \param out_data pointer to the data that will be sent out
74 * <em>(data is read when it is added to the JTAG queue)</em>
75 * \param in_data pointer to the memory that will receive data that was clocked in
76 * <em>(data is written when the JTAG queue is executed)</em>
77 * \param field target data structure that will be initialized
79 void arm11_setup_field(arm11_common_t * arm11, int num_bits, void * out_data, void * in_data, scan_field_t * field)
81 field->tap = arm11->jtag_info.tap;
82 field->num_bits = num_bits;
83 field->out_mask = NULL;
84 field->in_check_mask = NULL;
85 field->in_check_value = NULL;
86 field->in_handler = NULL;
87 field->in_handler_priv = NULL;
89 field->out_value = out_data;
90 field->in_value = in_data;
94 /** Write JTAG instruction register
96 * \param arm11 Target state variable.
97 * \param instr An ARM11 DBGTAP instruction. Use enum #arm11_instructions.
98 * \param state Pass the final TAP state or ARM11_TAP_DEFAULT for the default value (Pause-IR).
100 * \remarks This adds to the JTAG command queue but does \em not execute it.
102 void arm11_add_IR(arm11_common_t * arm11, u8 instr, tap_state_t state)
105 tap = arm11->jtag_info.tap;
107 if (buf_get_u32(tap->cur_instr, 0, 5) == instr)
109 JTAG_DEBUG("IR <= 0x%02x SKIPPED", instr);
113 JTAG_DEBUG("IR <= 0x%02x", instr);
117 arm11_setup_field(arm11, 5, &instr, NULL, &field);
119 arm11_add_ir_scan_vc(1, &field, state == ARM11_TAP_DEFAULT ? TAP_IRPAUSE : state);
122 /** Verify shifted out data from Scan Chain Register (SCREG)
123 * Used as parameter to scan_field_t::in_handler in
124 * arm11_add_debug_SCAN_N().
127 static int arm11_in_handler_SCAN_N(u8 *in_value, void *priv, struct scan_field_s *field)
129 /** \todo TODO: clarify why this isnt properly masked in jtag.c jtag_read_buffer() */
130 u8 v = *in_value & 0x1F;
134 LOG_ERROR("'arm11 target' JTAG communication error SCREG SCAN OUT 0x%02x (expected 0x10)", v);
138 JTAG_DEBUG("SCREG SCAN OUT 0x%02x", v);
142 /** Select and write to Scan Chain Register (SCREG)
144 * This function sets the instruction register to SCAN_N and writes
145 * the data register with the selected chain number.
147 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/Cacbjhfg.html
149 * \param arm11 Target state variable.
150 * \param chain Scan chain that will be selected.
151 * \param state Pass the final TAP state or ARM11_TAP_DEFAULT for the default
154 * The chain takes effect when Update-DR is passed (usually when subsequently
155 * the INTEXT/EXTEST instructions are written).
157 * \warning (Obsolete) Using this twice in a row will \em fail. The first
158 * call will end in Pause-DR. The second call, due to the IR
159 * caching, will not go through Capture-DR when shifting in the
160 * new scan chain number. As a result the verification in
161 * arm11_in_handler_SCAN_N() must fail.
163 * \remarks This adds to the JTAG command queue but does \em not execute it.
166 void arm11_add_debug_SCAN_N(arm11_common_t * arm11, u8 chain, tap_state_t state)
168 JTAG_DEBUG("SCREG <= 0x%02x", chain);
170 arm11_add_IR(arm11, ARM11_SCAN_N, ARM11_TAP_DEFAULT);
174 arm11_setup_field(arm11, 5, &chain, NULL, &field);
176 field.in_handler = arm11_in_handler_SCAN_N;
178 arm11_add_dr_scan_vc(1, &field, state == ARM11_TAP_DEFAULT ? TAP_DRPAUSE : state);
181 /** Write an instruction into the ITR register
183 * \param arm11 Target state variable.
184 * \param inst An ARM11 processor instruction/opcode.
185 * \param flag Optional parameter to retrieve the InstCompl flag
186 * (this will be written when the JTAG chain is executed).
187 * \param state Pass the final TAP state or ARM11_TAP_DEFAULT for the default
188 * value (Run-Test/Idle).
190 * \remarks By default this ends with Run-Test/Idle state
191 * and causes the instruction to be executed. If
192 * a subsequent write to DTR is needed before
193 * executing the instruction then TAP_DRPAUSE should be
194 * passed to \p state.
196 * \remarks This adds to the JTAG command queue but does \em not execute it.
198 void arm11_add_debug_INST(arm11_common_t * arm11, u32 inst, u8 * flag, tap_state_t state)
200 JTAG_DEBUG("INST <= 0x%08x", inst);
204 arm11_setup_field(arm11, 32, &inst, NULL, itr + 0);
205 arm11_setup_field(arm11, 1, NULL, flag, itr + 1);
207 arm11_add_dr_scan_vc(asizeof(itr), itr, state == ARM11_TAP_DEFAULT ? TAP_IDLE : state);
210 /** Read the Debug Status and Control Register (DSCR)
214 * \param arm11 Target state variable.
215 * \return DSCR content
217 * \remarks This is a stand-alone function that executes the JTAG command queue.
219 int arm11_read_DSCR(arm11_common_t * arm11, u32 *value)
221 arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
223 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
226 scan_field_t chain1_field;
228 arm11_setup_field(arm11, 32, NULL, &dscr, &chain1_field);
230 arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE);
233 if ((retval=jtag_execute_queue())!=ERROR_OK)
238 if (arm11->last_dscr != dscr)
239 JTAG_DEBUG("DSCR = %08x (OLD %08x)", dscr, arm11->last_dscr);
241 arm11->last_dscr = dscr;
248 /** Write the Debug Status and Control Register (DSCR)
252 * \param arm11 Target state variable.
253 * \param dscr DSCR content
255 * \remarks This is a stand-alone function that executes the JTAG command queue.
257 int arm11_write_DSCR(arm11_common_t * arm11, u32 dscr)
259 arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
261 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
263 scan_field_t chain1_field;
265 arm11_setup_field(arm11, 32, &dscr, NULL, &chain1_field);
267 arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE);
270 if ((retval=jtag_execute_queue())!=ERROR_OK)
273 JTAG_DEBUG("DSCR <= %08x (OLD %08x)", dscr, arm11->last_dscr);
275 arm11->last_dscr = dscr;
282 /** Get the debug reason from Debug Status and Control Register (DSCR)
284 * \param dscr DSCR value to analyze
285 * \return Debug reason
288 enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr)
290 switch (dscr & ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK)
292 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT:
293 LOG_INFO("Debug entry: JTAG HALT");
294 return DBG_REASON_DBGRQ;
296 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT:
297 LOG_INFO("Debug entry: breakpoint");
298 return DBG_REASON_BREAKPOINT;
300 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT:
301 LOG_INFO("Debug entry: watchpoint");
302 return DBG_REASON_WATCHPOINT;
304 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION:
305 LOG_INFO("Debug entry: BKPT instruction");
306 return DBG_REASON_BREAKPOINT;
308 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ:
309 LOG_INFO("Debug entry: EDBGRQ signal");
310 return DBG_REASON_DBGRQ;
312 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH:
313 LOG_INFO("Debug entry: VCR vector catch");
314 return DBG_REASON_BREAKPOINT;
317 LOG_INFO("Debug entry: unknown");
318 return DBG_REASON_DBGRQ;
324 /** Prepare the stage for ITR/DTR operations
325 * from the arm11_run_instr... group of functions.
327 * Put arm11_run_instr_data_prepare() and arm11_run_instr_data_finish()
328 * around a block of arm11_run_instr_... calls.
330 * Select scan chain 5 to allow quick access to DTR. When scan
331 * chain 4 is needed to put in a register the ITRSel instruction
332 * shortcut is used instead of actually changing the Scan_N
335 * \param arm11 Target state variable.
338 void arm11_run_instr_data_prepare(arm11_common_t * arm11)
340 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
343 /** Cleanup after ITR/DTR operations
344 * from the arm11_run_instr... group of functions
346 * Put arm11_run_instr_data_prepare() and arm11_run_instr_data_finish()
347 * around a block of arm11_run_instr_... calls.
349 * Any IDLE can lead to an instruction execution when
350 * scan chains 4 or 5 are selected and the IR holds
351 * INTEST or EXTEST. So we must disable that before
352 * any following activities lead to an IDLE.
354 * \param arm11 Target state variable.
357 void arm11_run_instr_data_finish(arm11_common_t * arm11)
359 arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
363 /** Execute one or multiple instructions via ITR
365 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
367 * \param arm11 Target state variable.
368 * \param opcode Pointer to sequence of ARM opcodes
369 * \param count Number of opcodes to execute
372 int arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count)
374 arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
378 arm11_add_debug_INST(arm11, *opcode++, NULL, TAP_IDLE);
384 arm11_add_debug_INST(arm11, 0, &flag, count ? TAP_IDLE : TAP_DRPAUSE);
387 if ((retval=jtag_execute_queue())!=ERROR_OK)
398 /** Execute one instruction via ITR
400 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
402 * \param arm11 Target state variable.
403 * \param opcode ARM opcode
406 void arm11_run_instr_no_data1(arm11_common_t * arm11, u32 opcode)
408 arm11_run_instr_no_data(arm11, &opcode, 1);
412 /** Execute one instruction via ITR repeatedly while
413 * passing data to the core via DTR on each execution.
415 * The executed instruction \em must read data from DTR.
417 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
419 * \param arm11 Target state variable.
420 * \param opcode ARM opcode
421 * \param data Pointer to the data words to be passed to the core
422 * \param count Number of data words and instruction repetitions
425 int arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
427 arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
429 arm11_add_debug_INST(arm11, opcode, NULL, TAP_DRPAUSE);
431 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
433 scan_field_t chain5_fields[3];
439 arm11_setup_field(arm11, 32, &Data, NULL, chain5_fields + 0);
440 arm11_setup_field(arm11, 1, NULL, &Ready, chain5_fields + 1);
441 arm11_setup_field(arm11, 1, NULL, &nRetry, chain5_fields + 2);
449 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_IDLE);
451 if ((retval=jtag_execute_queue())!=ERROR_OK)
454 JTAG_DEBUG("DTR Ready %d nRetry %d", Ready, nRetry);
461 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
467 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
469 if ((retval=jtag_execute_queue())!=ERROR_OK)
472 JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
479 /** JTAG path for arm11_run_instr_data_to_core_noack
481 * The repeated TAP_IDLE's do not cause a repeated execution
482 * if passed without leaving the state.
484 * Since this is more than 7 bits (adjustable via adding more
485 * TAP_IDLE's) it produces an artificial delay in the lower
486 * layer (FT2232) that is long enough to finish execution on
487 * the core but still shorter than any manually inducible delays.
490 tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] =
492 TAP_DREXIT2, TAP_DRUPDATE, TAP_IDLE, TAP_IDLE, TAP_IDLE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT
497 /** Execute one instruction via ITR repeatedly while
498 * passing data to the core via DTR on each execution.
500 * No Ready check during transmission.
502 * The executed instruction \em must read data from DTR.
504 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
506 * \param arm11 Target state variable.
507 * \param opcode ARM opcode
508 * \param data Pointer to the data words to be passed to the core
509 * \param count Number of data words and instruction repetitions
512 int arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
514 arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
516 arm11_add_debug_INST(arm11, opcode, NULL, TAP_DRPAUSE);
518 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
520 scan_field_t chain5_fields[3];
522 arm11_setup_field(arm11, 32, NULL/*&Data*/, NULL, chain5_fields + 0);
523 arm11_setup_field(arm11, 1, NULL, NULL /*&Ready*/, chain5_fields + 1);
524 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
526 u8 Readies[count + 1];
527 u8 * ReadyPos = Readies;
531 chain5_fields[0].out_value = (void *)(data++);
532 chain5_fields[1].in_value = ReadyPos++;
536 jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
537 jtag_add_pathmove(asizeof(arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay),
538 arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay);
542 jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, TAP_IDLE);
546 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
548 chain5_fields[0].out_value = 0;
549 chain5_fields[1].in_value = ReadyPos++;
551 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
554 if ((retval=jtag_execute_queue())!=ERROR_OK)
557 size_t error_count = 0;
560 for (i = 0; i < asizeof(Readies); i++)
569 LOG_ERROR("Transfer errors " ZU, error_count);
575 /** Execute an instruction via ITR while handing data into the core via DTR.
577 * The executed instruction \em must read data from DTR.
579 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
581 * \param arm11 Target state variable.
582 * \param opcode ARM opcode
583 * \param data Data word to be passed to the core via DTR
586 int arm11_run_instr_data_to_core1(arm11_common_t * arm11, u32 opcode, u32 data)
588 return arm11_run_instr_data_to_core(arm11, opcode, &data, 1);
592 /** Execute one instruction via ITR repeatedly while
593 * reading data from the core via DTR on each execution.
595 * The executed instruction \em must write data to DTR.
597 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
599 * \param arm11 Target state variable.
600 * \param opcode ARM opcode
601 * \param data Pointer to an array that receives the data words from the core
602 * \param count Number of data words and instruction repetitions
605 int arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
607 arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
609 arm11_add_debug_INST(arm11, opcode, NULL, TAP_IDLE);
611 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
613 scan_field_t chain5_fields[3];
619 arm11_setup_field(arm11, 32, NULL, &Data, chain5_fields + 0);
620 arm11_setup_field(arm11, 1, NULL, &Ready, chain5_fields + 1);
621 arm11_setup_field(arm11, 1, NULL, &nRetry, chain5_fields + 2);
627 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, count ? TAP_IDLE : TAP_DRPAUSE);
629 if ((retval=jtag_execute_queue())!=ERROR_OK)
632 JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
642 /** Execute one instruction via ITR
643 * then load r0 into DTR and read DTR from core.
645 * The first executed instruction (\p opcode) should write data to r0.
647 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
649 * \param arm11 Target state variable.
650 * \param opcode ARM opcode to write r0 with the value of interest
651 * \param data Pointer to a data word that receives the value from r0 after \p opcode was executed.
654 void arm11_run_instr_data_from_core_via_r0(arm11_common_t * arm11, u32 opcode, u32 * data)
656 arm11_run_instr_no_data1(arm11, opcode);
658 /* MCR p14,0,R0,c0,c5,0 (move r0 -> wDTR -> local var) */
659 arm11_run_instr_data_from_core(arm11, 0xEE000E15, data, 1);
662 /** Load data into core via DTR then move it to r0 then
663 * execute one instruction via ITR
665 * The final executed instruction (\p opcode) should read data from r0.
667 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
669 * \param arm11 Target state variable.
670 * \param opcode ARM opcode to read r0 act upon it
671 * \param data Data word that will be written to r0 before \p opcode is executed
674 void arm11_run_instr_data_to_core_via_r0(arm11_common_t * arm11, u32 opcode, u32 data)
676 /* MRC p14,0,r0,c0,c5,0 */
677 arm11_run_instr_data_to_core1(arm11, 0xEE100E15, data);
679 arm11_run_instr_no_data1(arm11, opcode);
682 /** Apply reads and writes to scan chain 7
684 * \see arm11_sc7_action_t
686 * \param arm11 Target state variable.
687 * \param actions A list of read and/or write instructions
688 * \param count Number of instructions in the list.
691 int arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count)
693 arm11_add_debug_SCAN_N(arm11, 0x07, ARM11_TAP_DEFAULT);
695 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
697 scan_field_t chain7_fields[3];
706 arm11_setup_field(arm11, 1, &nRW, &Ready, chain7_fields + 0);
707 arm11_setup_field(arm11, 32, &DataOut, &DataIn, chain7_fields + 1);
708 arm11_setup_field(arm11, 7, &AddressOut, &AddressIn, chain7_fields + 2);
711 for (i = 0; i < count + 1; i++)
715 nRW = actions[i].write ? 1 : 0;
716 DataOut = actions[i].value;
717 AddressOut = actions[i].address;
728 JTAG_DEBUG("SC7 <= Address %02x Data %08x nRW %d", AddressOut, DataOut, nRW);
730 arm11_add_dr_scan_vc(asizeof(chain7_fields), chain7_fields, TAP_DRPAUSE);
732 if ((retval=jtag_execute_queue())!=ERROR_OK)
735 JTAG_DEBUG("SC7 => Address %02x Data %08x Ready %d", AddressIn, DataIn, Ready);
737 while (!Ready); /* 'nRW' is 'Ready' on read out */
741 if (actions[i - 1].address != AddressIn)
743 LOG_WARNING("Scan chain 7 shifted out unexpected address");
746 if (!actions[i - 1].write)
748 actions[i - 1].value = DataIn;
752 if (actions[i - 1].value != DataIn)
754 LOG_WARNING("Scan chain 7 shifted out unexpected data");
761 for (i = 0; i < count; i++)
763 JTAG_DEBUG("SC7 %02d: %02x %s %08x", i, actions[i].address, actions[i].write ? "<=" : "=>", actions[i].value);
769 /** Clear VCR and all breakpoints and watchpoints via scan chain 7
771 * \param arm11 Target state variable.
774 void arm11_sc7_clear_vbw(arm11_common_t * arm11)
776 arm11_sc7_action_t clear_bw[arm11->brp + arm11->wrp + 1];
777 arm11_sc7_action_t * pos = clear_bw;
780 for (i = 0; i < asizeof(clear_bw); i++)
782 clear_bw[i].write = true;
783 clear_bw[i].value = 0;
787 for (i = 0; i < arm11->brp; i++)
788 (pos++)->address = ARM11_SC7_BCR0 + i;
792 for (i = 0; i < arm11->wrp; i++)
793 (pos++)->address = ARM11_SC7_WCR0 + i;
796 (pos++)->address = ARM11_SC7_VCR;
798 arm11_sc7_run(arm11, clear_bw, asizeof(clear_bw));
801 /** Write VCR register
803 * \param arm11 Target state variable.
804 * \param value Value to be written
806 void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value)
808 arm11_sc7_action_t set_vcr;
810 set_vcr.write = true;
811 set_vcr.address = ARM11_SC7_VCR;
812 set_vcr.value = value;
815 arm11_sc7_run(arm11, &set_vcr, 1);
820 /** Read word from address
822 * \param arm11 Target state variable.
823 * \param address Memory address to be read
824 * \param result Pointer where to store result
827 int arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result)
830 arm11_run_instr_data_prepare(arm11);
832 /* MRC p14,0,r0,c0,c5,0 (r0 = address) */
833 if ((retval=arm11_run_instr_data_to_core1(arm11, 0xee100e15, address))!=ERROR_OK)
836 /* LDC p14,c5,[R0],#4 (DTR = [r0]) */
837 if ((retval=arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1))!=ERROR_OK)
840 arm11_run_instr_data_finish(arm11);