1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
32 #define _DEBUG_INSTRUCTION_EXECUTION_
36 int arm720t_register_commands(struct command_context_s *cmd_ctx);
38 int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
39 int arm720t_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
40 int arm720t_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
41 int arm720t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
43 /* forward declarations */
44 int arm720t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
45 int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
47 int arm720t_arch_state(struct target_s *target, char *buf, int buf_size);
48 int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
49 int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
50 int arm720t_soft_reset_halt(struct target_s *target);
52 target_type_t arm720t_target =
57 .arch_state = arm720t_arch_state,
60 .resume = arm7_9_resume,
63 .assert_reset = arm7_9_assert_reset,
64 .deassert_reset = arm7_9_deassert_reset,
65 .soft_reset_halt = arm720t_soft_reset_halt,
67 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
69 .read_memory = arm720t_read_memory,
70 .write_memory = arm720t_write_memory,
71 .bulk_write_memory = arm7_9_bulk_write_memory,
73 .run_algorithm = armv4_5_run_algorithm,
75 .add_breakpoint = arm7_9_add_breakpoint,
76 .remove_breakpoint = arm7_9_remove_breakpoint,
77 .add_watchpoint = arm7_9_add_watchpoint,
78 .remove_watchpoint = arm7_9_remove_watchpoint,
80 .register_commands = arm720t_register_commands,
81 .target_command = arm720t_target_command,
82 .init_target = arm720t_init_target,
86 int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int clock)
88 armv4_5_common_t *armv4_5 = target->arch_info;
89 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
90 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
91 scan_field_t fields[2];
93 u8 instruction_buf = instruction;
95 buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
97 jtag_add_end_state(TAP_PD);
98 arm_jtag_scann(jtag_info, 0xf);
99 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
101 fields[0].device = jtag_info->chain_pos;
102 fields[0].num_bits = 1;
103 fields[0].out_value = &instruction_buf;
104 fields[0].out_mask = NULL;
105 fields[0].in_value = NULL;
106 fields[0].in_check_value = NULL;
107 fields[0].in_check_mask = NULL;
108 fields[0].in_handler = NULL;
109 fields[0].in_handler_priv = NULL;
111 fields[1].device = jtag_info->chain_pos;
112 fields[1].num_bits = 32;
113 fields[1].out_value = out_buf;
114 fields[1].out_mask = NULL;
115 fields[1].in_value = NULL;
118 fields[1].in_handler = arm_jtag_buf_to_u32_flip;
119 fields[1].in_handler_priv = in;
122 fields[1].in_handler = NULL;
123 fields[1].in_handler_priv = NULL;
125 fields[1].in_check_value = NULL;
126 fields[1].in_check_mask = NULL;
128 jtag_add_dr_scan(2, fields, -1);
131 jtag_add_runtest(0, -1);
133 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
134 jtag_execute_queue();
137 DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
139 DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
141 DEBUG("out: %8.8x, instruction: %i, clock: %i", in, out, instruction, clock);
147 int arm720t_read_cp15(target_t *target, u32 opcode, u32 *value)
149 /* fetch CP15 opcode */
150 arm720t_scan_cp15(target, opcode, NULL, 1, 1);
152 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
153 /* "EXECUTE" stage (1) */
154 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
155 arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
156 /* "EXECUTE" stage (2) */
157 arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
158 /* "EXECUTE" stage (3), CDATA is read */
159 arm720t_scan_cp15(target, ARMV4_5_NOP, value, 1, 1);
164 int arm720t_write_cp15(target_t *target, u32 opcode, u32 value)
166 /* fetch CP15 opcode */
167 arm720t_scan_cp15(target, opcode, NULL, 1, 1);
169 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
170 /* "EXECUTE" stage (1) */
171 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
172 arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
173 /* "EXECUTE" stage (2) */
174 arm720t_scan_cp15(target, value, NULL, 0, 1);
175 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
180 u32 arm720t_get_ttb(target_t *target)
184 arm720t_read_cp15(target, 0xee120f10, &ttb);
185 jtag_execute_queue();
192 void arm720t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
196 /* read cp15 control register */
197 arm720t_read_cp15(target, 0xee110f10, &cp15_control);
198 jtag_execute_queue();
201 cp15_control &= ~0x1U;
203 if (d_u_cache || i_cache)
204 cp15_control &= ~0x4U;
206 arm720t_write_cp15(target, 0xee010f10, cp15_control);
209 void arm720t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
213 /* read cp15 control register */
214 arm720t_read_cp15(target, 0xee110f10, &cp15_control);
215 jtag_execute_queue();
218 cp15_control |= 0x1U;
220 if (d_u_cache || i_cache)
221 cp15_control |= 0x4U;
223 arm720t_write_cp15(target, 0xee010f10, cp15_control);
226 void arm720t_post_debug_entry(target_t *target)
228 armv4_5_common_t *armv4_5 = target->arch_info;
229 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
230 arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
231 arm720t_common_t *arm720t = arm7tdmi->arch_info;
233 /* examine cp15 control reg */
234 arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
235 jtag_execute_queue();
236 DEBUG("cp15_control_reg: %8.8x", arm720t->cp15_control_reg);
238 arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
239 arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0;
240 arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
242 /* save i/d fault status and address register */
243 arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr);
244 arm720t_read_cp15(target, 0xee160f10, &arm720t->far);
245 jtag_execute_queue();
248 void arm720t_pre_restore_context(target_t *target)
250 armv4_5_common_t *armv4_5 = target->arch_info;
251 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
252 arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
253 arm720t_common_t *arm720t = arm7tdmi->arch_info;
255 /* restore i/d fault status and address register */
256 arm720t_write_cp15(target, 0xee050f10, arm720t->fsr);
257 arm720t_write_cp15(target, 0xee060f10, arm720t->far);
260 int arm720t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm7tdmi_common_t **arm7tdmi_p, arm720t_common_t **arm720t_p)
262 armv4_5_common_t *armv4_5 = target->arch_info;
263 arm7_9_common_t *arm7_9;
264 arm7tdmi_common_t *arm7tdmi;
265 arm720t_common_t *arm720t;
267 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
272 arm7_9 = armv4_5->arch_info;
273 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
278 arm7tdmi = arm7_9->arch_info;
279 if (arm7tdmi->common_magic != ARM7TDMI_COMMON_MAGIC)
284 arm720t = arm7tdmi->arch_info;
285 if (arm720t->common_magic != ARM720T_COMMON_MAGIC)
290 *armv4_5_p = armv4_5;
292 *arm7tdmi_p = arm7tdmi;
293 *arm720t_p = arm720t;
298 int arm720t_arch_state(struct target_s *target, char *buf, int buf_size)
300 armv4_5_common_t *armv4_5 = target->arch_info;
301 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
302 arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
303 arm720t_common_t *arm720t = arm7tdmi->arch_info;
307 "disabled", "enabled"
310 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
312 ERROR("BUG: called for a non-ARMv4/5 target");
316 snprintf(buf, buf_size,
317 "target halted in %s state due to %s, current mode: %s\n"
318 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
319 "MMU: %s, Cache: %s",
320 armv4_5_state_strings[armv4_5->core_state],
321 target_debug_reason_strings[target->debug_reason],
322 armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
323 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
324 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
325 state[arm720t->armv4_5_mmu.mmu_enabled],
326 state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]);
331 int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
334 armv4_5_common_t *armv4_5 = target->arch_info;
335 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
336 arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
337 arm720t_common_t *arm720t = arm7tdmi->arch_info;
339 /* disable cache, but leave MMU enabled */
340 if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
341 arm720t_disable_mmu_caches(target, 0, 1, 0);
343 retval = arm7_9_read_memory(target, address, size, count, buffer);
345 if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
346 arm720t_enable_mmu_caches(target, 0, 1, 0);
351 int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
355 if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
361 int arm720t_soft_reset_halt(struct target_s *target)
363 armv4_5_common_t *armv4_5 = target->arch_info;
364 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
365 arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
366 arm720t_common_t *arm720t = arm7tdmi->arch_info;
367 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
369 if (target->state == TARGET_RUNNING)
371 target->type->halt(target);
374 while (buf_get_u32(dbg_stat->value, EICE_DBG_CONTROL_DBGACK, 1) == 0)
376 embeddedice_read_reg(dbg_stat);
377 jtag_execute_queue();
380 target->state = TARGET_HALTED;
382 /* SVC, ARM state, IRQ and FIQ disabled */
383 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
384 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
385 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
387 /* start fetching from 0x0 */
388 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
389 armv4_5->core_cache->reg_list[15].dirty = 1;
390 armv4_5->core_cache->reg_list[15].valid = 1;
392 armv4_5->core_mode = ARMV4_5_MODE_SVC;
393 armv4_5->core_state = ARMV4_5_STATE_ARM;
395 arm720t_disable_mmu_caches(target, 1, 1, 1);
396 arm720t->armv4_5_mmu.mmu_enabled = 0;
397 arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
398 arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
400 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
405 int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
407 arm7tdmi_init_target(cmd_ctx, target);
419 int arm720t_init_arch_info(target_t *target, arm720t_common_t *arm720t, int chain_pos, char *variant)
421 arm7tdmi_common_t *arm7tdmi = &arm720t->arm7tdmi_common;
422 arm7_9_common_t *arm7_9 = &arm7tdmi->arm7_9_common;
424 arm7tdmi_init_arch_info(target, arm7tdmi, chain_pos, variant);
426 arm7tdmi->arch_info = arm720t;
427 arm720t->common_magic = ARM720T_COMMON_MAGIC;
429 arm7_9->post_debug_entry = arm720t_post_debug_entry;
430 arm7_9->pre_restore_context = arm720t_pre_restore_context;
432 arm720t->armv4_5_mmu.armv4_5_cache.ctype = -1;
433 arm720t->armv4_5_mmu.get_ttb = arm720t_get_ttb;
434 arm720t->armv4_5_mmu.read_memory = arm7_9_read_memory;
435 arm720t->armv4_5_mmu.write_memory = arm7_9_write_memory;
436 arm720t->armv4_5_mmu.disable_mmu_caches = arm720t_disable_mmu_caches;
437 arm720t->armv4_5_mmu.enable_mmu_caches = arm720t_enable_mmu_caches;
438 arm720t->armv4_5_mmu.has_tiny_pages = 0;
439 arm720t->armv4_5_mmu.mmu_enabled = 0;
444 int arm720t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
447 char *variant = NULL;
448 arm720t_common_t *arm720t = malloc(sizeof(arm720t_common_t));
452 ERROR("'target arm720t' requires at least one additional argument");
456 chain_pos = strtoul(args[3], NULL, 0);
461 DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
463 arm720t_init_arch_info(target, arm720t, chain_pos, variant);
468 int arm720t_register_commands(struct command_context_s *cmd_ctx)
471 command_t *arm720t_cmd;
474 retval = arm7tdmi_register_commands(cmd_ctx);
476 arm720t_cmd = register_command(cmd_ctx, NULL, "arm720t", NULL, COMMAND_ANY, "arm720t specific commands");
478 register_command(cmd_ctx, arm720t_cmd, "cp15", arm720t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode> [value]");
479 register_command(cmd_ctx, arm720t_cmd, "virt2phys", arm720t_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
481 register_command(cmd_ctx, arm720t_cmd, "mdw_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
482 register_command(cmd_ctx, arm720t_cmd, "mdh_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
483 register_command(cmd_ctx, arm720t_cmd, "mdb_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
485 register_command(cmd_ctx, arm720t_cmd, "mww_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
486 register_command(cmd_ctx, arm720t_cmd, "mwh_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
487 register_command(cmd_ctx, arm720t_cmd, "mwb_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
492 int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
495 target_t *target = get_current_target(cmd_ctx);
496 armv4_5_common_t *armv4_5;
497 arm7_9_common_t *arm7_9;
498 arm7tdmi_common_t *arm7tdmi;
499 arm720t_common_t *arm720t;
500 arm_jtag_t *jtag_info;
502 if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
504 command_print(cmd_ctx, "current target isn't an ARM720t target");
508 jtag_info = &arm7_9->jtag_info;
510 if (target->state != TARGET_HALTED)
512 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
516 /* one or more argument, access a single register (write if second argument is given */
519 u32 opcode = strtoul(args[0], NULL, 0);
524 if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK)
526 command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8x", opcode);
529 jtag_execute_queue();
531 command_print(cmd_ctx, "0x%8.8x: 0x%8.8x", opcode, value);
535 u32 value = strtoul(args[1], NULL, 0);
536 if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK)
538 command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8x", opcode);
541 command_print(cmd_ctx, "0x%8.8x: 0x%8.8x", opcode, value);
548 int arm720t_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
550 target_t *target = get_current_target(cmd_ctx);
551 armv4_5_common_t *armv4_5;
552 arm7_9_common_t *arm7_9;
553 arm7tdmi_common_t *arm7tdmi;
554 arm720t_common_t *arm720t;
555 arm_jtag_t *jtag_info;
557 if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
559 command_print(cmd_ctx, "current target isn't an ARM720t target");
563 jtag_info = &arm7_9->jtag_info;
565 if (target->state != TARGET_HALTED)
567 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
571 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
574 int arm720t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
576 target_t *target = get_current_target(cmd_ctx);
577 armv4_5_common_t *armv4_5;
578 arm7_9_common_t *arm7_9;
579 arm7tdmi_common_t *arm7tdmi;
580 arm720t_common_t *arm720t;
581 arm_jtag_t *jtag_info;
583 if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
585 command_print(cmd_ctx, "current target isn't an ARM720t target");
589 jtag_info = &arm7_9->jtag_info;
591 if (target->state != TARGET_HALTED)
593 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
597 return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
600 int arm720t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
602 target_t *target = get_current_target(cmd_ctx);
603 armv4_5_common_t *armv4_5;
604 arm7_9_common_t *arm7_9;
605 arm7tdmi_common_t *arm7tdmi;
606 arm720t_common_t *arm720t;
607 arm_jtag_t *jtag_info;
609 if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
611 command_print(cmd_ctx, "current target isn't an ARM720t target");
615 jtag_info = &arm7_9->jtag_info;
617 if (target->state != TARGET_HALTED)
619 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
623 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);