1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "replacements.h"
26 #include "embeddedice.h"
32 #include "arm7_9_common.h"
33 #include "breakpoints.h"
39 #include <sys/types.h>
44 int arm7_9_debug_entry(target_t *target);
45 int arm7_9_enable_sw_bkpts(struct target_s *target);
47 /* command handler forward declarations */
48 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
49 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
50 int handle_arm7_9_read_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
51 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
52 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
53 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
54 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
55 int handle_arm7_9_fast_writes_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
56 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
58 int arm7_9_reinit_embeddedice(target_t *target)
60 armv4_5_common_t *armv4_5 = target->arch_info;
61 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
63 breakpoint_t *breakpoint = target->breakpoints;
65 arm7_9->wp_available = 2;
69 /* mark all hardware breakpoints as unset */
72 if (breakpoint->type == BKPT_HARD)
76 breakpoint = breakpoint->next;
79 if (arm7_9->sw_bkpts_enabled && arm7_9->sw_bkpts_use_wp)
81 arm7_9->sw_bkpts_enabled = 0;
82 arm7_9_enable_sw_bkpts(target);
85 arm7_9->reinit_embeddedice = 0;
90 int arm7_9_jtag_callback(enum jtag_event event, void *priv)
92 target_t *target = priv;
93 armv4_5_common_t *armv4_5 = target->arch_info;
94 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
96 /* a test-logic reset occured
97 * the EmbeddedICE registers have been reset
98 * hardware breakpoints have been cleared
100 if (event == JTAG_TRST_ASSERTED)
102 arm7_9->reinit_embeddedice = 1;
108 int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p)
110 armv4_5_common_t *armv4_5 = target->arch_info;
111 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
113 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
118 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
123 *armv4_5_p = armv4_5;
129 int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
131 armv4_5_common_t *armv4_5 = target->arch_info;
132 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
134 if (target->state != TARGET_HALTED)
136 WARNING("target not halted");
137 return ERROR_TARGET_NOT_HALTED;
140 if (arm7_9->force_hw_bkpts)
141 breakpoint->type = BKPT_HARD;
145 WARNING("breakpoint already set");
149 if (breakpoint->type == BKPT_HARD)
151 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
152 u32 mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
153 if (!arm7_9->wp0_used)
155 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
156 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
157 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);
158 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
159 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
161 jtag_execute_queue();
162 arm7_9->wp0_used = 1;
165 else if (!arm7_9->wp1_used)
167 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
168 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
169 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);
170 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
171 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
173 jtag_execute_queue();
174 arm7_9->wp1_used = 1;
179 ERROR("BUG: no hardware comparator available");
183 else if (breakpoint->type == BKPT_SOFT)
185 if (breakpoint->length == 4)
187 target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
188 target->type->write_memory(target, breakpoint->address, 4, 1, (u8*)(&arm7_9->arm_bkpt));
192 target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
193 target->type->write_memory(target, breakpoint->address, 2, 1, (u8*)(&arm7_9->thumb_bkpt));
202 int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
204 armv4_5_common_t *armv4_5 = target->arch_info;
205 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
207 if (target->state != TARGET_HALTED)
209 WARNING("target not halted");
210 return ERROR_TARGET_NOT_HALTED;
213 if (!breakpoint->set)
215 WARNING("breakpoint not set");
219 if (breakpoint->type == BKPT_HARD)
221 if (breakpoint->set == 1)
223 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
224 jtag_execute_queue();
225 arm7_9->wp0_used = 0;
227 else if (breakpoint->set == 2)
229 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
230 jtag_execute_queue();
231 arm7_9->wp1_used = 0;
237 if (breakpoint->length == 4)
239 target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
243 target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
251 int arm7_9_add_breakpoint(struct target_s *target, u32 address, u32 length, enum breakpoint_type type)
253 armv4_5_common_t *armv4_5 = target->arch_info;
254 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
256 if (target->state != TARGET_HALTED)
258 WARNING("target not halted");
259 return ERROR_TARGET_NOT_HALTED;
262 if (arm7_9->force_hw_bkpts)
267 if ((type == BKPT_SOFT) && (arm7_9->sw_bkpts_enabled == 0))
269 INFO("sw breakpoint requested, but software breakpoints not enabled");
270 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
273 if ((type == BKPT_HARD) && (arm7_9->wp_available < 1))
275 INFO("no watchpoint unit available for hardware breakpoint");
276 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
279 if (type == BKPT_HARD)
280 arm7_9->wp_available--;
282 if ((length != 2) && (length != 4))
284 INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
285 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
291 int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
293 armv4_5_common_t *armv4_5 = target->arch_info;
294 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
296 if (target->state != TARGET_HALTED)
298 WARNING("target not halted");
299 return ERROR_TARGET_NOT_HALTED;
304 arm7_9_unset_breakpoint(target, breakpoint);
307 if (breakpoint->type == BKPT_HARD)
308 arm7_9->wp_available++;
313 int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
315 armv4_5_common_t *armv4_5 = target->arch_info;
316 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
320 mask = watchpoint->length - 1;
322 if (target->state != TARGET_HALTED)
324 WARNING("target not halted");
325 return ERROR_TARGET_NOT_HALTED;
328 if (watchpoint->rw == WPT_ACCESS)
333 if (!arm7_9->wp0_used)
335 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
336 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
337 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
338 if( watchpoint->mask != 0xffffffffu )
339 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
340 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
341 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
343 jtag_execute_queue();
345 arm7_9->wp0_used = 2;
347 else if (!arm7_9->wp1_used)
349 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
350 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
351 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
352 if( watchpoint->mask != 0xffffffffu )
353 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
354 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
355 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
357 jtag_execute_queue();
359 arm7_9->wp1_used = 2;
363 ERROR("BUG: no hardware comparator available");
370 int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
372 armv4_5_common_t *armv4_5 = target->arch_info;
373 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
375 if (target->state != TARGET_HALTED)
377 WARNING("target not halted");
378 return ERROR_TARGET_NOT_HALTED;
381 if (!watchpoint->set)
383 WARNING("breakpoint not set");
387 if (watchpoint->set == 1)
389 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
390 jtag_execute_queue();
391 arm7_9->wp0_used = 0;
393 else if (watchpoint->set == 2)
395 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
396 jtag_execute_queue();
397 arm7_9->wp1_used = 0;
404 int arm7_9_add_watchpoint(struct target_s *target, u32 address, u32 length, enum watchpoint_rw rw)
406 armv4_5_common_t *armv4_5 = target->arch_info;
407 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
409 if (target->state != TARGET_HALTED)
411 WARNING("target not halted");
412 return ERROR_TARGET_NOT_HALTED;
415 if (arm7_9->wp_available < 1)
417 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
420 if ((length != 1) && (length != 2) && (length != 4))
422 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
425 arm7_9->wp_available--;
430 int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
432 armv4_5_common_t *armv4_5 = target->arch_info;
433 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
435 if (target->state != TARGET_HALTED)
437 WARNING("target not halted");
438 return ERROR_TARGET_NOT_HALTED;
443 arm7_9_unset_watchpoint(target, watchpoint);
446 arm7_9->wp_available++;
451 int arm7_9_enable_sw_bkpts(struct target_s *target)
453 armv4_5_common_t *armv4_5 = target->arch_info;
454 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
457 if (arm7_9->sw_bkpts_enabled)
460 if (arm7_9->wp_available < 1)
462 WARNING("can't enable sw breakpoints with no watchpoint unit available");
463 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
465 arm7_9->wp_available--;
467 if (!arm7_9->wp0_used)
469 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
470 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
471 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
472 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
473 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
474 arm7_9->sw_bkpts_enabled = 1;
475 arm7_9->wp0_used = 3;
477 else if (!arm7_9->wp1_used)
479 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
480 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
481 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
482 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
483 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
484 arm7_9->sw_bkpts_enabled = 2;
485 arm7_9->wp1_used = 3;
489 ERROR("BUG: both watchpoints used, but wp_available >= 1");
493 if ((retval = jtag_execute_queue()) != ERROR_OK)
495 ERROR("error writing EmbeddedICE registers to enable sw breakpoints");
502 int arm7_9_disable_sw_bkpts(struct target_s *target)
504 armv4_5_common_t *armv4_5 = target->arch_info;
505 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
507 if (!arm7_9->sw_bkpts_enabled)
510 if (arm7_9->sw_bkpts_enabled == 1)
512 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
513 arm7_9->sw_bkpts_enabled = 0;
514 arm7_9->wp0_used = 0;
515 arm7_9->wp_available++;
517 else if (arm7_9->sw_bkpts_enabled == 2)
519 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
520 arm7_9->sw_bkpts_enabled = 0;
521 arm7_9->wp1_used = 0;
522 arm7_9->wp_available++;
528 int arm7_9_execute_sys_speed(struct target_s *target)
533 armv4_5_common_t *armv4_5 = target->arch_info;
534 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
535 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
536 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
538 /* set RESTART instruction */
539 jtag_add_end_state(TAP_RTI);
540 arm_jtag_set_instr(jtag_info, 0x4);
542 for (timeout=0; timeout<50; timeout++)
544 /* read debug status register */
545 embeddedice_read_reg(dbg_stat);
546 if ((retval = jtag_execute_queue()) != ERROR_OK)
548 if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
549 && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
555 ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
556 return ERROR_TARGET_TIMEOUT;
562 int arm7_9_execute_fast_sys_speed(struct target_s *target)
564 u8 check_value[4], check_mask[4];
566 armv4_5_common_t *armv4_5 = target->arch_info;
567 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
568 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
569 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
571 /* set RESTART instruction */
572 jtag_add_end_state(TAP_RTI);
573 arm_jtag_set_instr(jtag_info, 0x4);
575 /* check for DBGACK and SYSCOMP set (others don't care) */
576 buf_set_u32(check_value, 0, 32, 0x9);
577 buf_set_u32(check_mask, 0, 32, 0x9);
579 /* read debug status register */
580 embeddedice_read_reg_w_check(dbg_stat, check_value, check_value);
585 enum target_state arm7_9_poll(target_t *target)
588 armv4_5_common_t *armv4_5 = target->arch_info;
589 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
590 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
591 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
593 if (arm7_9->reinit_embeddedice)
595 arm7_9_reinit_embeddedice(target);
598 /* read debug status register */
599 embeddedice_read_reg(dbg_stat);
600 if ((retval = jtag_execute_queue()) != ERROR_OK)
604 case ERROR_JTAG_QUEUE_FAILED:
605 ERROR("JTAG queue failed while reading EmbeddedICE status register");
613 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
615 DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));
616 if ((target->state == TARGET_UNKNOWN))
618 WARNING("DBGACK set while target was in unknown state. Reset or initialize target before resuming");
619 target->state = TARGET_RUNNING;
621 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
623 target->state = TARGET_HALTED;
624 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
627 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
629 if (target->state == TARGET_DEBUG_RUNNING)
631 target->state = TARGET_HALTED;
632 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
635 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
640 if (target->state != TARGET_DEBUG_RUNNING)
641 target->state = TARGET_RUNNING;
644 return target->state;
647 int arm7_9_assert_reset(target_t *target)
651 DEBUG("target->state: %s", target_state_strings[target->state]);
653 if (target->state == TARGET_HALTED || target->state == TARGET_UNKNOWN)
655 /* assert SRST and TRST */
656 /* system would get ouf sync if we didn't reset test-logic, too */
657 if ((retval = jtag_add_reset(1, 1)) != ERROR_OK)
659 if (retval == ERROR_JTAG_RESET_CANT_SRST)
661 WARNING("can't assert srst");
666 ERROR("unknown error");
670 jtag_add_sleep(5000);
671 if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)
673 if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
675 WARNING("srst resets test logic, too");
676 retval = jtag_add_reset(1, 1);
682 if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)
684 if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
686 WARNING("srst resets test logic, too");
687 retval = jtag_add_reset(1, 1);
690 if (retval == ERROR_JTAG_RESET_CANT_SRST)
692 WARNING("can't assert srst");
695 else if (retval != ERROR_OK)
697 ERROR("unknown error");
703 target->state = TARGET_RESET;
704 jtag_add_sleep(50000);
706 armv4_5_invalidate_core_regs(target);
712 int arm7_9_deassert_reset(target_t *target)
714 DEBUG("target->state: %s", target_state_strings[target->state]);
716 /* deassert reset lines */
717 jtag_add_reset(0, 0);
723 int arm7_9_soft_reset_halt(struct target_s *target)
725 armv4_5_common_t *armv4_5 = target->arch_info;
726 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
727 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
730 if (target->state == TARGET_RUNNING)
732 target->type->halt(target);
735 while (buf_get_u32(dbg_stat->value, EICE_DBG_CONTROL_DBGACK, 1) == 0)
737 embeddedice_read_reg(dbg_stat);
738 jtag_execute_queue();
740 target->state = TARGET_HALTED;
742 /* all register content is now invalid */
743 armv4_5_invalidate_core_regs(target);
745 /* SVC, ARM state, IRQ and FIQ disabled */
746 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
747 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
748 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
750 /* start fetching from 0x0 */
751 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
752 armv4_5->core_cache->reg_list[15].dirty = 1;
753 armv4_5->core_cache->reg_list[15].valid = 1;
755 armv4_5->core_mode = ARMV4_5_MODE_SVC;
756 armv4_5->core_state = ARMV4_5_STATE_ARM;
758 /* reset registers */
759 for (i = 0; i <= 14; i++)
761 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, 0xffffffff);
762 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
763 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
766 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
771 int arm7_9_halt(target_t *target)
773 armv4_5_common_t *armv4_5 = target->arch_info;
774 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
775 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
777 DEBUG("target->state: %s", target_state_strings[target->state]);
779 if (target->state == TARGET_HALTED)
781 WARNING("target was already halted");
782 return ERROR_TARGET_ALREADY_HALTED;
785 if (target->state == TARGET_UNKNOWN)
787 WARNING("target was in unknown state when halt was requested");
790 if ((target->state == TARGET_RESET) && (jtag_reset_config & RESET_SRST_PULLS_TRST) && (jtag_srst))
792 ERROR("can't request a halt while in reset if nSRST pulls nTRST");
793 return ERROR_TARGET_FAILURE;
796 if (arm7_9->use_dbgrq)
798 /* program EmbeddedICE Debug Control Register to assert DBGRQ
800 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);
801 embeddedice_store_reg(dbg_ctrl);
805 /* program watchpoint unit to match on any address
807 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
808 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
809 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
810 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
813 target->debug_reason = DBG_REASON_DBGRQ;
818 int arm7_9_clear_halt(target_t *target)
820 armv4_5_common_t *armv4_5 = target->arch_info;
821 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
822 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
824 if (arm7_9->use_dbgrq)
826 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
828 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
829 embeddedice_store_reg(dbg_ctrl);
833 /* restore registers if watchpoint unit 0 was in use
835 if (arm7_9->wp0_used)
837 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
838 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
839 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
841 /* control value always has to be restored, as it was either disabled,
842 * or enabled with possibly different bits
844 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
850 int arm7_9_debug_entry(target_t *target)
855 u32 r0_thumb, pc_thumb;
858 /* get pointers to arch-specific information */
859 armv4_5_common_t *armv4_5 = target->arch_info;
860 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
861 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
862 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
864 #ifdef _DEBUG_ARM7_9_
868 if (arm7_9->pre_debug_entry)
869 arm7_9->pre_debug_entry(target);
871 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
872 * ensure that DBGRQ is cleared
874 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
875 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
876 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
877 embeddedice_store_reg(dbg_ctrl);
879 arm7_9_clear_halt(target);
881 if ((retval = jtag_execute_queue()) != ERROR_OK)
885 case ERROR_JTAG_QUEUE_FAILED:
886 ERROR("JTAG queue failed while writing EmbeddedICE control register");
894 if ((retval = arm7_9->examine_debug_reason(target)) != ERROR_OK)
898 if (target->state != TARGET_HALTED)
900 WARNING("target not halted");
901 return ERROR_TARGET_NOT_HALTED;
904 /* if the target is in Thumb state, change to ARM state */
905 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
907 DEBUG("target entered debug from Thumb state");
908 /* Entered debug from Thumb mode */
909 armv4_5->core_state = ARMV4_5_STATE_THUMB;
910 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
911 DEBUG("r0_thumb: 0x%8.8x, pc_thumb: 0x%8.8x", r0_thumb, pc_thumb);
915 DEBUG("target entered debug from ARM state");
916 /* Entered debug from ARM mode */
917 armv4_5->core_state = ARMV4_5_STATE_ARM;
920 for (i = 0; i < 16; i++)
921 context_p[i] = &context[i];
922 /* save core registers (r0 - r15 of current core mode) */
923 arm7_9->read_core_regs(target, 0xffff, context_p);
925 arm7_9->read_xpsr(target, &cpsr, 0);
927 if ((retval = jtag_execute_queue()) != ERROR_OK)
929 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
930 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
931 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
933 armv4_5->core_mode = cpsr & 0x1f;
934 DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
936 if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
938 target->state = TARGET_UNKNOWN;
939 ERROR("cpsr contains invalid mode value - communication failure");
940 return ERROR_TARGET_FAILURE;
943 if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
945 DEBUG("thumb state, applying fixups");
946 context[0] = r0_thumb;
947 context[15] = pc_thumb;
948 } else if (armv4_5->core_state == ARMV4_5_STATE_ARM)
950 /* adjust value stored by STM */
951 context[15] -= 3 * 4;
954 if ((target->debug_reason == DBG_REASON_BREAKPOINT)
955 || (target->debug_reason == DBG_REASON_SINGLESTEP)
956 || (target->debug_reason == DBG_REASON_WATCHPOINT)
957 || (target->debug_reason == DBG_REASON_WPTANDBKPT)
958 || ((target->debug_reason == DBG_REASON_DBGRQ) && (arm7_9->use_dbgrq == 0)))
959 context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
960 else if (target->debug_reason == DBG_REASON_DBGRQ)
961 context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
964 ERROR("unknown debug reason: %i", target->debug_reason);
968 for (i=0; i<=15; i++)
970 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]);
971 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
972 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
975 DEBUG("entered debug state at PC 0x%x", context[15]);
977 /* exceptions other than USR & SYS have a saved program status register */
978 if ((armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_USR) && (armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_SYS))
981 arm7_9->read_xpsr(target, &spsr, 1);
982 jtag_execute_queue();
983 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, spsr);
984 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
985 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
988 /* r0 and r15 (pc) have to be restored later */
989 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
990 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = 1;
992 if ((retval = jtag->execute_queue()) != ERROR_OK)
995 if (arm7_9->post_debug_entry)
996 arm7_9->post_debug_entry(target);
1001 int arm7_9_full_context(target_t *target)
1005 armv4_5_common_t *armv4_5 = target->arch_info;
1006 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1010 if (target->state != TARGET_HALTED)
1012 WARNING("target not halted");
1013 return ERROR_TARGET_NOT_HALTED;
1016 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1017 * SYS shares registers with User, so we don't touch SYS
1019 for(i = 0; i < 6; i++)
1026 /* check if there are invalid registers in the current mode
1028 for (j = 0; j <= 16; j++)
1030 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1038 /* change processor mode */
1039 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1040 tmp_cpsr |= armv4_5_number_to_mode(i);
1041 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1043 for (j = 0; j < 15; j++)
1045 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1047 reg_p[j] = (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value;
1049 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
1050 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1054 /* if only the PSR is invalid, mask is all zeroes */
1056 arm7_9->read_core_regs(target, mask, reg_p);
1058 /* check if the PSR has to be read */
1059 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid == 0)
1061 arm7_9->read_xpsr(target, (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1);
1062 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
1063 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1068 /* restore processor mode */
1069 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8), 0, 0);
1071 if ((retval = jtag_execute_queue()) != ERROR_OK)
1073 ERROR("JTAG failure");
1079 int arm7_9_restore_context(target_t *target)
1081 armv4_5_common_t *armv4_5 = target->arch_info;
1082 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1084 armv4_5_core_reg_t *reg_arch_info;
1085 enum armv4_5_mode current_mode = armv4_5->core_mode;
1092 if (target->state != TARGET_HALTED)
1094 WARNING("target not halted");
1095 return ERROR_TARGET_NOT_HALTED;
1098 if (arm7_9->pre_restore_context)
1099 arm7_9->pre_restore_context(target);
1101 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1102 * SYS shares registers with User, so we don't touch SYS
1104 for (i = 0; i < 6; i++)
1106 DEBUG("examining %s mode", armv4_5_mode_strings[i]);
1109 /* check if there are dirty registers in the current mode
1111 for (j = 0; j <= 16; j++)
1113 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1114 reg_arch_info = reg->arch_info;
1115 if (reg->dirty == 1)
1117 if (reg->valid == 1)
1120 DEBUG("examining dirty reg: %s", reg->name);
1121 if ((reg_arch_info->mode != ARMV4_5_MODE_ANY)
1122 && (reg_arch_info->mode != current_mode)
1123 && !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS))
1124 && !((reg_arch_info->mode == ARMV4_5_MODE_SYS) && (armv4_5->core_mode == ARMV4_5_MODE_USR)))
1127 DEBUG("require mode change");
1132 ERROR("BUG: dirty register '%s', but no valid data", reg->name);
1148 /* change processor mode */
1149 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1150 tmp_cpsr |= armv4_5_number_to_mode(i);
1151 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1152 current_mode = armv4_5_number_to_mode(i);
1155 for (j = 0; j <= 14; j++)
1157 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1158 reg_arch_info = reg->arch_info;
1161 if (reg->dirty == 1)
1163 regs[j] = buf_get_u32(reg->value, 0, 32);
1168 DEBUG("writing register %i of mode %s with value 0x%8.8x", j, armv4_5_mode_strings[i], regs[j]);
1174 arm7_9->write_core_regs(target, mask, regs);
1177 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
1178 reg_arch_info = reg->arch_info;
1179 if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
1181 DEBUG("writing SPSR of mode %i with value 0x%8.8x", i, buf_get_u32(reg->value, 0, 32));
1182 arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
1187 if ((armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 0) && (armv4_5->core_mode != current_mode))
1189 /* restore processor mode */
1192 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1193 tmp_cpsr |= armv4_5_number_to_mode(i);
1194 DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", tmp_cpsr);
1195 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1197 else if (armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 1)
1199 /* CPSR has been changed, full restore necessary */
1200 DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1201 arm7_9->write_xpsr(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), 0);
1202 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1203 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1207 DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1208 arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1209 armv4_5->core_cache->reg_list[15].dirty = 0;
1211 if (arm7_9->post_restore_context)
1212 arm7_9->post_restore_context(target);
1217 int arm7_9_restart_core(struct target_s *target)
1219 armv4_5_common_t *armv4_5 = target->arch_info;
1220 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1221 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
1223 /* set RESTART instruction */
1224 jtag_add_end_state(TAP_RTI);
1225 arm_jtag_set_instr(jtag_info, 0x4);
1227 jtag_add_runtest(1, TAP_RTI);
1228 if ((jtag_execute_queue()) != ERROR_OK)
1236 void arm7_9_enable_watchpoints(struct target_s *target)
1238 watchpoint_t *watchpoint = target->watchpoints;
1242 if (watchpoint->set == 0)
1243 arm7_9_set_watchpoint(target, watchpoint);
1244 watchpoint = watchpoint->next;
1248 void arm7_9_enable_breakpoints(struct target_s *target)
1250 breakpoint_t *breakpoint = target->breakpoints;
1252 /* set any pending breakpoints */
1255 if (breakpoint->set == 0)
1256 arm7_9_set_breakpoint(target, breakpoint);
1257 breakpoint = breakpoint->next;
1261 void arm7_9_disable_bkpts_and_wpts(struct target_s *target)
1263 breakpoint_t *breakpoint = target->breakpoints;
1264 watchpoint_t *watchpoint = target->watchpoints;
1266 /* set any pending breakpoints */
1269 if (breakpoint->set != 0)
1270 arm7_9_unset_breakpoint(target, breakpoint);
1271 breakpoint = breakpoint->next;
1276 if (watchpoint->set != 0)
1277 arm7_9_unset_watchpoint(target, watchpoint);
1278 watchpoint = watchpoint->next;
1282 int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
1284 armv4_5_common_t *armv4_5 = target->arch_info;
1285 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1286 breakpoint_t *breakpoint = target->breakpoints;
1287 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1291 if (target->state != TARGET_HALTED)
1293 WARNING("target not halted");
1294 return ERROR_TARGET_NOT_HALTED;
1297 if (!debug_execution)
1299 target_free_all_working_areas(target);
1302 /* current = 1: continue on current pc, otherwise continue at <address> */
1304 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1306 /* the front-end may request us not to handle breakpoints */
1307 if (handle_breakpoints)
1309 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1311 DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
1312 arm7_9_unset_breakpoint(target, breakpoint);
1314 DEBUG("enable single-step");
1315 arm7_9->enable_single_step(target);
1317 target->debug_reason = DBG_REASON_SINGLESTEP;
1319 arm7_9_restore_context(target);
1321 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1322 arm7_9->branch_resume(target);
1323 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1325 arm7_9->branch_resume_thumb(target);
1329 ERROR("unhandled core state");
1333 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1334 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1335 arm7_9_execute_sys_speed(target);
1337 DEBUG("disable single-step");
1338 arm7_9->disable_single_step(target);
1340 arm7_9_debug_entry(target);
1341 DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1343 DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
1344 arm7_9_set_breakpoint(target, breakpoint);
1348 /* enable any pending breakpoints and watchpoints */
1349 arm7_9_enable_breakpoints(target);
1350 arm7_9_enable_watchpoints(target);
1352 arm7_9_restore_context(target);
1354 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1356 arm7_9->branch_resume(target);
1358 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1360 arm7_9->branch_resume_thumb(target);
1364 ERROR("unhandled core state");
1368 /* deassert DBGACK and INTDIS */
1369 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1370 /* INTDIS only when we really resume, not during debug execution */
1371 if (!debug_execution)
1372 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);
1373 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1375 arm7_9_restart_core(target);
1377 target->debug_reason = DBG_REASON_NOTHALTED;
1379 if (!debug_execution)
1381 /* registers are now invalid */
1382 armv4_5_invalidate_core_regs(target);
1383 target->state = TARGET_RUNNING;
1384 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1388 target->state = TARGET_DEBUG_RUNNING;
1389 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1392 DEBUG("target resumed");
1397 void arm7_9_enable_eice_step(target_t *target)
1399 armv4_5_common_t *armv4_5 = target->arch_info;
1400 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1402 /* setup an inverse breakpoint on the current PC
1403 * - comparator 1 matches the current address
1404 * - rangeout from comparator 1 is connected to comparator 0 rangein
1405 * - comparator 0 matches any address, as long as rangein is low */
1406 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1407 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1408 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
1409 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0x77);
1410 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1411 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
1412 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
1413 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
1414 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xf7);
1417 void arm7_9_disable_eice_step(target_t *target)
1419 armv4_5_common_t *armv4_5 = target->arch_info;
1420 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1422 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
1423 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
1424 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
1425 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
1426 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE]);
1427 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK]);
1428 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK]);
1429 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK]);
1430 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
1433 int arm7_9_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
1435 armv4_5_common_t *armv4_5 = target->arch_info;
1436 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1437 breakpoint_t *breakpoint = target->breakpoints;
1439 if (target->state != TARGET_HALTED)
1441 WARNING("target not halted");
1442 return ERROR_TARGET_NOT_HALTED;
1445 /* current = 1: continue on current pc, otherwise continue at <address> */
1447 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1449 /* the front-end may request us not to handle breakpoints */
1450 if (handle_breakpoints)
1451 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1452 arm7_9_unset_breakpoint(target, breakpoint);
1454 target->debug_reason = DBG_REASON_SINGLESTEP;
1456 arm7_9_restore_context(target);
1458 arm7_9->enable_single_step(target);
1460 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1462 arm7_9->branch_resume(target);
1464 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1466 arm7_9->branch_resume_thumb(target);
1470 ERROR("unhandled core state");
1474 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1476 arm7_9_execute_sys_speed(target);
1477 arm7_9->disable_single_step(target);
1479 /* registers are now invalid */
1480 armv4_5_invalidate_core_regs(target);
1482 arm7_9_debug_entry(target);
1484 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1487 arm7_9_set_breakpoint(target, breakpoint);
1489 DEBUG("target stepped");
1495 int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
1499 armv4_5_common_t *armv4_5 = target->arch_info;
1500 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1501 enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1503 if ((num < 0) || (num > 16))
1504 return ERROR_INVALID_ARGUMENTS;
1506 if ((mode != ARMV4_5_MODE_ANY)
1507 && (mode != armv4_5->core_mode)
1508 && (reg_mode != ARMV4_5_MODE_ANY))
1512 /* change processor mode */
1513 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1515 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1518 if ((num >= 0) && (num <= 15))
1520 /* read a normal core register */
1521 reg_p[num] = (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).value;
1523 arm7_9->read_core_regs(target, 1 << num, reg_p);
1527 /* read a program status register
1528 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
1530 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1531 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1533 arm7_9->read_xpsr(target, (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).value, spsr);
1536 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1537 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1539 if ((mode != ARMV4_5_MODE_ANY)
1540 && (mode != armv4_5->core_mode)
1541 && (reg_mode != ARMV4_5_MODE_ANY)) {
1542 /* restore processor mode */
1543 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8), 0, 0);
1546 if ((retval = jtag_execute_queue()) != ERROR_OK)
1548 ERROR("JTAG failure");
1556 int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value)
1560 armv4_5_common_t *armv4_5 = target->arch_info;
1561 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1562 enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1564 if ((num < 0) || (num > 16))
1565 return ERROR_INVALID_ARGUMENTS;
1567 if ((mode != ARMV4_5_MODE_ANY)
1568 && (mode != armv4_5->core_mode)
1569 && (reg_mode != ARMV4_5_MODE_ANY)) {
1572 /* change processor mode */
1573 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1575 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1578 if ((num >= 0) && (num <= 15))
1580 /* write a normal core register */
1583 arm7_9->write_core_regs(target, 1 << num, reg);
1587 /* write a program status register
1588 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
1590 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1591 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1593 arm7_9->write_xpsr(target, value, spsr);
1596 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1597 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1599 if ((mode != ARMV4_5_MODE_ANY)
1600 && (mode != armv4_5->core_mode)
1601 && (reg_mode != ARMV4_5_MODE_ANY)) {
1602 /* restore processor mode */
1603 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8), 0, 0);
1606 if ((retval = jtag_execute_queue()) != ERROR_OK)
1608 ERROR("JTAG failure");
1616 int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1618 armv4_5_common_t *armv4_5 = target->arch_info;
1619 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1623 int num_accesses = 0;
1624 int thisrun_accesses;
1630 DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1632 if (target->state != TARGET_HALTED)
1634 WARNING("target not halted");
1635 return ERROR_TARGET_NOT_HALTED;
1638 /* sanitize arguments */
1639 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1640 return ERROR_INVALID_ARGUMENTS;
1642 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1643 return ERROR_TARGET_UNALIGNED_ACCESS;
1645 for (i = 0; i < 16; i++)
1650 /* load the base register with the address of the first word */
1652 arm7_9->write_core_regs(target, 0x1, reg);
1657 while (num_accesses < count)
1660 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1661 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1663 arm7_9->load_word_regs(target, reg_list);
1664 arm7_9_execute_sys_speed(target);
1666 arm7_9->read_core_regs(target, reg_list, reg_p);
1667 jtag_execute_queue();
1669 for (i = 1; i <= thisrun_accesses; i++)
1673 target_buffer_set_u32(target, buffer, reg[i]);
1676 num_accesses += thisrun_accesses;
1680 while (num_accesses < count)
1683 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1684 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1686 for (i = 1; i <= thisrun_accesses; i++)
1690 arm7_9->load_hword_reg(target, i);
1691 arm7_9_execute_sys_speed(target);
1694 arm7_9->read_core_regs(target, reg_list, reg_p);
1695 jtag_execute_queue();
1697 for (i = 1; i <= thisrun_accesses; i++)
1699 target_buffer_set_u16(target, buffer, reg[i]);
1702 num_accesses += thisrun_accesses;
1706 while (num_accesses < count)
1709 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1710 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1712 for (i = 1; i <= thisrun_accesses; i++)
1716 arm7_9->load_byte_reg(target, i);
1717 arm7_9_execute_sys_speed(target);
1720 arm7_9->read_core_regs(target, reg_list, reg_p);
1721 jtag_execute_queue();
1723 for (i = 1; i <= thisrun_accesses; i++)
1725 *(buffer++) = reg[i] & 0xff;
1727 num_accesses += thisrun_accesses;
1731 ERROR("BUG: we shouldn't get here");
1736 for (i=0; i<=last_reg; i++)
1737 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
1739 arm7_9->read_xpsr(target, &cpsr, 0);
1740 if ((retval = jtag_execute_queue()) != ERROR_OK)
1742 ERROR("JTAG error while reading cpsr");
1746 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
1748 ERROR("memory read caused data abort");
1750 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8), 0, 0);
1752 return ERROR_TARGET_DATA_ABORT;
1758 int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1760 armv4_5_common_t *armv4_5 = target->arch_info;
1761 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1764 int num_accesses = 0;
1765 int thisrun_accesses;
1771 DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1773 if (target->state != TARGET_HALTED)
1775 WARNING("target not halted");
1776 return ERROR_TARGET_NOT_HALTED;
1779 /* sanitize arguments */
1780 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1781 return ERROR_INVALID_ARGUMENTS;
1783 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1784 return ERROR_TARGET_UNALIGNED_ACCESS;
1786 /* load the base register with the address of the first word */
1788 arm7_9->write_core_regs(target, 0x1, reg);
1793 while (num_accesses < count)
1796 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1797 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1799 for (i = 1; i <= thisrun_accesses; i++)
1803 reg[i] = target_buffer_get_u32(target, buffer);
1807 arm7_9->write_core_regs(target, reg_list, reg);
1809 arm7_9->store_word_regs(target, reg_list);
1811 /* fast memory writes are only safe when the target is running
1812 * from a sufficiently high clock (32 kHz is usually too slow)
1814 if (arm7_9->fast_memory_writes)
1815 arm7_9_execute_fast_sys_speed(target);
1817 arm7_9_execute_sys_speed(target);
1819 num_accesses += thisrun_accesses;
1823 while (num_accesses < count)
1826 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1827 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1829 for (i = 1; i <= thisrun_accesses; i++)
1833 reg[i] = target_buffer_get_u16(target, buffer) & 0xffff;
1837 arm7_9->write_core_regs(target, reg_list, reg);
1839 for (i = 1; i <= thisrun_accesses; i++)
1841 arm7_9->store_hword_reg(target, i);
1843 /* fast memory writes are only safe when the target is running
1844 * from a sufficiently high clock (32 kHz is usually too slow)
1846 if (arm7_9->fast_memory_writes)
1847 arm7_9_execute_fast_sys_speed(target);
1849 arm7_9_execute_sys_speed(target);
1852 num_accesses += thisrun_accesses;
1856 while (num_accesses < count)
1859 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1860 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1862 for (i = 1; i <= thisrun_accesses; i++)
1866 reg[i] = *buffer++ & 0xff;
1869 arm7_9->write_core_regs(target, reg_list, reg);
1871 for (i = 1; i <= thisrun_accesses; i++)
1873 arm7_9->store_byte_reg(target, i);
1874 /* fast memory writes are only safe when the target is running
1875 * from a sufficiently high clock (32 kHz is usually too slow)
1877 if (arm7_9->fast_memory_writes)
1878 arm7_9_execute_fast_sys_speed(target);
1880 arm7_9_execute_sys_speed(target);
1883 num_accesses += thisrun_accesses;
1887 ERROR("BUG: we shouldn't get here");
1892 if ((retval = jtag_execute_queue()) != ERROR_OK)
1894 ERROR("JTAG error while writing target memory");
1898 for (i=0; i<=last_reg; i++)
1899 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
1901 arm7_9->read_xpsr(target, &cpsr, 0);
1902 if ((retval = jtag_execute_queue()) != ERROR_OK)
1904 ERROR("JTAG error while reading cpsr");
1908 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
1910 ERROR("memory write caused data abort");
1912 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8), 0, 0);
1914 return ERROR_TARGET_DATA_ABORT;
1920 int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
1922 armv4_5_common_t *armv4_5 = target->arch_info;
1923 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1924 enum armv4_5_state core_state = armv4_5->core_state;
1925 u32 r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
1926 u32 r1 = buf_get_u32(armv4_5->core_cache->reg_list[1].value, 0, 32);
1927 u32 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1932 /* MRC TST BNE MRC STR B */
1933 0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9
1936 if (!arm7_9->dcc_downloads)
1937 return target->type->write_memory(target, address, 4, count, buffer);
1939 /* regrab previously allocated working_area, or allocate a new one */
1940 if (!arm7_9->dcc_working_area)
1942 /* make sure we have a working area */
1943 if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
1945 INFO("no working area available, falling back to memory writes");
1946 return target->type->write_memory(target, address, 4, count, buffer);
1949 /* write DCC code to working area */
1950 target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, (u8*)dcc_code);
1953 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address);
1954 armv4_5->core_cache->reg_list[0].valid = 1;
1955 armv4_5->core_cache->reg_list[0].dirty = 1;
1956 armv4_5->core_state = ARMV4_5_STATE_ARM;
1958 arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
1960 for (i = 0; i < count; i++)
1962 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], target_buffer_get_u32(target, buffer));
1966 target->type->halt(target);
1968 while (target->state != TARGET_HALTED)
1969 target->type->poll(target);
1971 /* restore target state */
1972 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, r0);
1973 armv4_5->core_cache->reg_list[0].valid = 1;
1974 armv4_5->core_cache->reg_list[0].dirty = 1;
1975 buf_set_u32(armv4_5->core_cache->reg_list[1].value, 0, 32, r1);
1976 armv4_5->core_cache->reg_list[1].valid = 1;
1977 armv4_5->core_cache->reg_list[1].dirty = 1;
1978 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, pc);
1979 armv4_5->core_cache->reg_list[15].valid = 1;
1980 armv4_5->core_cache->reg_list[15].dirty = 1;
1981 armv4_5->core_state = core_state;
1986 int arm7_9_register_commands(struct command_context_s *cmd_ctx)
1988 command_t *arm7_9_cmd;
1990 arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, NULL);
1992 register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register <value> <not cpsr|spsr>");
1993 register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> <rotate> <not cpsr|spsr>");
1995 register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register <num> <mode> <value>");
1997 register_command(cmd_ctx, arm7_9_cmd, "sw_bkpts", handle_arm7_9_sw_bkpts_command, COMMAND_EXEC, "support for software breakpoints <enable|disable>");
1998 register_command(cmd_ctx, arm7_9_cmd, "force_hw_bkpts", handle_arm7_9_force_hw_bkpts_command, COMMAND_EXEC, "use hardware breakpoints for all breakpoints (disables sw breakpoint support) <enable|disable>");
1999 register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command,
2000 COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable|disable>");
2001 register_command(cmd_ctx, arm7_9_cmd, "fast_writes", handle_arm7_9_fast_writes_command,
2002 COMMAND_ANY, "use fast memory writes instead of slower but potentially unsafe slow writes <enable|disable>");
2003 register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", handle_arm7_9_dcc_downloads_command,
2004 COMMAND_ANY, "use DCC downloads for larger memory writes <enable|disable>");
2006 armv4_5_register_commands(cmd_ctx);
2011 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2016 target_t *target = get_current_target(cmd_ctx);
2017 armv4_5_common_t *armv4_5;
2018 arm7_9_common_t *arm7_9;
2020 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2022 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2026 if (target->state != TARGET_HALTED)
2028 command_print(cmd_ctx, "can't write registers while running");
2034 command_print(cmd_ctx, "usage: write_xpsr <value> <not cpsr|spsr>");
2038 value = strtoul(args[0], NULL, 0);
2039 spsr = strtol(args[1], NULL, 0);
2041 arm7_9->write_xpsr(target, value, spsr);
2042 if ((retval = jtag_execute_queue()) != ERROR_OK)
2044 ERROR("JTAG error while writing to xpsr");
2051 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2057 target_t *target = get_current_target(cmd_ctx);
2058 armv4_5_common_t *armv4_5;
2059 arm7_9_common_t *arm7_9;
2061 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2063 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2067 if (target->state != TARGET_HALTED)
2069 command_print(cmd_ctx, "can't write registers while running");
2075 command_print(cmd_ctx, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr|spsr>");
2079 value = strtoul(args[0], NULL, 0);
2080 rotate = strtol(args[1], NULL, 0);
2081 spsr = strtol(args[2], NULL, 0);
2083 arm7_9->write_xpsr_im8(target, value, rotate, spsr);
2084 if ((retval = jtag_execute_queue()) != ERROR_OK)
2086 ERROR("JTAG error while writing 8-bit immediate to xpsr");
2093 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2098 target_t *target = get_current_target(cmd_ctx);
2099 armv4_5_common_t *armv4_5;
2100 arm7_9_common_t *arm7_9;
2102 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2104 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2108 if (target->state != TARGET_HALTED)
2110 command_print(cmd_ctx, "can't write registers while running");
2116 command_print(cmd_ctx, "usage: write_core_reg <num> <mode> <value>");
2120 num = strtol(args[0], NULL, 0);
2121 mode = strtoul(args[1], NULL, 0);
2122 value = strtoul(args[2], NULL, 0);
2124 arm7_9_write_core_reg(target, num, mode, value);
2129 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2131 target_t *target = get_current_target(cmd_ctx);
2132 armv4_5_common_t *armv4_5;
2133 arm7_9_common_t *arm7_9;
2135 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2137 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2143 command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2147 if (strcmp("enable", args[0]) == 0)
2149 if (arm7_9->sw_bkpts_use_wp)
2151 arm7_9_enable_sw_bkpts(target);
2155 arm7_9->sw_bkpts_enabled = 1;
2158 else if (strcmp("disable", args[0]) == 0)
2160 if (arm7_9->sw_bkpts_use_wp)
2162 arm7_9_disable_sw_bkpts(target);
2166 arm7_9->sw_bkpts_enabled = 0;
2171 command_print(cmd_ctx, "usage: arm7_9 sw_bkpts <enable|disable>");
2174 command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2179 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2181 target_t *target = get_current_target(cmd_ctx);
2182 armv4_5_common_t *armv4_5;
2183 arm7_9_common_t *arm7_9;
2185 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2187 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2191 if ((argc >= 1) && (strcmp("enable", args[0]) == 0))
2193 arm7_9->force_hw_bkpts = 1;
2194 if (arm7_9->sw_bkpts_use_wp)
2196 arm7_9_disable_sw_bkpts(target);
2199 else if ((argc >= 1) && (strcmp("disable", args[0]) == 0))
2201 arm7_9->force_hw_bkpts = 0;
2205 command_print(cmd_ctx, "usage: arm7_9 force_hw_bkpts <enable|disable>");
2208 command_print(cmd_ctx, "force hardware breakpoints %s", (arm7_9->force_hw_bkpts) ? "enabled" : "disabled");
2213 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2215 target_t *target = get_current_target(cmd_ctx);
2216 armv4_5_common_t *armv4_5;
2217 arm7_9_common_t *arm7_9;
2219 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2221 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2227 if (strcmp("enable", args[0]) == 0)
2229 arm7_9->use_dbgrq = 1;
2231 else if (strcmp("disable", args[0]) == 0)
2233 arm7_9->use_dbgrq = 0;
2237 command_print(cmd_ctx, "usage: arm7_9 dbgrq <enable|disable>");
2241 command_print(cmd_ctx, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
2246 int handle_arm7_9_fast_writes_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2248 target_t *target = get_current_target(cmd_ctx);
2249 armv4_5_common_t *armv4_5;
2250 arm7_9_common_t *arm7_9;
2252 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2254 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2260 if (strcmp("enable", args[0]) == 0)
2262 arm7_9->fast_memory_writes = 1;
2264 else if (strcmp("disable", args[0]) == 0)
2266 arm7_9->fast_memory_writes = 0;
2270 command_print(cmd_ctx, "usage: arm7_9 fast_writes <enable|disable>");
2274 command_print(cmd_ctx, "fast memory writes are %s", (arm7_9->fast_memory_writes) ? "enabled" : "disabled");
2279 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2281 target_t *target = get_current_target(cmd_ctx);
2282 armv4_5_common_t *armv4_5;
2283 arm7_9_common_t *arm7_9;
2285 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2287 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2293 if (strcmp("enable", args[0]) == 0)
2295 arm7_9->dcc_downloads = 1;
2297 else if (strcmp("disable", args[0]) == 0)
2299 arm7_9->dcc_downloads = 0;
2303 command_print(cmd_ctx, "usage: arm7_9 dcc_downloads <enable|disable>");
2307 command_print(cmd_ctx, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");
2312 int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
2314 armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common;
2316 arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
2318 arm_jtag_setup_connection(&arm7_9->jtag_info);
2319 arm7_9->wp_available = 2;
2320 arm7_9->wp0_used = 0;
2321 arm7_9->wp1_used = 0;
2322 arm7_9->force_hw_bkpts = 0;
2323 arm7_9->use_dbgrq = 0;
2324 arm7_9->has_etm = 0;
2326 arm7_9->reinit_embeddedice = 0;
2328 arm7_9->dcc_working_area = NULL;
2330 arm7_9->fast_memory_writes = 0;
2331 arm7_9->dcc_downloads = 0;
2333 jtag_register_event_callback(arm7_9_jtag_callback, target);
2335 armv4_5->arch_info = arm7_9;
2336 armv4_5->read_core_reg = arm7_9_read_core_reg;
2337 armv4_5->write_core_reg = arm7_9_write_core_reg;
2338 armv4_5->full_context = arm7_9_full_context;
2340 armv4_5_init_arch_info(target, armv4_5);