1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2007,2008 Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
27 #include "replacements.h"
29 #include "embeddedice.h"
31 #include "target_request.h"
36 #include "arm7_9_common.h"
37 #include "breakpoints.h"
43 #include <sys/types.h>
48 int arm7_9_debug_entry(target_t *target);
49 int arm7_9_enable_sw_bkpts(struct target_s *target);
51 /* command handler forward declarations */
52 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
53 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
54 int handle_arm7_9_read_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
55 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
56 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
57 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
58 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
59 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
60 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
61 int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
63 int arm7_9_reinit_embeddedice(target_t *target)
65 armv4_5_common_t *armv4_5 = target->arch_info;
66 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
68 breakpoint_t *breakpoint = target->breakpoints;
70 arm7_9->wp_available = 2;
74 /* mark all hardware breakpoints as unset */
77 if (breakpoint->type == BKPT_HARD)
81 breakpoint = breakpoint->next;
84 if (arm7_9->sw_bkpts_enabled && arm7_9->sw_bkpts_use_wp)
86 arm7_9->sw_bkpts_enabled = 0;
87 arm7_9_enable_sw_bkpts(target);
93 /* set things up after a reset / on startup */
94 int arm7_9_setup(target_t *target)
96 /* a test-logic reset have occured
97 * the EmbeddedICE registers have been reset
98 * hardware breakpoints have been cleared
100 return arm7_9_reinit_embeddedice(target);
103 int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p)
105 armv4_5_common_t *armv4_5 = target->arch_info;
106 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
108 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
113 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
118 *armv4_5_p = armv4_5;
124 int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
126 armv4_5_common_t *armv4_5 = target->arch_info;
127 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
129 if (target->state != TARGET_HALTED)
131 LOG_WARNING("target not halted");
132 return ERROR_TARGET_NOT_HALTED;
135 if (arm7_9->force_hw_bkpts)
136 breakpoint->type = BKPT_HARD;
140 LOG_WARNING("breakpoint already set");
144 if (breakpoint->type == BKPT_HARD)
146 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
147 u32 mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
148 if (!arm7_9->wp0_used)
150 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
151 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
152 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);
153 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
154 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
156 jtag_execute_queue();
157 arm7_9->wp0_used = 1;
160 else if (!arm7_9->wp1_used)
162 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
163 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
164 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);
165 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
166 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
168 jtag_execute_queue();
169 arm7_9->wp1_used = 1;
174 LOG_ERROR("BUG: no hardware comparator available");
178 else if (breakpoint->type == BKPT_SOFT)
180 if (breakpoint->length == 4)
182 u32 verify = 0xffffffff;
183 /* keep the original instruction in target endianness */
184 target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
185 /* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
186 target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt);
188 target->type->read_memory(target, breakpoint->address, 4, 1, (u8 *)&verify);
189 if (verify != arm7_9->arm_bkpt)
191 LOG_ERROR("Unable to set 32 bit software breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
198 /* keep the original instruction in target endianness */
199 target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
200 /* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
201 target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt);
203 target->type->read_memory(target, breakpoint->address, 2, 1, (u8 *)&verify);
204 if (verify != arm7_9->thumb_bkpt)
206 LOG_ERROR("Unable to set thumb software breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
217 int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
219 armv4_5_common_t *armv4_5 = target->arch_info;
220 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
222 if (target->state != TARGET_HALTED)
224 LOG_WARNING("target not halted");
225 return ERROR_TARGET_NOT_HALTED;
228 if (!breakpoint->set)
230 LOG_WARNING("breakpoint not set");
234 if (breakpoint->type == BKPT_HARD)
236 if (breakpoint->set == 1)
238 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
239 jtag_execute_queue();
240 arm7_9->wp0_used = 0;
242 else if (breakpoint->set == 2)
244 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
245 jtag_execute_queue();
246 arm7_9->wp1_used = 0;
252 /* restore original instruction (kept in target endianness) */
253 if (breakpoint->length == 4)
256 /* check that user program as not modified breakpoint instruction */
257 target->type->read_memory(target, breakpoint->address, 4, 1, (u8*)¤t_instr);
258 if (current_instr==arm7_9->arm_bkpt)
259 target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
264 /* check that user program as not modified breakpoint instruction */
265 target->type->read_memory(target, breakpoint->address, 2, 1, (u8*)¤t_instr);
266 if (current_instr==arm7_9->thumb_bkpt)
267 target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
275 int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
277 armv4_5_common_t *armv4_5 = target->arch_info;
278 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
280 if (target->state != TARGET_HALTED)
282 LOG_WARNING("target not halted");
283 return ERROR_TARGET_NOT_HALTED;
286 if (arm7_9->force_hw_bkpts)
288 LOG_DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint->address);
289 breakpoint->type = BKPT_HARD;
292 if ((breakpoint->type == BKPT_SOFT) && (arm7_9->sw_bkpts_enabled == 0))
294 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
295 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
298 if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1))
300 LOG_INFO("no watchpoint unit available for hardware breakpoint");
301 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
304 if ((breakpoint->length != 2) && (breakpoint->length != 4))
306 LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
307 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
310 if (breakpoint->type == BKPT_HARD)
311 arm7_9->wp_available--;
316 int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
318 armv4_5_common_t *armv4_5 = target->arch_info;
319 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
321 if (target->state != TARGET_HALTED)
323 LOG_WARNING("target not halted");
324 return ERROR_TARGET_NOT_HALTED;
329 arm7_9_unset_breakpoint(target, breakpoint);
332 if (breakpoint->type == BKPT_HARD)
333 arm7_9->wp_available++;
338 int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
340 armv4_5_common_t *armv4_5 = target->arch_info;
341 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
345 mask = watchpoint->length - 1;
347 if (target->state != TARGET_HALTED)
349 LOG_WARNING("target not halted");
350 return ERROR_TARGET_NOT_HALTED;
353 if (watchpoint->rw == WPT_ACCESS)
358 if (!arm7_9->wp0_used)
360 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
361 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
362 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
363 if( watchpoint->mask != 0xffffffffu )
364 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
365 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
366 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
368 jtag_execute_queue();
370 arm7_9->wp0_used = 2;
372 else if (!arm7_9->wp1_used)
374 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
375 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
376 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
377 if( watchpoint->mask != 0xffffffffu )
378 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
379 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
380 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
382 jtag_execute_queue();
384 arm7_9->wp1_used = 2;
388 LOG_ERROR("BUG: no hardware comparator available");
395 int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
397 armv4_5_common_t *armv4_5 = target->arch_info;
398 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
400 if (target->state != TARGET_HALTED)
402 LOG_WARNING("target not halted");
403 return ERROR_TARGET_NOT_HALTED;
406 if (!watchpoint->set)
408 LOG_WARNING("breakpoint not set");
412 if (watchpoint->set == 1)
414 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
415 jtag_execute_queue();
416 arm7_9->wp0_used = 0;
418 else if (watchpoint->set == 2)
420 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
421 jtag_execute_queue();
422 arm7_9->wp1_used = 0;
429 int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
431 armv4_5_common_t *armv4_5 = target->arch_info;
432 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
434 if (target->state != TARGET_HALTED)
436 LOG_WARNING("target not halted");
437 return ERROR_TARGET_NOT_HALTED;
440 if (arm7_9->wp_available < 1)
442 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
445 if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
447 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
450 arm7_9->wp_available--;
455 int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
457 armv4_5_common_t *armv4_5 = target->arch_info;
458 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
460 if (target->state != TARGET_HALTED)
462 LOG_WARNING("target not halted");
463 return ERROR_TARGET_NOT_HALTED;
468 arm7_9_unset_watchpoint(target, watchpoint);
471 arm7_9->wp_available++;
476 int arm7_9_enable_sw_bkpts(struct target_s *target)
478 armv4_5_common_t *armv4_5 = target->arch_info;
479 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
482 if (arm7_9->sw_bkpts_enabled)
485 if (arm7_9->wp_available < 1)
487 LOG_WARNING("can't enable sw breakpoints with no watchpoint unit available");
488 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
490 arm7_9->wp_available--;
492 if (!arm7_9->wp0_used)
494 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
495 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
496 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
497 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
498 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
499 arm7_9->sw_bkpts_enabled = 1;
500 arm7_9->wp0_used = 3;
502 else if (!arm7_9->wp1_used)
504 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
505 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
506 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
507 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
508 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
509 arm7_9->sw_bkpts_enabled = 2;
510 arm7_9->wp1_used = 3;
514 LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
518 if ((retval = jtag_execute_queue()) != ERROR_OK)
520 LOG_ERROR("error writing EmbeddedICE registers to enable sw breakpoints");
527 int arm7_9_disable_sw_bkpts(struct target_s *target)
529 armv4_5_common_t *armv4_5 = target->arch_info;
530 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
532 if (!arm7_9->sw_bkpts_enabled)
535 if (arm7_9->sw_bkpts_enabled == 1)
537 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
538 arm7_9->sw_bkpts_enabled = 0;
539 arm7_9->wp0_used = 0;
540 arm7_9->wp_available++;
542 else if (arm7_9->sw_bkpts_enabled == 2)
544 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
545 arm7_9->sw_bkpts_enabled = 0;
546 arm7_9->wp1_used = 0;
547 arm7_9->wp_available++;
553 int arm7_9_execute_sys_speed(struct target_s *target)
558 armv4_5_common_t *armv4_5 = target->arch_info;
559 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
560 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
561 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
563 /* set RESTART instruction */
564 jtag_add_end_state(TAP_RTI);
565 if (arm7_9->need_bypass_before_restart) {
566 arm7_9->need_bypass_before_restart = 0;
567 arm_jtag_set_instr(jtag_info, 0xf, NULL);
569 arm_jtag_set_instr(jtag_info, 0x4, NULL);
571 for (timeout=0; timeout<50; timeout++)
573 /* read debug status register */
574 embeddedice_read_reg(dbg_stat);
575 if ((retval = jtag_execute_queue()) != ERROR_OK)
577 if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
578 && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
584 LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
585 return ERROR_TARGET_TIMEOUT;
591 int arm7_9_execute_fast_sys_speed(struct target_s *target)
594 static u8 check_value[4], check_mask[4];
596 armv4_5_common_t *armv4_5 = target->arch_info;
597 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
598 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
599 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
601 /* set RESTART instruction */
602 jtag_add_end_state(TAP_RTI);
603 if (arm7_9->need_bypass_before_restart) {
604 arm7_9->need_bypass_before_restart = 0;
605 arm_jtag_set_instr(jtag_info, 0xf, NULL);
607 arm_jtag_set_instr(jtag_info, 0x4, NULL);
611 /* check for DBGACK and SYSCOMP set (others don't care) */
613 /* NB! These are constants that must be available until after next jtag_execute() and
614 we evaluate the values upon first execution in lieu of setting up these constants
617 buf_set_u32(check_value, 0, 32, 0x9);
618 buf_set_u32(check_mask, 0, 32, 0x9);
622 /* read debug status register */
623 embeddedice_read_reg_w_check(dbg_stat, check_value, check_value);
628 int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer)
630 armv4_5_common_t *armv4_5 = target->arch_info;
631 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
632 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
636 data = malloc(size * (sizeof(u32)));
638 embeddedice_receive(jtag_info, data, size);
640 for (i = 0; i < size; i++)
642 h_u32_to_le(buffer + (i * 4), data[i]);
650 int arm7_9_handle_target_request(void *priv)
652 target_t *target = priv;
653 if (!target->type->examined)
655 armv4_5_common_t *armv4_5 = target->arch_info;
656 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
657 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
658 reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
661 if (!target->dbg_msg_enabled)
664 if (target->state == TARGET_RUNNING)
666 /* read DCC control register */
667 embeddedice_read_reg(dcc_control);
668 jtag_execute_queue();
671 if (buf_get_u32(dcc_control->value, 1, 1) == 1)
675 embeddedice_receive(jtag_info, &request, 1);
676 target_request(target, request);
683 int arm7_9_poll(target_t *target)
686 armv4_5_common_t *armv4_5 = target->arch_info;
687 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
688 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
690 /* read debug status register */
691 embeddedice_read_reg(dbg_stat);
692 if ((retval = jtag_execute_queue()) != ERROR_OK)
697 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
699 /* LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));*/
700 if (target->state == TARGET_UNKNOWN)
702 target->state = TARGET_RUNNING;
703 LOG_WARNING("DBGACK set while target was in unknown state. Reset or initialize target.");
705 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
708 if (target->state == TARGET_RESET)
710 if (target->reset_halt)
712 if ((jtag_reset_config & RESET_SRST_PULLS_TRST)==0)
719 target->state = TARGET_HALTED;
721 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
726 reg_t *reg = register_get_by_name(target->reg_cache, "pc", 1);
727 u32 t=*((u32 *)reg->value);
730 LOG_ERROR("PC was not 0. Does this target need srst_pulls_trst?");
734 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
736 if (target->state == TARGET_DEBUG_RUNNING)
738 target->state = TARGET_HALTED;
739 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
742 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
744 if (target->state != TARGET_HALTED)
746 LOG_WARNING("DBGACK set, but the target did not end up in the halted stated %d", target->state);
751 if (target->state != TARGET_DEBUG_RUNNING)
752 target->state = TARGET_RUNNING;
759 Some -S targets (ARM966E-S in the STR912 isn't affected, ARM926EJ-S
760 in the LPC3180 and AT91SAM9260 is affected) completely stop the JTAG clock
761 while the core is held in reset(SRST). It isn't possible to program the halt
762 condition once reset was asserted, hence a hook that allows the target to set
763 up its reset-halt condition prior to asserting reset.
766 int arm7_9_assert_reset(target_t *target)
768 armv4_5_common_t *armv4_5 = target->arch_info;
769 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
770 LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
772 if (!(jtag_reset_config & RESET_HAS_SRST))
774 LOG_ERROR("Can't assert SRST");
778 if (target->reset_halt)
781 * Some targets do not support communication while SRST is asserted. We need to
782 * set up the reset vector catch here.
784 * If TRST is asserted, then these settings will be reset anyway, so setting them
787 if (arm7_9->has_vector_catch)
789 /* program vector catch register to catch reset vector */
790 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
794 /* program watchpoint unit to match on reset vector address */
795 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], 0x0);
796 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);
797 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
798 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
799 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
803 /* here we should issue a srst only, but we may have to assert trst as well */
804 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
806 jtag_add_reset(1, 1);
809 jtag_add_reset(0, 1);
813 target->state = TARGET_RESET;
814 jtag_add_sleep(50000);
816 armv4_5_invalidate_core_regs(target);
818 if ((target->reset_halt)&&((jtag_reset_config & RESET_SRST_PULLS_TRST)==0))
820 /* debug entry was already prepared in arm7_9_assert_reset() */
821 target->debug_reason = DBG_REASON_DBGRQ;
828 int arm7_9_deassert_reset(target_t *target)
831 LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
833 /* deassert reset lines */
834 jtag_add_reset(0, 0);
836 if ((jtag_reset_config & RESET_SRST_PULLS_TRST)!=0)
838 LOG_WARNING("srst pulls trst - can not reset into halted mode. Issuing halt after reset.");
839 /* set up embedded ice registers again */
840 if ((retval=target->type->examine(target))!=ERROR_OK)
843 if ((retval=target_poll(target))!=ERROR_OK)
848 if ((retval=target_halt(target))!=ERROR_OK)
857 int arm7_9_clear_halt(target_t *target)
859 armv4_5_common_t *armv4_5 = target->arch_info;
860 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
861 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
863 /* we used DBGRQ only if we didn't come out of reset */
864 if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq)
866 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
868 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
869 embeddedice_store_reg(dbg_ctrl);
873 if (arm7_9->debug_entry_from_reset && arm7_9->has_vector_catch)
875 /* if we came out of reset, and vector catch is supported, we used
876 * vector catch to enter debug state
877 * restore the register in that case
879 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH]);
883 /* restore registers if watchpoint unit 0 was in use
885 if (arm7_9->wp0_used)
887 if (arm7_9->debug_entry_from_reset)
889 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]);
891 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
892 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
893 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
895 /* control value always has to be restored, as it was either disabled,
896 * or enabled with possibly different bits
898 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
905 int arm7_9_soft_reset_halt(struct target_s *target)
907 armv4_5_common_t *armv4_5 = target->arch_info;
908 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
909 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
910 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
914 if ((retval=target_halt(target))!=ERROR_OK)
919 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0)
921 embeddedice_read_reg(dbg_stat);
922 if ((retval=jtag_execute_queue())!=ERROR_OK)
924 /* do not eat all CPU, time out after 1 se*/
930 LOG_ERROR("Failed to halt CPU after 1 sec");
931 return ERROR_TARGET_TIMEOUT;
933 target->state = TARGET_HALTED;
935 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
936 * ensure that DBGRQ is cleared
938 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
939 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
940 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
941 embeddedice_store_reg(dbg_ctrl);
943 arm7_9_clear_halt(target);
945 /* if the target is in Thumb state, change to ARM state */
946 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
948 u32 r0_thumb, pc_thumb;
949 LOG_DEBUG("target entered debug from Thumb state, changing to ARM");
950 /* Entered debug from Thumb mode */
951 armv4_5->core_state = ARMV4_5_STATE_THUMB;
952 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
955 /* all register content is now invalid */
956 armv4_5_invalidate_core_regs(target);
958 /* SVC, ARM state, IRQ and FIQ disabled */
959 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
960 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
961 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
963 /* start fetching from 0x0 */
964 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
965 armv4_5->core_cache->reg_list[15].dirty = 1;
966 armv4_5->core_cache->reg_list[15].valid = 1;
968 armv4_5->core_mode = ARMV4_5_MODE_SVC;
969 armv4_5->core_state = ARMV4_5_STATE_ARM;
971 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
974 /* reset registers */
975 for (i = 0; i <= 14; i++)
977 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, 0xffffffff);
978 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
979 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
982 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
987 int arm7_9_halt(target_t *target)
989 if (target->state==TARGET_RESET)
991 LOG_ERROR("BUG: arm7/9 does not support halt during reset. This is handled in arm7_9_assert_reset()");
995 armv4_5_common_t *armv4_5 = target->arch_info;
996 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
997 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
999 LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
1001 if (target->state == TARGET_HALTED)
1003 LOG_DEBUG("target was already halted");
1007 if (target->state == TARGET_UNKNOWN)
1009 LOG_WARNING("target was in unknown state when halt was requested");
1012 if (arm7_9->use_dbgrq)
1014 /* program EmbeddedICE Debug Control Register to assert DBGRQ
1016 if (arm7_9->set_special_dbgrq) {
1017 arm7_9->set_special_dbgrq(target);
1019 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);
1020 embeddedice_store_reg(dbg_ctrl);
1025 /* program watchpoint unit to match on any address
1027 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1028 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1029 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1030 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1033 target->debug_reason = DBG_REASON_DBGRQ;
1038 int arm7_9_debug_entry(target_t *target)
1043 u32 r0_thumb, pc_thumb;
1046 /* get pointers to arch-specific information */
1047 armv4_5_common_t *armv4_5 = target->arch_info;
1048 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1049 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
1050 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1052 #ifdef _DEBUG_ARM7_9_
1056 if (arm7_9->pre_debug_entry)
1057 arm7_9->pre_debug_entry(target);
1059 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1060 * ensure that DBGRQ is cleared
1062 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
1063 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
1064 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
1065 embeddedice_store_reg(dbg_ctrl);
1067 arm7_9_clear_halt(target);
1069 if ((retval = jtag_execute_queue()) != ERROR_OK)
1074 if ((retval = arm7_9->examine_debug_reason(target)) != ERROR_OK)
1078 if (target->state != TARGET_HALTED)
1080 LOG_WARNING("target not halted");
1081 return ERROR_TARGET_NOT_HALTED;
1084 /* if the target is in Thumb state, change to ARM state */
1085 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
1087 LOG_DEBUG("target entered debug from Thumb state");
1088 /* Entered debug from Thumb mode */
1089 armv4_5->core_state = ARMV4_5_STATE_THUMB;
1090 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
1091 LOG_DEBUG("r0_thumb: 0x%8.8x, pc_thumb: 0x%8.8x", r0_thumb, pc_thumb);
1095 LOG_DEBUG("target entered debug from ARM state");
1096 /* Entered debug from ARM mode */
1097 armv4_5->core_state = ARMV4_5_STATE_ARM;
1100 for (i = 0; i < 16; i++)
1101 context_p[i] = &context[i];
1102 /* save core registers (r0 - r15 of current core mode) */
1103 arm7_9->read_core_regs(target, 0xffff, context_p);
1105 arm7_9->read_xpsr(target, &cpsr, 0);
1107 if ((retval = jtag_execute_queue()) != ERROR_OK)
1110 /* if the core has been executing in Thumb state, set the T bit */
1111 if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1114 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
1115 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1116 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1118 armv4_5->core_mode = cpsr & 0x1f;
1120 if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
1122 target->state = TARGET_UNKNOWN;
1123 LOG_ERROR("cpsr contains invalid mode value - communication failure");
1124 return ERROR_TARGET_FAILURE;
1127 LOG_DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
1129 if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1131 LOG_DEBUG("thumb state, applying fixups");
1132 context[0] = r0_thumb;
1133 context[15] = pc_thumb;
1134 } else if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1136 /* adjust value stored by STM */
1137 context[15] -= 3 * 4;
1140 if ((target->debug_reason == DBG_REASON_BREAKPOINT)
1141 || (target->debug_reason == DBG_REASON_SINGLESTEP)
1142 || (target->debug_reason == DBG_REASON_WATCHPOINT)
1143 || (target->debug_reason == DBG_REASON_WPTANDBKPT)
1144 || ((target->debug_reason == DBG_REASON_DBGRQ) && (arm7_9->use_dbgrq == 0)))
1145 context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1146 else if (target->debug_reason == DBG_REASON_DBGRQ)
1147 context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1150 LOG_ERROR("unknown debug reason: %i", target->debug_reason);
1153 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1156 for (i=0; i<=15; i++)
1158 LOG_DEBUG("r%i: 0x%8.8x", i, context[i]);
1159 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]);
1160 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
1161 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
1164 LOG_DEBUG("entered debug state at PC 0x%x", context[15]);
1166 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1169 /* exceptions other than USR & SYS have a saved program status register */
1170 if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS))
1173 arm7_9->read_xpsr(target, &spsr, 1);
1174 jtag_execute_queue();
1175 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, spsr);
1176 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
1177 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
1180 /* r0 and r15 (pc) have to be restored later */
1181 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
1182 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).valid;
1184 if ((retval = jtag_execute_queue()) != ERROR_OK)
1187 if (arm7_9->post_debug_entry)
1188 arm7_9->post_debug_entry(target);
1193 int arm7_9_full_context(target_t *target)
1197 armv4_5_common_t *armv4_5 = target->arch_info;
1198 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1202 if (target->state != TARGET_HALTED)
1204 LOG_WARNING("target not halted");
1205 return ERROR_TARGET_NOT_HALTED;
1208 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1211 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1212 * SYS shares registers with User, so we don't touch SYS
1214 for(i = 0; i < 6; i++)
1221 /* check if there are invalid registers in the current mode
1223 for (j = 0; j <= 16; j++)
1225 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1233 /* change processor mode (and mask T bit) */
1234 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1235 tmp_cpsr |= armv4_5_number_to_mode(i);
1237 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1239 for (j = 0; j < 15; j++)
1241 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1243 reg_p[j] = (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value;
1245 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
1246 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1250 /* if only the PSR is invalid, mask is all zeroes */
1252 arm7_9->read_core_regs(target, mask, reg_p);
1254 /* check if the PSR has to be read */
1255 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid == 0)
1257 arm7_9->read_xpsr(target, (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1);
1258 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
1259 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1264 /* restore processor mode (mask T bit) */
1265 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1267 if ((retval = jtag_execute_queue()) != ERROR_OK)
1274 int arm7_9_restore_context(target_t *target)
1276 armv4_5_common_t *armv4_5 = target->arch_info;
1277 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1279 armv4_5_core_reg_t *reg_arch_info;
1280 enum armv4_5_mode current_mode = armv4_5->core_mode;
1287 if (target->state != TARGET_HALTED)
1289 LOG_WARNING("target not halted");
1290 return ERROR_TARGET_NOT_HALTED;
1293 if (arm7_9->pre_restore_context)
1294 arm7_9->pre_restore_context(target);
1296 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1299 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1300 * SYS shares registers with User, so we don't touch SYS
1302 for (i = 0; i < 6; i++)
1304 LOG_DEBUG("examining %s mode", armv4_5_mode_strings[i]);
1307 /* check if there are dirty registers in the current mode
1309 for (j = 0; j <= 16; j++)
1311 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1312 reg_arch_info = reg->arch_info;
1313 if (reg->dirty == 1)
1315 if (reg->valid == 1)
1318 LOG_DEBUG("examining dirty reg: %s", reg->name);
1319 if ((reg_arch_info->mode != ARMV4_5_MODE_ANY)
1320 && (reg_arch_info->mode != current_mode)
1321 && !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS))
1322 && !((reg_arch_info->mode == ARMV4_5_MODE_SYS) && (armv4_5->core_mode == ARMV4_5_MODE_USR)))
1325 LOG_DEBUG("require mode change");
1330 LOG_ERROR("BUG: dirty register '%s', but no valid data", reg->name);
1345 /* change processor mode (mask T bit) */
1346 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1347 tmp_cpsr |= armv4_5_number_to_mode(i);
1349 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1350 current_mode = armv4_5_number_to_mode(i);
1353 for (j = 0; j <= 14; j++)
1355 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1356 reg_arch_info = reg->arch_info;
1359 if (reg->dirty == 1)
1361 regs[j] = buf_get_u32(reg->value, 0, 32);
1366 LOG_DEBUG("writing register %i of mode %s with value 0x%8.8x", j, armv4_5_mode_strings[i], regs[j]);
1372 arm7_9->write_core_regs(target, mask, regs);
1375 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
1376 reg_arch_info = reg->arch_info;
1377 if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
1379 LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8x", i, buf_get_u32(reg->value, 0, 32));
1380 arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
1385 if ((armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 0) && (armv4_5->core_mode != current_mode))
1387 /* restore processor mode (mask T bit) */
1390 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1391 tmp_cpsr |= armv4_5_number_to_mode(i);
1393 LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", tmp_cpsr);
1394 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1396 else if (armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 1)
1398 /* CPSR has been changed, full restore necessary (mask T bit) */
1399 LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1400 arm7_9->write_xpsr(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32) & ~0x20, 0);
1401 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1402 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1406 LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1407 arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1408 armv4_5->core_cache->reg_list[15].dirty = 0;
1410 if (arm7_9->post_restore_context)
1411 arm7_9->post_restore_context(target);
1416 int arm7_9_restart_core(struct target_s *target)
1418 armv4_5_common_t *armv4_5 = target->arch_info;
1419 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1420 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
1422 /* set RESTART instruction */
1423 jtag_add_end_state(TAP_RTI);
1424 if (arm7_9->need_bypass_before_restart) {
1425 arm7_9->need_bypass_before_restart = 0;
1426 arm_jtag_set_instr(jtag_info, 0xf, NULL);
1428 arm_jtag_set_instr(jtag_info, 0x4, NULL);
1430 jtag_add_runtest(1, TAP_RTI);
1431 return jtag_execute_queue();
1434 void arm7_9_enable_watchpoints(struct target_s *target)
1436 watchpoint_t *watchpoint = target->watchpoints;
1440 if (watchpoint->set == 0)
1441 arm7_9_set_watchpoint(target, watchpoint);
1442 watchpoint = watchpoint->next;
1446 void arm7_9_enable_breakpoints(struct target_s *target)
1448 breakpoint_t *breakpoint = target->breakpoints;
1450 /* set any pending breakpoints */
1453 if (breakpoint->set == 0)
1454 arm7_9_set_breakpoint(target, breakpoint);
1455 breakpoint = breakpoint->next;
1459 void arm7_9_disable_bkpts_and_wpts(struct target_s *target)
1461 breakpoint_t *breakpoint = target->breakpoints;
1462 watchpoint_t *watchpoint = target->watchpoints;
1464 /* set any pending breakpoints */
1467 if (breakpoint->set != 0)
1468 arm7_9_unset_breakpoint(target, breakpoint);
1469 breakpoint = breakpoint->next;
1474 if (watchpoint->set != 0)
1475 arm7_9_unset_watchpoint(target, watchpoint);
1476 watchpoint = watchpoint->next;
1480 int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
1482 armv4_5_common_t *armv4_5 = target->arch_info;
1483 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1484 breakpoint_t *breakpoint = target->breakpoints;
1485 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1490 if (target->state != TARGET_HALTED)
1492 LOG_WARNING("target not halted");
1493 return ERROR_TARGET_NOT_HALTED;
1496 if (!debug_execution)
1498 target_free_all_working_areas(target);
1501 /* current = 1: continue on current pc, otherwise continue at <address> */
1503 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1505 /* the front-end may request us not to handle breakpoints */
1506 if (handle_breakpoints)
1508 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1510 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
1511 arm7_9_unset_breakpoint(target, breakpoint);
1513 LOG_DEBUG("enable single-step");
1514 arm7_9->enable_single_step(target);
1516 target->debug_reason = DBG_REASON_SINGLESTEP;
1518 arm7_9_restore_context(target);
1520 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1521 arm7_9->branch_resume(target);
1522 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1524 arm7_9->branch_resume_thumb(target);
1528 LOG_ERROR("unhandled core state");
1532 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1533 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1534 err = arm7_9_execute_sys_speed(target);
1536 LOG_DEBUG("disable single-step");
1537 arm7_9->disable_single_step(target);
1539 if (err != ERROR_OK)
1541 arm7_9_set_breakpoint(target, breakpoint);
1542 target->state = TARGET_UNKNOWN;
1546 arm7_9_debug_entry(target);
1547 LOG_DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1549 LOG_DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
1550 arm7_9_set_breakpoint(target, breakpoint);
1554 /* enable any pending breakpoints and watchpoints */
1555 arm7_9_enable_breakpoints(target);
1556 arm7_9_enable_watchpoints(target);
1558 arm7_9_restore_context(target);
1560 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1562 arm7_9->branch_resume(target);
1564 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1566 arm7_9->branch_resume_thumb(target);
1570 LOG_ERROR("unhandled core state");
1574 /* deassert DBGACK and INTDIS */
1575 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1576 /* INTDIS only when we really resume, not during debug execution */
1577 if (!debug_execution)
1578 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);
1579 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1581 arm7_9_restart_core(target);
1583 target->debug_reason = DBG_REASON_NOTHALTED;
1585 if (!debug_execution)
1587 /* registers are now invalid */
1588 armv4_5_invalidate_core_regs(target);
1589 target->state = TARGET_RUNNING;
1590 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1594 target->state = TARGET_DEBUG_RUNNING;
1595 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1598 LOG_DEBUG("target resumed");
1603 void arm7_9_enable_eice_step(target_t *target)
1605 armv4_5_common_t *armv4_5 = target->arch_info;
1606 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1608 /* setup an inverse breakpoint on the current PC
1609 * - comparator 1 matches the current address
1610 * - rangeout from comparator 1 is connected to comparator 0 rangein
1611 * - comparator 0 matches any address, as long as rangein is low */
1612 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1613 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1614 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1615 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~(EICE_W_CTRL_RANGE|EICE_W_CTRL_nOPC) & 0xff);
1616 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1617 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
1618 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
1619 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
1620 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1623 void arm7_9_disable_eice_step(target_t *target)
1625 armv4_5_common_t *armv4_5 = target->arch_info;
1626 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1628 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
1629 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
1630 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
1631 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
1632 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE]);
1633 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK]);
1634 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK]);
1635 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK]);
1636 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
1639 int arm7_9_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
1641 armv4_5_common_t *armv4_5 = target->arch_info;
1642 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1643 breakpoint_t *breakpoint = NULL;
1646 if (target->state != TARGET_HALTED)
1648 LOG_WARNING("target not halted");
1649 return ERROR_TARGET_NOT_HALTED;
1652 /* current = 1: continue on current pc, otherwise continue at <address> */
1654 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1656 /* the front-end may request us not to handle breakpoints */
1657 if (handle_breakpoints)
1658 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1659 arm7_9_unset_breakpoint(target, breakpoint);
1661 target->debug_reason = DBG_REASON_SINGLESTEP;
1663 arm7_9_restore_context(target);
1665 arm7_9->enable_single_step(target);
1667 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1669 arm7_9->branch_resume(target);
1671 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1673 arm7_9->branch_resume_thumb(target);
1677 LOG_ERROR("unhandled core state");
1681 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1683 err = arm7_9_execute_sys_speed(target);
1684 arm7_9->disable_single_step(target);
1686 /* registers are now invalid */
1687 armv4_5_invalidate_core_regs(target);
1689 if (err != ERROR_OK)
1691 target->state = TARGET_UNKNOWN;
1693 arm7_9_debug_entry(target);
1694 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1695 LOG_DEBUG("target stepped");
1699 arm7_9_set_breakpoint(target, breakpoint);
1705 int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
1710 armv4_5_common_t *armv4_5 = target->arch_info;
1711 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1713 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1716 enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1718 if ((num < 0) || (num > 16))
1719 return ERROR_INVALID_ARGUMENTS;
1721 if ((mode != ARMV4_5_MODE_ANY)
1722 && (mode != armv4_5->core_mode)
1723 && (reg_mode != ARMV4_5_MODE_ANY))
1727 /* change processor mode (mask T bit) */
1728 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1731 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1734 if ((num >= 0) && (num <= 15))
1736 /* read a normal core register */
1737 reg_p[num] = &value;
1739 arm7_9->read_core_regs(target, 1 << num, reg_p);
1743 /* read a program status register
1744 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
1746 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1747 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1749 arm7_9->read_xpsr(target, &value, spsr);
1752 if ((retval = jtag_execute_queue()) != ERROR_OK)
1757 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1758 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1759 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).value, 0, 32, value);
1761 if ((mode != ARMV4_5_MODE_ANY)
1762 && (mode != armv4_5->core_mode)
1763 && (reg_mode != ARMV4_5_MODE_ANY)) {
1764 /* restore processor mode (mask T bit) */
1765 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1772 int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value)
1775 armv4_5_common_t *armv4_5 = target->arch_info;
1776 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1778 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1781 enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1783 if ((num < 0) || (num > 16))
1784 return ERROR_INVALID_ARGUMENTS;
1786 if ((mode != ARMV4_5_MODE_ANY)
1787 && (mode != armv4_5->core_mode)
1788 && (reg_mode != ARMV4_5_MODE_ANY)) {
1791 /* change processor mode (mask T bit) */
1792 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1795 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1798 if ((num >= 0) && (num <= 15))
1800 /* write a normal core register */
1803 arm7_9->write_core_regs(target, 1 << num, reg);
1807 /* write a program status register
1808 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
1810 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1811 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1813 /* if we're writing the CPSR, mask the T bit */
1817 arm7_9->write_xpsr(target, value, spsr);
1820 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1821 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1823 if ((mode != ARMV4_5_MODE_ANY)
1824 && (mode != armv4_5->core_mode)
1825 && (reg_mode != ARMV4_5_MODE_ANY)) {
1826 /* restore processor mode (mask T bit) */
1827 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1830 return jtag_execute_queue();
1833 int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1835 armv4_5_common_t *armv4_5 = target->arch_info;
1836 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1839 int num_accesses = 0;
1840 int thisrun_accesses;
1846 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1848 if (target->state != TARGET_HALTED)
1850 LOG_WARNING("target not halted");
1851 return ERROR_TARGET_NOT_HALTED;
1854 /* sanitize arguments */
1855 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1856 return ERROR_INVALID_ARGUMENTS;
1858 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1859 return ERROR_TARGET_UNALIGNED_ACCESS;
1861 /* load the base register with the address of the first word */
1863 arm7_9->write_core_regs(target, 0x1, reg);
1868 while (num_accesses < count)
1871 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1872 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1874 if (last_reg <= thisrun_accesses)
1875 last_reg = thisrun_accesses;
1877 arm7_9->load_word_regs(target, reg_list);
1879 /* fast memory reads are only safe when the target is running
1880 * from a sufficiently high clock (32 kHz is usually too slow)
1882 if (arm7_9->fast_memory_access)
1883 arm7_9_execute_fast_sys_speed(target);
1885 arm7_9_execute_sys_speed(target);
1887 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4);
1889 /* advance buffer, count number of accesses */
1890 buffer += thisrun_accesses * 4;
1891 num_accesses += thisrun_accesses;
1895 while (num_accesses < count)
1898 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1899 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1901 for (i = 1; i <= thisrun_accesses; i++)
1905 arm7_9->load_hword_reg(target, i);
1906 /* fast memory reads are only safe when the target is running
1907 * from a sufficiently high clock (32 kHz is usually too slow)
1909 if (arm7_9->fast_memory_access)
1910 arm7_9_execute_fast_sys_speed(target);
1912 arm7_9_execute_sys_speed(target);
1915 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2);
1917 /* advance buffer, count number of accesses */
1918 buffer += thisrun_accesses * 2;
1919 num_accesses += thisrun_accesses;
1923 while (num_accesses < count)
1926 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1927 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1929 for (i = 1; i <= thisrun_accesses; i++)
1933 arm7_9->load_byte_reg(target, i);
1934 /* fast memory reads are only safe when the target is running
1935 * from a sufficiently high clock (32 kHz is usually too slow)
1937 if (arm7_9->fast_memory_access)
1938 arm7_9_execute_fast_sys_speed(target);
1940 arm7_9_execute_sys_speed(target);
1943 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1);
1945 /* advance buffer, count number of accesses */
1946 buffer += thisrun_accesses * 1;
1947 num_accesses += thisrun_accesses;
1951 LOG_ERROR("BUG: we shouldn't get here");
1956 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1959 for (i=0; i<=last_reg; i++)
1960 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
1962 arm7_9->read_xpsr(target, &cpsr, 0);
1963 if ((retval = jtag_execute_queue()) != ERROR_OK)
1965 LOG_ERROR("JTAG error while reading cpsr");
1966 return ERROR_TARGET_DATA_ABORT;
1969 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
1971 LOG_WARNING("memory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
1973 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1975 return ERROR_TARGET_DATA_ABORT;
1981 int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1983 armv4_5_common_t *armv4_5 = target->arch_info;
1984 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1985 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1988 int num_accesses = 0;
1989 int thisrun_accesses;
1995 #ifdef _DEBUG_ARM7_9_
1996 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1999 if (target->state != TARGET_HALTED)
2001 LOG_WARNING("target not halted");
2002 return ERROR_TARGET_NOT_HALTED;
2005 /* sanitize arguments */
2006 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
2007 return ERROR_INVALID_ARGUMENTS;
2009 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
2010 return ERROR_TARGET_UNALIGNED_ACCESS;
2012 /* load the base register with the address of the first word */
2014 arm7_9->write_core_regs(target, 0x1, reg);
2016 /* Clear DBGACK, to make sure memory fetches work as expected */
2017 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
2018 embeddedice_store_reg(dbg_ctrl);
2023 while (num_accesses < count)
2026 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2027 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2029 for (i = 1; i <= thisrun_accesses; i++)
2033 reg[i] = target_buffer_get_u32(target, buffer);
2037 arm7_9->write_core_regs(target, reg_list, reg);
2039 arm7_9->store_word_regs(target, reg_list);
2041 /* fast memory writes are only safe when the target is running
2042 * from a sufficiently high clock (32 kHz is usually too slow)
2044 if (arm7_9->fast_memory_access)
2045 arm7_9_execute_fast_sys_speed(target);
2047 arm7_9_execute_sys_speed(target);
2049 num_accesses += thisrun_accesses;
2053 while (num_accesses < count)
2056 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2057 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2059 for (i = 1; i <= thisrun_accesses; i++)
2063 reg[i] = target_buffer_get_u16(target, buffer) & 0xffff;
2067 arm7_9->write_core_regs(target, reg_list, reg);
2069 for (i = 1; i <= thisrun_accesses; i++)
2071 arm7_9->store_hword_reg(target, i);
2073 /* fast memory writes are only safe when the target is running
2074 * from a sufficiently high clock (32 kHz is usually too slow)
2076 if (arm7_9->fast_memory_access)
2077 arm7_9_execute_fast_sys_speed(target);
2079 arm7_9_execute_sys_speed(target);
2082 num_accesses += thisrun_accesses;
2086 while (num_accesses < count)
2089 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2090 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2092 for (i = 1; i <= thisrun_accesses; i++)
2096 reg[i] = *buffer++ & 0xff;
2099 arm7_9->write_core_regs(target, reg_list, reg);
2101 for (i = 1; i <= thisrun_accesses; i++)
2103 arm7_9->store_byte_reg(target, i);
2104 /* fast memory writes are only safe when the target is running
2105 * from a sufficiently high clock (32 kHz is usually too slow)
2107 if (arm7_9->fast_memory_access)
2108 arm7_9_execute_fast_sys_speed(target);
2110 arm7_9_execute_sys_speed(target);
2113 num_accesses += thisrun_accesses;
2117 LOG_ERROR("BUG: we shouldn't get here");
2123 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
2124 embeddedice_store_reg(dbg_ctrl);
2126 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
2129 for (i=0; i<=last_reg; i++)
2130 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
2132 arm7_9->read_xpsr(target, &cpsr, 0);
2133 if ((retval = jtag_execute_queue()) != ERROR_OK)
2135 LOG_ERROR("JTAG error while reading cpsr");
2136 return ERROR_TARGET_DATA_ABORT;
2139 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
2141 LOG_WARNING("memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
2143 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
2145 return ERROR_TARGET_DATA_ABORT;
2151 static const u32 dcc_code[] =
2153 /* MRC TST BNE MRC STR B */
2154 0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9
2157 int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
2159 armv4_5_common_t *armv4_5 = target->arch_info;
2160 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
2161 enum armv4_5_state core_state = armv4_5->core_state;
2162 u32 r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
2163 u32 r1 = buf_get_u32(armv4_5->core_cache->reg_list[1].value, 0, 32);
2164 u32 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
2167 if (!arm7_9->dcc_downloads)
2168 return target->type->write_memory(target, address, 4, count, buffer);
2170 /* regrab previously allocated working_area, or allocate a new one */
2171 if (!arm7_9->dcc_working_area)
2173 u8 dcc_code_buf[6 * 4];
2175 /* make sure we have a working area */
2176 if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
2178 LOG_INFO("no working area available, falling back to memory writes");
2179 return target->type->write_memory(target, address, 4, count, buffer);
2182 /* copy target instructions to target endianness */
2183 for (i = 0; i < 6; i++)
2185 target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
2188 /* write DCC code to working area */
2189 target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf);
2192 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address);
2193 armv4_5->core_cache->reg_list[0].valid = 1;
2194 armv4_5->core_cache->reg_list[0].dirty = 1;
2195 armv4_5->core_state = ARMV4_5_STATE_ARM;
2197 arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
2199 int little=target->endianness==TARGET_LITTLE_ENDIAN;
2202 /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
2203 core function repeated.
2205 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2208 embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
2209 u8 reg_addr = ice_reg->addr & 0x1f;
2210 int chain_pos = ice_reg->jtag_info->chain_pos;
2212 embeddedice_write_dcc(chain_pos, reg_addr, buffer, little, count-2);
2213 buffer += (count-2)*4;
2215 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2218 for (i = 0; i < count; i++)
2220 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2225 target_halt(target);
2227 for (i=0; i<100; i++)
2229 target_poll(target);
2230 if (target->state == TARGET_HALTED)
2232 usleep(1000); /* sleep 1ms */
2236 LOG_ERROR("bulk write timed out, target not halted");
2237 return ERROR_TARGET_TIMEOUT;
2240 /* restore target state */
2241 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, r0);
2242 armv4_5->core_cache->reg_list[0].valid = 1;
2243 armv4_5->core_cache->reg_list[0].dirty = 1;
2244 buf_set_u32(armv4_5->core_cache->reg_list[1].value, 0, 32, r1);
2245 armv4_5->core_cache->reg_list[1].valid = 1;
2246 armv4_5->core_cache->reg_list[1].dirty = 1;
2247 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, pc);
2248 armv4_5->core_cache->reg_list[15].valid = 1;
2249 armv4_5->core_cache->reg_list[15].dirty = 1;
2250 armv4_5->core_state = core_state;
2255 int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
2257 working_area_t *crc_algorithm;
2258 armv4_5_algorithm_t armv4_5_info;
2259 reg_param_t reg_params[2];
2262 u32 arm7_9_crc_code[] = {
2263 0xE1A02000, /* mov r2, r0 */
2264 0xE3E00000, /* mov r0, #0xffffffff */
2265 0xE1A03001, /* mov r3, r1 */
2266 0xE3A04000, /* mov r4, #0 */
2267 0xEA00000B, /* b ncomp */
2269 0xE7D21004, /* ldrb r1, [r2, r4] */
2270 0xE59F7030, /* ldr r7, CRC32XOR */
2271 0xE0200C01, /* eor r0, r0, r1, asl 24 */
2272 0xE3A05000, /* mov r5, #0 */
2274 0xE3500000, /* cmp r0, #0 */
2275 0xE1A06080, /* mov r6, r0, asl #1 */
2276 0xE2855001, /* add r5, r5, #1 */
2277 0xE1A00006, /* mov r0, r6 */
2278 0xB0260007, /* eorlt r0, r6, r7 */
2279 0xE3550008, /* cmp r5, #8 */
2280 0x1AFFFFF8, /* bne loop */
2281 0xE2844001, /* add r4, r4, #1 */
2283 0xE1540003, /* cmp r4, r3 */
2284 0x1AFFFFF1, /* bne nbyte */
2286 0xEAFFFFFE, /* b end */
2287 0x04C11DB7 /* CRC32XOR: .word 0x04C11DB7 */
2292 if (target_alloc_working_area(target, sizeof(arm7_9_crc_code), &crc_algorithm) != ERROR_OK)
2294 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2297 /* convert flash writing code into a buffer in target endianness */
2298 for (i = 0; i < (sizeof(arm7_9_crc_code)/sizeof(u32)); i++)
2299 target_write_u32(target, crc_algorithm->address + i*sizeof(u32), arm7_9_crc_code[i]);
2301 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
2302 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
2303 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
2305 init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT);
2306 init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
2308 buf_set_u32(reg_params[0].value, 0, 32, address);
2309 buf_set_u32(reg_params[1].value, 0, 32, count);
2311 if ((retval = target->type->run_algorithm(target, 0, NULL, 2, reg_params,
2312 crc_algorithm->address, crc_algorithm->address + (sizeof(arm7_9_crc_code) - 8), 20000, &armv4_5_info)) != ERROR_OK)
2314 LOG_ERROR("error executing arm7_9 crc algorithm");
2315 destroy_reg_param(®_params[0]);
2316 destroy_reg_param(®_params[1]);
2317 target_free_working_area(target, crc_algorithm);
2321 *checksum = buf_get_u32(reg_params[0].value, 0, 32);
2323 destroy_reg_param(®_params[0]);
2324 destroy_reg_param(®_params[1]);
2326 target_free_working_area(target, crc_algorithm);
2331 int arm7_9_blank_check_memory(struct target_s *target, u32 address, u32 count, u32* blank)
2333 working_area_t *erase_check_algorithm;
2334 reg_param_t reg_params[3];
2335 armv4_5_algorithm_t armv4_5_info;
2339 u32 erase_check_code[] =
2342 0xe4d03001, /* ldrb r3, [r0], #1 */
2343 0xe0022003, /* and r2, r2, r3 */
2344 0xe2511001, /* subs r1, r1, #1 */
2345 0x1afffffb, /* bne loop */
2347 0xeafffffe /* b end */
2350 /* make sure we have a working area */
2351 if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK)
2353 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2356 /* convert flash writing code into a buffer in target endianness */
2357 for (i = 0; i < (sizeof(erase_check_code)/sizeof(u32)); i++)
2358 target_write_u32(target, erase_check_algorithm->address + i*sizeof(u32), erase_check_code[i]);
2360 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
2361 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
2362 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
2364 init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
2365 buf_set_u32(reg_params[0].value, 0, 32, address);
2367 init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
2368 buf_set_u32(reg_params[1].value, 0, 32, count);
2370 init_reg_param(®_params[2], "r2", 32, PARAM_IN_OUT);
2371 buf_set_u32(reg_params[2].value, 0, 32, 0xff);
2373 if ((retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params,
2374 erase_check_algorithm->address, erase_check_algorithm->address + (sizeof(erase_check_code) - 4), 10000, &armv4_5_info)) != ERROR_OK)
2376 destroy_reg_param(®_params[0]);
2377 destroy_reg_param(®_params[1]);
2378 destroy_reg_param(®_params[2]);
2379 target_free_working_area(target, erase_check_algorithm);
2383 *blank = buf_get_u32(reg_params[2].value, 0, 32);
2385 destroy_reg_param(®_params[0]);
2386 destroy_reg_param(®_params[1]);
2387 destroy_reg_param(®_params[2]);
2389 target_free_working_area(target, erase_check_algorithm);
2394 int arm7_9_register_commands(struct command_context_s *cmd_ctx)
2396 command_t *arm7_9_cmd;
2398 arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands");
2400 register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register <value> <not cpsr|spsr>");
2401 register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> <rotate> <not cpsr|spsr>");
2403 register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register <num> <mode> <value>");
2405 register_command(cmd_ctx, arm7_9_cmd, "sw_bkpts", handle_arm7_9_sw_bkpts_command, COMMAND_EXEC, "support for software breakpoints <enable|disable>");
2406 register_command(cmd_ctx, arm7_9_cmd, "force_hw_bkpts", handle_arm7_9_force_hw_bkpts_command, COMMAND_EXEC, "use hardware breakpoints for all breakpoints (disables sw breakpoint support) <enable|disable>");
2407 register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command,
2408 COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable|disable>");
2409 register_command(cmd_ctx, arm7_9_cmd, "fast_writes", handle_arm7_9_fast_memory_access_command,
2410 COMMAND_ANY, "(deprecated, see: arm7_9 fast_memory_access)");
2411 register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", handle_arm7_9_fast_memory_access_command,
2412 COMMAND_ANY, "use fast memory accesses instead of slower but potentially unsafe slow accesses <enable|disable>");
2413 register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", handle_arm7_9_dcc_downloads_command,
2414 COMMAND_ANY, "use DCC downloads for larger memory writes <enable|disable>");
2416 armv4_5_register_commands(cmd_ctx);
2418 etm_register_commands(cmd_ctx);
2423 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2428 target_t *target = get_current_target(cmd_ctx);
2429 armv4_5_common_t *armv4_5;
2430 arm7_9_common_t *arm7_9;
2432 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2434 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2438 if (target->state != TARGET_HALTED)
2440 command_print(cmd_ctx, "can't write registers while running");
2446 command_print(cmd_ctx, "usage: write_xpsr <value> <not cpsr|spsr>");
2450 value = strtoul(args[0], NULL, 0);
2451 spsr = strtol(args[1], NULL, 0);
2453 /* if we're writing the CPSR, mask the T bit */
2457 arm7_9->write_xpsr(target, value, spsr);
2458 if ((retval = jtag_execute_queue()) != ERROR_OK)
2460 LOG_ERROR("JTAG error while writing to xpsr");
2467 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2473 target_t *target = get_current_target(cmd_ctx);
2474 armv4_5_common_t *armv4_5;
2475 arm7_9_common_t *arm7_9;
2477 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2479 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2483 if (target->state != TARGET_HALTED)
2485 command_print(cmd_ctx, "can't write registers while running");
2491 command_print(cmd_ctx, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr|spsr>");
2495 value = strtoul(args[0], NULL, 0);
2496 rotate = strtol(args[1], NULL, 0);
2497 spsr = strtol(args[2], NULL, 0);
2499 arm7_9->write_xpsr_im8(target, value, rotate, spsr);
2500 if ((retval = jtag_execute_queue()) != ERROR_OK)
2502 LOG_ERROR("JTAG error while writing 8-bit immediate to xpsr");
2509 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2514 target_t *target = get_current_target(cmd_ctx);
2515 armv4_5_common_t *armv4_5;
2516 arm7_9_common_t *arm7_9;
2518 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2520 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2524 if (target->state != TARGET_HALTED)
2526 command_print(cmd_ctx, "can't write registers while running");
2532 command_print(cmd_ctx, "usage: write_core_reg <num> <mode> <value>");
2536 num = strtol(args[0], NULL, 0);
2537 mode = strtoul(args[1], NULL, 0);
2538 value = strtoul(args[2], NULL, 0);
2540 arm7_9_write_core_reg(target, num, mode, value);
2545 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2547 target_t *target = get_current_target(cmd_ctx);
2548 armv4_5_common_t *armv4_5;
2549 arm7_9_common_t *arm7_9;
2551 if (target->state != TARGET_HALTED)
2553 LOG_ERROR("target not halted");
2554 return ERROR_TARGET_NOT_HALTED;
2557 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2559 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2565 command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2569 if (strcmp("enable", args[0]) == 0)
2571 if (arm7_9->sw_bkpts_use_wp)
2573 arm7_9_enable_sw_bkpts(target);
2577 arm7_9->sw_bkpts_enabled = 1;
2580 else if (strcmp("disable", args[0]) == 0)
2582 if (arm7_9->sw_bkpts_use_wp)
2584 arm7_9_disable_sw_bkpts(target);
2588 arm7_9->sw_bkpts_enabled = 0;
2593 command_print(cmd_ctx, "usage: arm7_9 sw_bkpts <enable|disable>");
2596 command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2601 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2603 target_t *target = get_current_target(cmd_ctx);
2604 armv4_5_common_t *armv4_5;
2605 arm7_9_common_t *arm7_9;
2607 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2609 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2613 if ((argc >= 1) && (strcmp("enable", args[0]) == 0))
2615 arm7_9->force_hw_bkpts = 1;
2616 if (arm7_9->sw_bkpts_use_wp)
2618 arm7_9_disable_sw_bkpts(target);
2621 else if ((argc >= 1) && (strcmp("disable", args[0]) == 0))
2623 arm7_9->force_hw_bkpts = 0;
2627 command_print(cmd_ctx, "usage: arm7_9 force_hw_bkpts <enable|disable>");
2630 command_print(cmd_ctx, "force hardware breakpoints %s", (arm7_9->force_hw_bkpts) ? "enabled" : "disabled");
2635 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2637 target_t *target = get_current_target(cmd_ctx);
2638 armv4_5_common_t *armv4_5;
2639 arm7_9_common_t *arm7_9;
2641 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2643 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2649 if (strcmp("enable", args[0]) == 0)
2651 arm7_9->use_dbgrq = 1;
2653 else if (strcmp("disable", args[0]) == 0)
2655 arm7_9->use_dbgrq = 0;
2659 command_print(cmd_ctx, "usage: arm7_9 dbgrq <enable|disable>");
2663 command_print(cmd_ctx, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
2668 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2670 target_t *target = get_current_target(cmd_ctx);
2671 armv4_5_common_t *armv4_5;
2672 arm7_9_common_t *arm7_9;
2674 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2676 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2682 if (strcmp("enable", args[0]) == 0)
2684 arm7_9->fast_memory_access = 1;
2686 else if (strcmp("disable", args[0]) == 0)
2688 arm7_9->fast_memory_access = 0;
2692 command_print(cmd_ctx, "usage: arm7_9 fast_memory_access <enable|disable>");
2696 command_print(cmd_ctx, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");
2701 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2703 target_t *target = get_current_target(cmd_ctx);
2704 armv4_5_common_t *armv4_5;
2705 arm7_9_common_t *arm7_9;
2707 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2709 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2715 if (strcmp("enable", args[0]) == 0)
2717 arm7_9->dcc_downloads = 1;
2719 else if (strcmp("disable", args[0]) == 0)
2721 arm7_9->dcc_downloads = 0;
2725 command_print(cmd_ctx, "usage: arm7_9 dcc_downloads <enable|disable>");
2729 command_print(cmd_ctx, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");
2734 int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
2736 armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common;
2738 arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
2740 arm_jtag_setup_connection(&arm7_9->jtag_info);
2741 arm7_9->wp_available = 2;
2742 arm7_9->wp0_used = 0;
2743 arm7_9->wp1_used = 0;
2744 arm7_9->force_hw_bkpts = 0;
2745 arm7_9->use_dbgrq = 0;
2747 arm7_9->etm_ctx = NULL;
2748 arm7_9->has_single_step = 0;
2749 arm7_9->has_monitor_mode = 0;
2750 arm7_9->has_vector_catch = 0;
2752 arm7_9->debug_entry_from_reset = 0;
2754 arm7_9->dcc_working_area = NULL;
2756 arm7_9->fast_memory_access = fast_and_dangerous;
2757 arm7_9->dcc_downloads = fast_and_dangerous;
2759 arm7_9->need_bypass_before_restart = 0;
2761 armv4_5->arch_info = arm7_9;
2762 armv4_5->read_core_reg = arm7_9_read_core_reg;
2763 armv4_5->write_core_reg = arm7_9_write_core_reg;
2764 armv4_5->full_context = arm7_9_full_context;
2766 armv4_5_init_arch_info(target, armv4_5);
2768 target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target);