git.sur5r.net Git - openocd/blob - src/target/arm7_9_common.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "replacements.h"
  25
  26 #include "embeddedice.h"
  27 #include "target.h"
  28 #include "armv4_5.h"
  29 #include "arm_jtag.h"
  30 #include "jtag.h"
  31 #include "log.h"
  32 #include "arm7_9_common.h"
  33 #include "breakpoints.h"
  34
  35 #include <stdlib.h>
  36 #include <string.h>
  37 #include <unistd.h>
  38
  39 #include <sys/types.h>
  40 #include <sys/stat.h>
  41 #include <sys/time.h>
  42 #include <errno.h>
  43
  44 int arm7_9_debug_entry(target_t *target);
  45 int arm7_9_enable_sw_bkpts(struct target_s *target);
  46
  47 /* command handler forward declarations */
  48 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  49 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  50 int handle_arm7_9_read_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  51 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  52 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  53 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  54 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  55 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  56 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  57 int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  58 int handle_arm7_9_etb_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  59
  60 int arm7_9_reinit_embeddedice(target_t *target)
  61 {
  62         armv4_5_common_t *armv4_5 = target->arch_info;
  63         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  64
  65         breakpoint_t *breakpoint = target->breakpoints;
  66
  67         arm7_9->wp_available = 2;
  68         arm7_9->wp0_used = 0;
  69         arm7_9->wp1_used = 0;
  70
  71         /* mark all hardware breakpoints as unset */
  72         while (breakpoint)
  73         {
  74                 if (breakpoint->type == BKPT_HARD)
  75                 {
  76                         breakpoint->set = 0;
  77                 }
  78                 breakpoint = breakpoint->next;
  79         }
  80
  81         if (arm7_9->sw_bkpts_enabled && arm7_9->sw_bkpts_use_wp)
  82         {
  83                 arm7_9->sw_bkpts_enabled = 0;
  84                 arm7_9_enable_sw_bkpts(target);
  85         }
  86
  87         arm7_9->reinit_embeddedice = 0;
  88
  89         return ERROR_OK;
  90 }
  91
  92 int arm7_9_jtag_callback(enum jtag_event event, void *priv)
  93 {
  94         target_t *target = priv;
  95         armv4_5_common_t *armv4_5 = target->arch_info;
  96         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  97
  98         /* a test-logic reset occured
  99          * the EmbeddedICE registers have been reset
 100          * hardware breakpoints have been cleared
 101          */
 102         if (event == JTAG_TRST_ASSERTED)
 103         {
 104                 arm7_9->reinit_embeddedice = 1;
 105         }
 106
 107         return ERROR_OK;
 108 }
 109
 110 int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p)
 111 {
 112         armv4_5_common_t *armv4_5 = target->arch_info;
 113         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 114
 115         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 116         {
 117                 return -1;
 118         }
 119
 120         if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
 121         {
 122                 return -1;
 123         }
 124
 125         *armv4_5_p = armv4_5;
 126         *arm7_9_p = arm7_9;
 127
 128         return ERROR_OK;
 129 }
 130
 131 int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 132 {
 133         armv4_5_common_t *armv4_5 = target->arch_info;
 134         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 135
 136         if (target->state != TARGET_HALTED)
 137         {
 138                 WARNING("target not halted");
 139                 return ERROR_TARGET_NOT_HALTED;
 140         }
 141
 142         if (arm7_9->force_hw_bkpts)
 143                 breakpoint->type = BKPT_HARD;
 144
 145         if (breakpoint->set)
 146         {
 147                 WARNING("breakpoint already set");
 148                 return ERROR_OK;
 149         }
 150
 151         if (breakpoint->type == BKPT_HARD)
 152         {
 153                 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
 154                 u32 mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
 155                 if (!arm7_9->wp0_used)
 156                 {
 157                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
 158                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
 159                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);
 160                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
 161                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
 162
 163                         jtag_execute_queue();
 164                         arm7_9->wp0_used = 1;
 165                         breakpoint->set = 1;
 166                 }
 167                 else if (!arm7_9->wp1_used)
 168                 {
 169                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
 170                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
 171                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);
 172                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
 173                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
 174
 175                         jtag_execute_queue();
 176                         arm7_9->wp1_used = 1;
 177                         breakpoint->set = 2;
 178                 }
 179                 else
 180                 {
 181                         ERROR("BUG: no hardware comparator available");
 182                         return ERROR_OK;
 183                 }
 184         }
 185         else if (breakpoint->type == BKPT_SOFT)
 186         {
 187                 if (breakpoint->length == 4)
 188                 {
 189                         /* keep the original instruction in target endianness */
 190                         target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
 191                         /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
 192                         target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt);
 193                 }
 194                 else
 195                 {
 196                         /* keep the original instruction in target endianness */
 197                         target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
 198                         /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
 199                         target_write_u32(target, breakpoint->address, arm7_9->thumb_bkpt);
 200                 }
 201                 breakpoint->set = 1;
 202         }
 203
 204         return ERROR_OK;
 205
 206 }
 207
 208 int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 209 {
 210         armv4_5_common_t *armv4_5 = target->arch_info;
 211         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 212
 213         if (target->state != TARGET_HALTED)
 214         {
 215                 WARNING("target not halted");
 216                 return ERROR_TARGET_NOT_HALTED;
 217         }
 218
 219         if (!breakpoint->set)
 220         {
 221                 WARNING("breakpoint not set");
 222                 return ERROR_OK;
 223         }
 224
 225         if (breakpoint->type == BKPT_HARD)
 226         {
 227                 if (breakpoint->set == 1)
 228                 {
 229                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
 230                         jtag_execute_queue();
 231                         arm7_9->wp0_used = 0;
 232                 }
 233                 else if (breakpoint->set == 2)
 234                 {
 235                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
 236                         jtag_execute_queue();
 237                         arm7_9->wp1_used = 0;
 238                 }
 239                 breakpoint->set = 0;
 240         }
 241         else
 242         {
 243                 /* restore original instruction (kept in target endianness) */
 244                 if (breakpoint->length == 4)
 245                 {
 246                         target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
 247                 }
 248                 else
 249                 {
 250                         target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
 251                 }
 252                 breakpoint->set = 0;
 253         }
 254
 255         return ERROR_OK;
 256 }
 257
 258 int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 259 {
 260         armv4_5_common_t *armv4_5 = target->arch_info;
 261         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 262
 263         if (target->state != TARGET_HALTED)
 264         {
 265                 WARNING("target not halted");
 266                 return ERROR_TARGET_NOT_HALTED;
 267         }
 268
 269         if (arm7_9->force_hw_bkpts)
 270         {
 271                 DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint->address);
 272                 breakpoint->type = BKPT_HARD;
 273         }
 274
 275         if ((breakpoint->type == BKPT_SOFT) && (arm7_9->sw_bkpts_enabled == 0))
 276         {
 277                 INFO("sw breakpoint requested, but software breakpoints not enabled");
 278                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 279         }
 280
 281         if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1))
 282         {
 283                 INFO("no watchpoint unit available for hardware breakpoint");
 284                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 285         }
 286
 287         if ((breakpoint->length != 2) && (breakpoint->length != 4))
 288         {
 289                 INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
 290                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 291         }
 292
 293         if (breakpoint->type == BKPT_HARD)
 294                 arm7_9->wp_available--;
 295
 296         return ERROR_OK;
 297 }
 298
 299 int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 300 {
 301         armv4_5_common_t *armv4_5 = target->arch_info;
 302         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 303
 304         if (target->state != TARGET_HALTED)
 305         {
 306                 WARNING("target not halted");
 307                 return ERROR_TARGET_NOT_HALTED;
 308         }
 309
 310         if (breakpoint->set)
 311         {
 312                 arm7_9_unset_breakpoint(target, breakpoint);
 313         }
 314
 315         if (breakpoint->type == BKPT_HARD)
 316                 arm7_9->wp_available++;
 317
 318         return ERROR_OK;
 319 }
 320
 321 int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 322 {
 323         armv4_5_common_t *armv4_5 = target->arch_info;
 324         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 325         int rw_mask = 1;
 326         u32 mask;
 327
 328         mask = watchpoint->length - 1;
 329
 330         if (target->state != TARGET_HALTED)
 331         {
 332                 WARNING("target not halted");
 333                 return ERROR_TARGET_NOT_HALTED;
 334         }
 335
 336         if (watchpoint->rw == WPT_ACCESS)
 337                 rw_mask = 0;
 338         else
 339                 rw_mask = 1;
 340
 341         if (!arm7_9->wp0_used)
 342         {
 343                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
 344                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
 345                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
 346                 if( watchpoint->mask != 0xffffffffu )
 347                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
 348                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
 349                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
 350
 351                 jtag_execute_queue();
 352                 watchpoint->set = 1;
 353                 arm7_9->wp0_used = 2;
 354         }
 355         else if (!arm7_9->wp1_used)
 356         {
 357                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
 358                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
 359                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
 360                 if( watchpoint->mask != 0xffffffffu )
 361                         embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
 362                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
 363                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
 364
 365                 jtag_execute_queue();
 366                 watchpoint->set = 2;
 367                 arm7_9->wp1_used = 2;
 368         }
 369         else
 370         {
 371                 ERROR("BUG: no hardware comparator available");
 372                 return ERROR_OK;
 373         }
 374
 375         return ERROR_OK;
 376 }
 377
 378 int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 379 {
 380         armv4_5_common_t *armv4_5 = target->arch_info;
 381         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 382
 383         if (target->state != TARGET_HALTED)
 384         {
 385                 WARNING("target not halted");
 386                 return ERROR_TARGET_NOT_HALTED;
 387         }
 388
 389         if (!watchpoint->set)
 390         {
 391                 WARNING("breakpoint not set");
 392                 return ERROR_OK;
 393         }
 394
 395         if (watchpoint->set == 1)
 396         {
 397                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
 398                 jtag_execute_queue();
 399                 arm7_9->wp0_used = 0;
 400         }
 401         else if (watchpoint->set == 2)
 402         {
 403                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
 404                 jtag_execute_queue();
 405                 arm7_9->wp1_used = 0;
 406         }
 407         watchpoint->set = 0;
 408
 409         return ERROR_OK;
 410 }
 411
 412 int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 413 {
 414         armv4_5_common_t *armv4_5 = target->arch_info;
 415         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 416
 417         if (target->state != TARGET_HALTED)
 418         {
 419                 WARNING("target not halted");
 420                 return ERROR_TARGET_NOT_HALTED;
 421         }
 422
 423         if (arm7_9->wp_available < 1)
 424         {
 425                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 426         }
 427
 428         if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
 429         {
 430                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 431         }
 432
 433         arm7_9->wp_available--;
 434
 435         return ERROR_OK;
 436 }
 437
 438 int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 439 {
 440         armv4_5_common_t *armv4_5 = target->arch_info;
 441         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 442
 443         if (target->state != TARGET_HALTED)
 444         {
 445                 WARNING("target not halted");
 446                 return ERROR_TARGET_NOT_HALTED;
 447         }
 448
 449         if (watchpoint->set)
 450         {
 451                 arm7_9_unset_watchpoint(target, watchpoint);
 452         }
 453
 454         arm7_9->wp_available++;
 455
 456         return ERROR_OK;
 457 }
 458
 459 int arm7_9_enable_sw_bkpts(struct target_s *target)
 460 {
 461         armv4_5_common_t *armv4_5 = target->arch_info;
 462         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 463         int retval;
 464
 465         if (arm7_9->sw_bkpts_enabled)
 466                 return ERROR_OK;
 467
 468         if (arm7_9->wp_available < 1)
 469         {
 470                 WARNING("can't enable sw breakpoints with no watchpoint unit available");
 471                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 472         }
 473         arm7_9->wp_available--;
 474
 475         if (!arm7_9->wp0_used)
 476         {
 477                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
 478                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
 479                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
 480                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
 481                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
 482                 arm7_9->sw_bkpts_enabled = 1;
 483                 arm7_9->wp0_used = 3;
 484         }
 485         else if (!arm7_9->wp1_used)
 486         {
 487                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
 488                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
 489                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
 490                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
 491                 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
 492                 arm7_9->sw_bkpts_enabled = 2;
 493                 arm7_9->wp1_used = 3;
 494         }
 495         else
 496         {
 497                 ERROR("BUG: both watchpoints used, but wp_available >= 1");
 498                 exit(-1);
 499         }
 500
 501         if ((retval = jtag_execute_queue()) != ERROR_OK)
 502         {
 503                 ERROR("error writing EmbeddedICE registers to enable sw breakpoints");
 504                 exit(-1);
 505         };
 506
 507         return ERROR_OK;
 508 }
 509
 510 int arm7_9_disable_sw_bkpts(struct target_s *target)
 511 {
 512         armv4_5_common_t *armv4_5 = target->arch_info;
 513         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 514
 515         if (!arm7_9->sw_bkpts_enabled)
 516                 return ERROR_OK;
 517
 518         if (arm7_9->sw_bkpts_enabled == 1)
 519         {
 520                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
 521                 arm7_9->sw_bkpts_enabled = 0;
 522                 arm7_9->wp0_used = 0;
 523                 arm7_9->wp_available++;
 524         }
 525         else if (arm7_9->sw_bkpts_enabled == 2)
 526         {
 527                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
 528                 arm7_9->sw_bkpts_enabled = 0;
 529                 arm7_9->wp1_used = 0;
 530                 arm7_9->wp_available++;
 531         }
 532
 533         return ERROR_OK;
 534 }
 535
 536 int arm7_9_execute_sys_speed(struct target_s *target)
 537 {
 538         int timeout;
 539         int retval;
 540
 541         armv4_5_common_t *armv4_5 = target->arch_info;
 542         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 543         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 544         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 545
 546         /* set RESTART instruction */
 547         jtag_add_end_state(TAP_RTI);
 548         arm_jtag_set_instr(jtag_info, 0x4);
 549
 550         for (timeout=0; timeout<50; timeout++)
 551         {
 552                 /* read debug status register */
 553                 embeddedice_read_reg(dbg_stat);
 554                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 555                         return retval;
 556                 if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
 557                                    && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
 558                         break;
 559                 usleep(100000);
 560         }
 561         if (timeout == 50)
 562         {
 563                 ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
 564                 return ERROR_TARGET_TIMEOUT;
 565         }
 566
 567         return ERROR_OK;
 568 }
 569
 570 int arm7_9_execute_fast_sys_speed(struct target_s *target)
 571 {
 572         u8 check_value[4], check_mask[4];
 573
 574         armv4_5_common_t *armv4_5 = target->arch_info;
 575         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 576         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 577         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 578
 579         /* set RESTART instruction */
 580         jtag_add_end_state(TAP_RTI);
 581         arm_jtag_set_instr(jtag_info, 0x4);
 582
 583         /* check for DBGACK and SYSCOMP set (others don't care) */
 584         buf_set_u32(check_value, 0, 32, 0x9);
 585         buf_set_u32(check_mask, 0, 32, 0x9);
 586
 587         /* read debug status register */
 588         embeddedice_read_reg_w_check(dbg_stat, check_value, check_value);
 589
 590         return ERROR_OK;
 591 }
 592
 593 enum target_state arm7_9_poll(target_t *target)
 594 {
 595         int retval;
 596         armv4_5_common_t *armv4_5 = target->arch_info;
 597         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 598         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 599
 600         if (arm7_9->reinit_embeddedice)
 601         {
 602                 arm7_9_reinit_embeddedice(target);
 603         }
 604
 605         /* read debug status register */
 606         embeddedice_read_reg(dbg_stat);
 607         if ((retval = jtag_execute_queue()) != ERROR_OK)
 608         {
 609                 switch (retval)
 610                 {
 611                         case ERROR_JTAG_QUEUE_FAILED:
 612                                 ERROR("JTAG queue failed while reading EmbeddedICE status register");
 613                                 exit(-1);
 614                                 break;
 615                         default:
 616                                 break;
 617                 }
 618         }
 619
 620         if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
 621         {
 622                 DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));
 623                 if ((target->state == TARGET_UNKNOWN))
 624                 {
 625                         WARNING("DBGACK set while target was in unknown state. Reset or initialize target before resuming");
 626                         target->state = TARGET_RUNNING;
 627                 }
 628                 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
 629                 {
 630                         target->state = TARGET_HALTED;
 631                         if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
 632                                 return retval;
 633
 634                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 635                 }
 636                 if (target->state == TARGET_DEBUG_RUNNING)
 637                 {
 638                         target->state = TARGET_HALTED;
 639                         if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
 640                                 return retval;
 641
 642                         target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 643                 }
 644         }
 645         else
 646         {
 647                 if (target->state != TARGET_DEBUG_RUNNING)
 648                         target->state = TARGET_RUNNING;
 649         }
 650
 651         return target->state;
 652 }
 653
 654 int arm7_9_assert_reset(target_t *target)
 655 {
 656         int retval;
 657
 658         DEBUG("target->state: %s", target_state_strings[target->state]);
 659
 660         if (target->state == TARGET_HALTED || target->state == TARGET_UNKNOWN)
 661         {
 662                 /* if the target wasn't running, there might be working areas allocated */
 663                 target_free_all_working_areas(target);
 664
 665                 /* assert SRST and TRST */
 666                 /* system would get ouf sync if we didn't reset test-logic, too */
 667                 if ((retval = jtag_add_reset(1, 1)) != ERROR_OK)
 668                 {
 669                         if (retval == ERROR_JTAG_RESET_CANT_SRST)
 670                         {
 671                                 WARNING("can't assert srst");
 672                                 return retval;
 673                         }
 674                         else
 675                         {
 676                                 ERROR("unknown error");
 677                                 exit(-1);
 678                         }
 679                 }
 680                 jtag_add_sleep(5000);
 681                 if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)
 682                 {
 683                         if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
 684                         {
 685                                 WARNING("srst resets test logic, too");
 686                                 retval = jtag_add_reset(1, 1);
 687                         }
 688                 }
 689         }
 690         else
 691         {
 692                 if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)
 693                 {
 694                         if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
 695                         {
 696                                 WARNING("srst resets test logic, too");
 697                                 retval = jtag_add_reset(1, 1);
 698                         }
 699
 700                         if (retval == ERROR_JTAG_RESET_CANT_SRST)
 701                         {
 702                                 WARNING("can't assert srst");
 703                                 return retval;
 704                         }
 705                         else if (retval != ERROR_OK)
 706                         {
 707                                 ERROR("unknown error");
 708                                 exit(-1);
 709                         }
 710                 }
 711         }
 712
 713         target->state = TARGET_RESET;
 714         jtag_add_sleep(50000);
 715
 716         armv4_5_invalidate_core_regs(target);
 717
 718         return ERROR_OK;
 719
 720 }
 721
 722 int arm7_9_deassert_reset(target_t *target)
 723 {
 724         DEBUG("target->state: %s", target_state_strings[target->state]);
 725
 726         /* deassert reset lines */
 727         jtag_add_reset(0, 0);
 728
 729         return ERROR_OK;
 730
 731 }
 732
 733 int arm7_9_clear_halt(target_t *target)
 734 {
 735         armv4_5_common_t *armv4_5 = target->arch_info;
 736         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 737         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 738
 739         if (arm7_9->use_dbgrq)
 740         {
 741                 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
 742                  */
 743                 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
 744                 embeddedice_store_reg(dbg_ctrl);
 745         }
 746         else
 747         {
 748                 /* restore registers if watchpoint unit 0 was in use
 749                  */
 750                 if (arm7_9->wp0_used)
 751                 {
 752                         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
 753                         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
 754                         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
 755                 }
 756                 /* control value always has to be restored, as it was either disabled,
 757                  * or enabled with possibly different bits
 758                  */
 759                 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
 760         }
 761
 762         return ERROR_OK;
 763 }
 764
 765 int arm7_9_soft_reset_halt(struct target_s *target)
 766 {
 767         armv4_5_common_t *armv4_5 = target->arch_info;
 768         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 769         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 770         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 771         int i;
 772
 773         if (target->state == TARGET_RUNNING)
 774         {
 775                 target->type->halt(target);
 776         }
 777
 778         while (buf_get_u32(dbg_stat->value, EICE_DBG_CONTROL_DBGACK, 1) == 0)
 779         {
 780                 embeddedice_read_reg(dbg_stat);
 781                 jtag_execute_queue();
 782         }
 783         target->state = TARGET_HALTED;
 784
 785         /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
 786          * ensure that DBGRQ is cleared
 787          */
 788         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
 789         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
 790         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
 791         embeddedice_store_reg(dbg_ctrl);
 792
 793         arm7_9_clear_halt(target);
 794
 795         /* if the target is in Thumb state, change to ARM state */
 796         if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
 797         {
 798                 u32 r0_thumb, pc_thumb;
 799                 DEBUG("target entered debug from Thumb state, changing to ARM");
 800                 /* Entered debug from Thumb mode */
 801                 armv4_5->core_state = ARMV4_5_STATE_THUMB;
 802                 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
 803         }
 804
 805         /* all register content is now invalid */
 806         armv4_5_invalidate_core_regs(target);
 807
 808         /* SVC, ARM state, IRQ and FIQ disabled */
 809         buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
 810         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
 811         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
 812
 813         /* start fetching from 0x0 */
 814         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
 815         armv4_5->core_cache->reg_list[15].dirty = 1;
 816         armv4_5->core_cache->reg_list[15].valid = 1;
 817
 818         armv4_5->core_mode = ARMV4_5_MODE_SVC;
 819         armv4_5->core_state = ARMV4_5_STATE_ARM;
 820
 821         /* reset registers */
 822         for (i = 0; i <= 14; i++)
 823         {
 824                 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, 0xffffffff);
 825                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
 826                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
 827         }
 828
 829         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 830
 831         return ERROR_OK;
 832 }
 833
 834 int arm7_9_halt(target_t *target)
 835 {
 836         armv4_5_common_t *armv4_5 = target->arch_info;
 837         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 838         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 839
 840         DEBUG("target->state: %s", target_state_strings[target->state]);
 841
 842         if (target->state == TARGET_HALTED)
 843         {
 844                 WARNING("target was already halted");
 845                 return ERROR_TARGET_ALREADY_HALTED;
 846         }
 847
 848         if (target->state == TARGET_UNKNOWN)
 849         {
 850                 WARNING("target was in unknown state when halt was requested");
 851         }
 852
 853         if ((target->state == TARGET_RESET) && (jtag_reset_config & RESET_SRST_PULLS_TRST) && (jtag_srst))
 854         {
 855                 ERROR("can't request a halt while in reset if nSRST pulls nTRST");
 856                 return ERROR_TARGET_FAILURE;
 857         }
 858
 859         if (arm7_9->use_dbgrq)
 860         {
 861                 /* program EmbeddedICE Debug Control Register to assert DBGRQ
 862                  */
 863                 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);
 864                 embeddedice_store_reg(dbg_ctrl);
 865         }
 866         else
 867         {
 868                 /* program watchpoint unit to match on any address
 869                  */
 870                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
 871                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
 872                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
 873                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
 874         }
 875
 876         target->debug_reason = DBG_REASON_DBGRQ;
 877
 878         return ERROR_OK;
 879 }
 880
 881 int arm7_9_debug_entry(target_t *target)
 882 {
 883         int i;
 884         u32 context[16];
 885         u32* context_p[16];
 886         u32 r0_thumb, pc_thumb;
 887         u32 cpsr;
 888         int retval;
 889         /* get pointers to arch-specific information */
 890         armv4_5_common_t *armv4_5 = target->arch_info;
 891         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 892         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 893         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 894
 895 #ifdef _DEBUG_ARM7_9_
 896         DEBUG("-");
 897 #endif
 898
 899         if (arm7_9->pre_debug_entry)
 900                 arm7_9->pre_debug_entry(target);
 901
 902         /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
 903          * ensure that DBGRQ is cleared
 904          */
 905         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
 906         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
 907         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
 908         embeddedice_store_reg(dbg_ctrl);
 909
 910         arm7_9_clear_halt(target);
 911
 912         if ((retval = jtag_execute_queue()) != ERROR_OK)
 913         {
 914                 switch (retval)
 915                 {
 916                         case ERROR_JTAG_QUEUE_FAILED:
 917                                 ERROR("JTAG queue failed while writing EmbeddedICE control register");
 918                                 exit(-1);
 919                                 break;
 920                         default:
 921                                 break;
 922                 }
 923         }
 924
 925         if ((retval = arm7_9->examine_debug_reason(target)) != ERROR_OK)
 926                 return retval;
 927
 928
 929         if (target->state != TARGET_HALTED)
 930         {
 931                 WARNING("target not halted");
 932                 return ERROR_TARGET_NOT_HALTED;
 933         }
 934
 935         /* if the target is in Thumb state, change to ARM state */
 936         if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
 937         {
 938                 DEBUG("target entered debug from Thumb state");
 939                 /* Entered debug from Thumb mode */
 940                 armv4_5->core_state = ARMV4_5_STATE_THUMB;
 941                 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
 942                 DEBUG("r0_thumb: 0x%8.8x, pc_thumb: 0x%8.8x", r0_thumb, pc_thumb);
 943         }
 944         else
 945         {
 946                 DEBUG("target entered debug from ARM state");
 947                 /* Entered debug from ARM mode */
 948                 armv4_5->core_state = ARMV4_5_STATE_ARM;
 949         }
 950
 951         for (i = 0; i < 16; i++)
 952                 context_p[i] = &context[i];
 953         /* save core registers (r0 - r15 of current core mode) */
 954         arm7_9->read_core_regs(target, 0xffff, context_p);
 955
 956         arm7_9->read_xpsr(target, &cpsr, 0);
 957
 958         if ((retval = jtag_execute_queue()) != ERROR_OK)
 959                 return retval;
 960
 961         /* if the core has been executing in Thumb state, set the T bit */
 962         if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
 963                 cpsr |= 0x20;
 964
 965         buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
 966         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
 967         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
 968
 969         armv4_5->core_mode = cpsr & 0x1f;
 970
 971         if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
 972         {
 973                 target->state = TARGET_UNKNOWN;
 974                 ERROR("cpsr contains invalid mode value - communication failure");
 975                 return ERROR_TARGET_FAILURE;
 976         }
 977
 978         DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
 979
 980         if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
 981         {
 982                 DEBUG("thumb state, applying fixups");
 983                 context[0] = r0_thumb;
 984                 context[15] = pc_thumb;
 985         } else if (armv4_5->core_state == ARMV4_5_STATE_ARM)
 986         {
 987                 /* adjust value stored by STM */
 988                 context[15] -= 3 * 4;
 989         }
 990
 991         if ((target->debug_reason == DBG_REASON_BREAKPOINT)
 992                         || (target->debug_reason == DBG_REASON_SINGLESTEP)
 993                         || (target->debug_reason == DBG_REASON_WATCHPOINT)
 994                         || (target->debug_reason == DBG_REASON_WPTANDBKPT)
 995                         || ((target->debug_reason == DBG_REASON_DBGRQ) && (arm7_9->use_dbgrq == 0)))
 996                 context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
 997         else if (target->debug_reason == DBG_REASON_DBGRQ)
 998                 context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
 999         else
1000         {
1001                 ERROR("unknown debug reason: %i", target->debug_reason);
1002         }
1003
1004
1005         for (i=0; i<=15; i++)
1006         {
1007                 DEBUG("r%i: 0x%8.8x", i, context[i]);
1008                 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]);
1009                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
1010                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
1011         }
1012
1013         DEBUG("entered debug state at PC 0x%x", context[15]);
1014
1015         /* exceptions other than USR & SYS have a saved program status register */
1016         if ((armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_USR) && (armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_SYS))
1017         {
1018                 u32 spsr;
1019                 arm7_9->read_xpsr(target, &spsr, 1);
1020                 jtag_execute_queue();
1021                 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, spsr);
1022                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
1023                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
1024         }
1025
1026         /* r0 and r15 (pc) have to be restored later */
1027         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
1028         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = 1;
1029
1030         if ((retval = jtag->execute_queue()) != ERROR_OK)
1031                 return retval;
1032
1033         if (arm7_9->post_debug_entry)
1034                 arm7_9->post_debug_entry(target);
1035
1036         return ERROR_OK;
1037 }
1038
1039 int arm7_9_full_context(target_t *target)
1040 {
1041         int i;
1042         int retval;
1043         armv4_5_common_t *armv4_5 = target->arch_info;
1044         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1045
1046         DEBUG("-");
1047
1048         if (target->state != TARGET_HALTED)
1049         {
1050                 WARNING("target not halted");
1051                 return ERROR_TARGET_NOT_HALTED;
1052         }
1053
1054         /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1055          * SYS shares registers with User, so we don't touch SYS
1056          */
1057         for(i = 0; i < 6; i++)
1058         {
1059                 u32 mask = 0;
1060                 u32* reg_p[16];
1061                 int j;
1062                 int valid = 1;
1063
1064                 /* check if there are invalid registers in the current mode
1065                  */
1066                 for (j = 0; j <= 16; j++)
1067                 {
1068                         if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1069                                 valid = 0;
1070                 }
1071
1072                 if (!valid)
1073                 {
1074                         u32 tmp_cpsr;
1075
1076                         /* change processor mode (and mask T bit) */
1077                         tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1078                         tmp_cpsr |= armv4_5_number_to_mode(i);
1079                         tmp_cpsr &= ~0x20;
1080                         arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1081
1082                         for (j = 0; j < 15; j++)
1083                         {
1084                                 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1085                                 {
1086                                         reg_p[j] = (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value;
1087                                         mask |= 1 << j;
1088                                         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
1089                                         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1090                                 }
1091                         }
1092
1093                         /* if only the PSR is invalid, mask is all zeroes */
1094                         if (mask)
1095                                 arm7_9->read_core_regs(target, mask, reg_p);
1096
1097                         /* check if the PSR has to be read */
1098                         if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid == 0)
1099                         {
1100                                 arm7_9->read_xpsr(target, (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1);
1101                                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
1102                                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1103                         }
1104                 }
1105         }
1106
1107         /* restore processor mode (mask T bit) */
1108         arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1109
1110         if ((retval = jtag_execute_queue()) != ERROR_OK)
1111         {
1112                 ERROR("JTAG failure");
1113                 exit(-1);
1114         }
1115         return ERROR_OK;
1116 }
1117
1118 int arm7_9_restore_context(target_t *target)
1119 {
1120         armv4_5_common_t *armv4_5 = target->arch_info;
1121         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1122         reg_t *reg;
1123         armv4_5_core_reg_t *reg_arch_info;
1124         enum armv4_5_mode current_mode = armv4_5->core_mode;
1125         int i, j;
1126         int dirty;
1127         int mode_change;
1128
1129         DEBUG("-");
1130
1131         if (target->state != TARGET_HALTED)
1132         {
1133                 WARNING("target not halted");
1134                 return ERROR_TARGET_NOT_HALTED;
1135         }
1136
1137         if (arm7_9->pre_restore_context)
1138                 arm7_9->pre_restore_context(target);
1139
1140         /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1141          * SYS shares registers with User, so we don't touch SYS
1142          */
1143         for (i = 0; i < 6; i++)
1144         {
1145                 DEBUG("examining %s mode", armv4_5_mode_strings[i]);
1146                 dirty = 0;
1147                 mode_change = 0;
1148                 /* check if there are dirty registers in the current mode
1149                 */
1150                 for (j = 0; j <= 16; j++)
1151                 {
1152                         reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1153                         reg_arch_info = reg->arch_info;
1154                         if (reg->dirty == 1)
1155                         {
1156                                 if (reg->valid == 1)
1157                                 {
1158                                         dirty = 1;
1159                                         DEBUG("examining dirty reg: %s", reg->name);
1160                                         if ((reg_arch_info->mode != ARMV4_5_MODE_ANY)
1161                                                 && (reg_arch_info->mode != current_mode)
1162                                                 && !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS))
1163                                                 && !((reg_arch_info->mode == ARMV4_5_MODE_SYS) && (armv4_5->core_mode == ARMV4_5_MODE_USR)))
1164                                         {
1165                                                 mode_change = 1;
1166                                                 DEBUG("require mode change");
1167                                         }
1168                                 }
1169                                 else
1170                                 {
1171                                         ERROR("BUG: dirty register '%s', but no valid data", reg->name);
1172                                         exit(-1);
1173                                 }
1174                         }
1175                 }
1176
1177                 if (dirty)
1178                 {
1179                         u32 mask = 0x0;
1180                         int num_regs = 0;
1181                         u32 regs[16];
1182
1183                         if (mode_change)
1184                         {
1185                                 u32 tmp_cpsr;
1186
1187                                 /* change processor mode (mask T bit) */
1188                                 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1189                                 tmp_cpsr |= armv4_5_number_to_mode(i);
1190                                 tmp_cpsr &= ~0x20;
1191                                 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1192                                 current_mode = armv4_5_number_to_mode(i);
1193                         }
1194
1195                         for (j = 0; j <= 14; j++)
1196                         {
1197                                 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1198                                 reg_arch_info = reg->arch_info;
1199
1200
1201                                 if (reg->dirty == 1)
1202                                 {
1203                                         regs[j] = buf_get_u32(reg->value, 0, 32);
1204                                         mask |= 1 << j;
1205                                         num_regs++;
1206                                         reg->dirty = 0;
1207                                         reg->valid = 1;
1208                                         DEBUG("writing register %i of mode %s with value 0x%8.8x", j, armv4_5_mode_strings[i], regs[j]);
1209                                 }
1210                         }
1211
1212                         if (mask)
1213                         {
1214                                 arm7_9->write_core_regs(target, mask, regs);
1215                         }
1216
1217                         reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
1218                         reg_arch_info = reg->arch_info;
1219                         if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
1220                         {
1221                                 DEBUG("writing SPSR of mode %i with value 0x%8.8x", i, buf_get_u32(reg->value, 0, 32));
1222                                 arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
1223                         }
1224                 }
1225         }
1226
1227         if ((armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 0) && (armv4_5->core_mode != current_mode))
1228         {
1229                 /* restore processor mode (mask T bit) */
1230                 u32 tmp_cpsr;
1231
1232                 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1233                 tmp_cpsr |= armv4_5_number_to_mode(i);
1234                 tmp_cpsr &= ~0x20;
1235                 DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", tmp_cpsr);
1236                 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1237         }
1238         else if (armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 1)
1239         {
1240                 /* CPSR has been changed, full restore necessary (mask T bit) */
1241                 DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1242                 arm7_9->write_xpsr(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32) & ~0x20, 0);
1243                 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1244                 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1245         }
1246
1247         /* restore PC */
1248         DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1249         arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1250         armv4_5->core_cache->reg_list[15].dirty = 0;
1251
1252         if (arm7_9->post_restore_context)
1253                 arm7_9->post_restore_context(target);
1254
1255         return ERROR_OK;
1256 }
1257
1258 int arm7_9_restart_core(struct target_s *target)
1259 {
1260         armv4_5_common_t *armv4_5 = target->arch_info;
1261         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1262         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
1263
1264         /* set RESTART instruction */
1265         jtag_add_end_state(TAP_RTI);
1266         arm_jtag_set_instr(jtag_info, 0x4);
1267
1268         jtag_add_runtest(1, TAP_RTI);
1269         if ((jtag_execute_queue()) != ERROR_OK)
1270         {
1271                 exit(-1);
1272         }
1273
1274         return ERROR_OK;
1275 }
1276
1277 void arm7_9_enable_watchpoints(struct target_s *target)
1278 {
1279         watchpoint_t *watchpoint = target->watchpoints;
1280
1281         while (watchpoint)
1282         {
1283                 if (watchpoint->set == 0)
1284                         arm7_9_set_watchpoint(target, watchpoint);
1285                 watchpoint = watchpoint->next;
1286         }
1287 }
1288
1289 void arm7_9_enable_breakpoints(struct target_s *target)
1290 {
1291         breakpoint_t *breakpoint = target->breakpoints;
1292
1293         /* set any pending breakpoints */
1294         while (breakpoint)
1295         {
1296                 if (breakpoint->set == 0)
1297                         arm7_9_set_breakpoint(target, breakpoint);
1298                 breakpoint = breakpoint->next;
1299         }
1300 }
1301
1302 void arm7_9_disable_bkpts_and_wpts(struct target_s *target)
1303 {
1304         breakpoint_t *breakpoint = target->breakpoints;
1305         watchpoint_t *watchpoint = target->watchpoints;
1306
1307         /* set any pending breakpoints */
1308         while (breakpoint)
1309         {
1310                 if (breakpoint->set != 0)
1311                         arm7_9_unset_breakpoint(target, breakpoint);
1312                 breakpoint = breakpoint->next;
1313         }
1314
1315         while (watchpoint)
1316         {
1317                 if (watchpoint->set != 0)
1318                         arm7_9_unset_watchpoint(target, watchpoint);
1319                 watchpoint = watchpoint->next;
1320         }
1321 }
1322
1323 int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
1324 {
1325         armv4_5_common_t *armv4_5 = target->arch_info;
1326         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1327         breakpoint_t *breakpoint = target->breakpoints;
1328         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1329
1330         DEBUG("-");
1331
1332         if (target->state != TARGET_HALTED)
1333         {
1334                 WARNING("target not halted");
1335                 return ERROR_TARGET_NOT_HALTED;
1336         }
1337
1338         if (!debug_execution)
1339         {
1340                 target_free_all_working_areas(target);
1341         }
1342
1343         /* current = 1: continue on current pc, otherwise continue at <address> */
1344         if (!current)
1345                 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1346
1347         /* the front-end may request us not to handle breakpoints */
1348         if (handle_breakpoints)
1349         {
1350                 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1351                 {
1352                         DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
1353                         arm7_9_unset_breakpoint(target, breakpoint);
1354
1355                         DEBUG("enable single-step");
1356                         arm7_9->enable_single_step(target);
1357
1358                         target->debug_reason = DBG_REASON_SINGLESTEP;
1359
1360                         arm7_9_restore_context(target);
1361
1362                         if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1363                                 arm7_9->branch_resume(target);
1364                         else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1365                         {
1366                                 arm7_9->branch_resume_thumb(target);
1367                         }
1368                         else
1369                         {
1370                                 ERROR("unhandled core state");
1371                                 exit(-1);
1372                         }
1373
1374                         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1375                         embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1376                         arm7_9_execute_sys_speed(target);
1377
1378                         DEBUG("disable single-step");
1379                         arm7_9->disable_single_step(target);
1380
1381                         arm7_9_debug_entry(target);
1382                         DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1383
1384                         DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
1385                         arm7_9_set_breakpoint(target, breakpoint);
1386                 }
1387         }
1388
1389         /* enable any pending breakpoints and watchpoints */
1390         arm7_9_enable_breakpoints(target);
1391         arm7_9_enable_watchpoints(target);
1392
1393         arm7_9_restore_context(target);
1394
1395         if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1396         {
1397                 arm7_9->branch_resume(target);
1398         }
1399         else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1400         {
1401                 arm7_9->branch_resume_thumb(target);
1402         }
1403         else
1404         {
1405                 ERROR("unhandled core state");
1406                 exit(-1);
1407         }
1408
1409         /* deassert DBGACK and INTDIS */
1410         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1411         /* INTDIS only when we really resume, not during debug execution */
1412         if (!debug_execution)
1413                 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);
1414         embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1415
1416         arm7_9_restart_core(target);
1417
1418         target->debug_reason = DBG_REASON_NOTHALTED;
1419
1420         if (!debug_execution)
1421         {
1422                 /* registers are now invalid */
1423                 armv4_5_invalidate_core_regs(target);
1424                 target->state = TARGET_RUNNING;
1425                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1426         }
1427         else
1428         {
1429                 target->state = TARGET_DEBUG_RUNNING;
1430                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1431         }
1432
1433         DEBUG("target resumed");
1434
1435         return ERROR_OK;
1436 }
1437
1438 void arm7_9_enable_eice_step(target_t *target)
1439 {
1440         armv4_5_common_t *armv4_5 = target->arch_info;
1441         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1442
1443         /* setup an inverse breakpoint on the current PC
1444         * - comparator 1 matches the current address
1445         * - rangeout from comparator 1 is connected to comparator 0 rangein
1446         * - comparator 0 matches any address, as long as rangein is low */
1447         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1448         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1449         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
1450         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0x77);
1451         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1452         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
1453         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
1454         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
1455         embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xf7);
1456 }
1457
1458 void arm7_9_disable_eice_step(target_t *target)
1459 {
1460         armv4_5_common_t *armv4_5 = target->arch_info;
1461         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1462
1463         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
1464         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
1465         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
1466         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
1467         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE]);
1468         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK]);
1469         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK]);
1470         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK]);
1471         embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
1472 }
1473
1474 int arm7_9_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
1475 {
1476         armv4_5_common_t *armv4_5 = target->arch_info;
1477         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1478         breakpoint_t *breakpoint = NULL;
1479
1480         if (target->state != TARGET_HALTED)
1481         {
1482                 WARNING("target not halted");
1483                 return ERROR_TARGET_NOT_HALTED;
1484         }
1485
1486         /* current = 1: continue on current pc, otherwise continue at <address> */
1487         if (!current)
1488                 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1489
1490         /* the front-end may request us not to handle breakpoints */
1491         if (handle_breakpoints)
1492                 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1493                         arm7_9_unset_breakpoint(target, breakpoint);
1494
1495         target->debug_reason = DBG_REASON_SINGLESTEP;
1496
1497         arm7_9_restore_context(target);
1498
1499         arm7_9->enable_single_step(target);
1500
1501         if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1502         {
1503                 arm7_9->branch_resume(target);
1504         }
1505         else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1506         {
1507                 arm7_9->branch_resume_thumb(target);
1508         }
1509         else
1510         {
1511                 ERROR("unhandled core state");
1512                 exit(-1);
1513         }
1514
1515         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1516
1517         arm7_9_execute_sys_speed(target);
1518         arm7_9->disable_single_step(target);
1519
1520         /* registers are now invalid */
1521         armv4_5_invalidate_core_regs(target);
1522
1523         arm7_9_debug_entry(target);
1524
1525         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1526
1527         if (breakpoint)
1528                 arm7_9_set_breakpoint(target, breakpoint);
1529
1530         DEBUG("target stepped");
1531
1532         return ERROR_OK;
1533
1534 }
1535
1536 int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
1537 {
1538         u32* reg_p[16];
1539         u32 value;
1540         int retval;
1541         armv4_5_common_t *armv4_5 = target->arch_info;
1542         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1543         enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1544
1545         if ((num < 0) || (num > 16))
1546                 return ERROR_INVALID_ARGUMENTS;
1547
1548         if ((mode != ARMV4_5_MODE_ANY)
1549                         && (mode != armv4_5->core_mode)
1550                         && (reg_mode != ARMV4_5_MODE_ANY))
1551         {
1552                 u32 tmp_cpsr;
1553
1554                 /* change processor mode (mask T bit) */
1555                 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1556                 tmp_cpsr |= mode;
1557                 tmp_cpsr &= ~0x20;
1558                 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1559         }
1560
1561         if ((num >= 0) && (num <= 15))
1562         {
1563                 /* read a normal core register */
1564                 reg_p[num] = &value;
1565
1566                 arm7_9->read_core_regs(target, 1 << num, reg_p);
1567         }
1568         else
1569         {
1570                 /* read a program status register
1571                  * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
1572                  */
1573                 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1574                 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1575
1576                 arm7_9->read_xpsr(target, &value, spsr);
1577         }
1578
1579         if ((retval = jtag_execute_queue()) != ERROR_OK)
1580         {
1581                 ERROR("JTAG failure");
1582                 exit(-1);
1583         }
1584
1585         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1586         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1587         buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).value, 0, 32, value);
1588
1589         if ((mode != ARMV4_5_MODE_ANY)
1590                         && (mode != armv4_5->core_mode)
1591                         && (reg_mode != ARMV4_5_MODE_ANY))      {
1592                 /* restore processor mode (mask T bit) */
1593                 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1594         }
1595
1596         return ERROR_OK;
1597
1598 }
1599
1600 int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value)
1601 {
1602         u32 reg[16];
1603         int retval;
1604         armv4_5_common_t *armv4_5 = target->arch_info;
1605         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1606         enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1607
1608         if ((num < 0) || (num > 16))
1609                 return ERROR_INVALID_ARGUMENTS;
1610
1611         if ((mode != ARMV4_5_MODE_ANY)
1612                         && (mode != armv4_5->core_mode)
1613                         && (reg_mode != ARMV4_5_MODE_ANY))      {
1614                 u32 tmp_cpsr;
1615
1616                 /* change processor mode (mask T bit) */
1617                 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1618                 tmp_cpsr |= mode;
1619                 tmp_cpsr &= ~0x20;
1620                 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1621         }
1622
1623         if ((num >= 0) && (num <= 15))
1624         {
1625                 /* write a normal core register */
1626                 reg[num] = value;
1627
1628                 arm7_9->write_core_regs(target, 1 << num, reg);
1629         }
1630         else
1631         {
1632                 /* write a program status register
1633                 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
1634                 */
1635                 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1636                 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1637
1638                 /* if we're writing the CPSR, mask the T bit */
1639                 if (!spsr)
1640                         value &= ~0x20;
1641
1642                 arm7_9->write_xpsr(target, value, spsr);
1643         }
1644
1645         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1646         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1647
1648         if ((mode != ARMV4_5_MODE_ANY)
1649                         && (mode != armv4_5->core_mode)
1650                         && (reg_mode != ARMV4_5_MODE_ANY))      {
1651                 /* restore processor mode (mask T bit) */
1652                 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1653         }
1654
1655         if ((retval = jtag_execute_queue()) != ERROR_OK)
1656         {
1657                 ERROR("JTAG failure");
1658                 exit(-1);
1659         }
1660
1661         return ERROR_OK;
1662
1663 }
1664
1665 int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1666 {
1667         armv4_5_common_t *armv4_5 = target->arch_info;
1668         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1669
1670         u32 reg[16];
1671         int num_accesses = 0;
1672         int thisrun_accesses;
1673         int i;
1674         u32 cpsr;
1675         int retval;
1676         int last_reg = 0;
1677
1678         DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1679
1680         if (target->state != TARGET_HALTED)
1681         {
1682                 WARNING("target not halted");
1683                 return ERROR_TARGET_NOT_HALTED;
1684         }
1685
1686         /* sanitize arguments */
1687         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1688                 return ERROR_INVALID_ARGUMENTS;
1689
1690         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1691                 return ERROR_TARGET_UNALIGNED_ACCESS;
1692
1693         /* load the base register with the address of the first word */
1694         reg[0] = address;
1695         arm7_9->write_core_regs(target, 0x1, reg);
1696
1697         switch (size)
1698         {
1699                 case 4:
1700                         while (num_accesses < count)
1701                         {
1702                                 u32 reg_list;
1703                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1704                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1705
1706                                 if (last_reg <= thisrun_accesses)
1707                                         last_reg = thisrun_accesses;
1708
1709                                 arm7_9->load_word_regs(target, reg_list);
1710
1711                                 /* fast memory reads are only safe when the target is running
1712                                  * from a sufficiently high clock (32 kHz is usually too slow)
1713                                  */
1714                                 if (arm7_9->fast_memory_access)
1715                                         arm7_9_execute_fast_sys_speed(target);
1716                                 else
1717                                         arm7_9_execute_sys_speed(target);
1718
1719                                 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4);
1720
1721                                 /* advance buffer, count number of accesses */
1722                                 buffer += thisrun_accesses * 4;
1723                                 num_accesses += thisrun_accesses;
1724                         }
1725                         break;
1726                 case 2:
1727                         while (num_accesses < count)
1728                         {
1729                                 u32 reg_list;
1730                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1731                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1732
1733                                 for (i = 1; i <= thisrun_accesses; i++)
1734                                 {
1735                                         if (i > last_reg)
1736                                                 last_reg = i;
1737                                         arm7_9->load_hword_reg(target, i);
1738                                         /* fast memory reads are only safe when the target is running
1739                                          * from a sufficiently high clock (32 kHz is usually too slow)
1740                                          */
1741                                         if (arm7_9->fast_memory_access)
1742                                                 arm7_9_execute_fast_sys_speed(target);
1743                                         else
1744                                                 arm7_9_execute_sys_speed(target);
1745                                 }
1746
1747                                 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2);
1748
1749                                 /* advance buffer, count number of accesses */
1750                                 buffer += thisrun_accesses * 2;
1751                                 num_accesses += thisrun_accesses;
1752                         }
1753                         break;
1754                 case 1:
1755                         while (num_accesses < count)
1756                         {
1757                                 u32 reg_list;
1758                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1759                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1760
1761                                 for (i = 1; i <= thisrun_accesses; i++)
1762                                 {
1763                                         if (i > last_reg)
1764                                                 last_reg = i;
1765                                         arm7_9->load_byte_reg(target, i);
1766                                         /* fast memory reads are only safe when the target is running
1767                                          * from a sufficiently high clock (32 kHz is usually too slow)
1768                                          */
1769                                         if (arm7_9->fast_memory_access)
1770                                                 arm7_9_execute_fast_sys_speed(target);
1771                                         else
1772                                                 arm7_9_execute_sys_speed(target);
1773                                 }
1774
1775                                 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1);
1776
1777                                 /* advance buffer, count number of accesses */
1778                                 buffer += thisrun_accesses * 1;
1779                                 num_accesses += thisrun_accesses;
1780                         }
1781                         break;
1782                 default:
1783                         ERROR("BUG: we shouldn't get here");
1784                         exit(-1);
1785                         break;
1786         }
1787
1788         for (i=0; i<=last_reg; i++)
1789                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
1790
1791         arm7_9->read_xpsr(target, &cpsr, 0);
1792         if ((retval = jtag_execute_queue()) != ERROR_OK)
1793         {
1794                 ERROR("JTAG error while reading cpsr");
1795                 exit(-1);
1796         }
1797
1798         if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
1799         {
1800                 WARNING("memory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
1801
1802                 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1803
1804                 return ERROR_TARGET_DATA_ABORT;
1805         }
1806
1807         return ERROR_OK;
1808 }
1809
1810 int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1811 {
1812         armv4_5_common_t *armv4_5 = target->arch_info;
1813         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1814         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1815
1816         u32 reg[16];
1817         int num_accesses = 0;
1818         int thisrun_accesses;
1819         int i;
1820         u32 cpsr;
1821         int retval;
1822         int last_reg = 0;
1823
1824         DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1825
1826         if (target->state != TARGET_HALTED)
1827         {
1828                 WARNING("target not halted");
1829                 return ERROR_TARGET_NOT_HALTED;
1830         }
1831
1832         /* sanitize arguments */
1833         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1834                 return ERROR_INVALID_ARGUMENTS;
1835
1836         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1837                 return ERROR_TARGET_UNALIGNED_ACCESS;
1838
1839         /* load the base register with the address of the first word */
1840         reg[0] = address;
1841         arm7_9->write_core_regs(target, 0x1, reg);
1842
1843         /* Clear DBGACK, to make sure memory fetches work as expected */
1844         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1845         embeddedice_store_reg(dbg_ctrl);
1846
1847         switch (size)
1848         {
1849                 case 4:
1850                         while (num_accesses < count)
1851                         {
1852                                 u32 reg_list;
1853                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1854                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1855
1856                                 for (i = 1; i <= thisrun_accesses; i++)
1857                                 {
1858                                         if (i > last_reg)
1859                                                 last_reg = i;
1860                                         reg[i] = target_buffer_get_u32(target, buffer);
1861                                         buffer += 4;
1862                                 }
1863
1864                                 arm7_9->write_core_regs(target, reg_list, reg);
1865
1866                                 arm7_9->store_word_regs(target, reg_list);
1867
1868                                 /* fast memory writes are only safe when the target is running
1869                                  * from a sufficiently high clock (32 kHz is usually too slow)
1870                                  */
1871                                 if (arm7_9->fast_memory_access)
1872                                         arm7_9_execute_fast_sys_speed(target);
1873                                 else
1874                                         arm7_9_execute_sys_speed(target);
1875
1876                                 num_accesses += thisrun_accesses;
1877                         }
1878                         break;
1879                 case 2:
1880                         while (num_accesses < count)
1881                         {
1882                                 u32 reg_list;
1883                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1884                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1885
1886                                 for (i = 1; i <= thisrun_accesses; i++)
1887                                 {
1888                                         if (i > last_reg)
1889                                                 last_reg = i;
1890                                         reg[i] = target_buffer_get_u16(target, buffer) & 0xffff;
1891                                         buffer += 2;
1892                                 }
1893
1894                                 arm7_9->write_core_regs(target, reg_list, reg);
1895
1896                                 for (i = 1; i <= thisrun_accesses; i++)
1897                                 {
1898                                         arm7_9->store_hword_reg(target, i);
1899
1900                                         /* fast memory writes are only safe when the target is running
1901                                          * from a sufficiently high clock (32 kHz is usually too slow)
1902                                          */
1903                                         if (arm7_9->fast_memory_access)
1904                                                 arm7_9_execute_fast_sys_speed(target);
1905                                         else
1906                                                 arm7_9_execute_sys_speed(target);
1907                                 }
1908
1909                                 num_accesses += thisrun_accesses;
1910                         }
1911                         break;
1912                 case 1:
1913                         while (num_accesses < count)
1914                         {
1915                                 u32 reg_list;
1916                                 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1917                                 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1918
1919                                 for (i = 1; i <= thisrun_accesses; i++)
1920                                 {
1921                                         if (i > last_reg)
1922                                                 last_reg = i;
1923                                         reg[i] = *buffer++ & 0xff;
1924                                 }
1925
1926                                 arm7_9->write_core_regs(target, reg_list, reg);
1927
1928                                 for (i = 1; i <= thisrun_accesses; i++)
1929                                 {
1930                                         arm7_9->store_byte_reg(target, i);
1931                                         /* fast memory writes are only safe when the target is running
1932                                          * from a sufficiently high clock (32 kHz is usually too slow)
1933                                          */
1934                                         if (arm7_9->fast_memory_access)
1935                                                 arm7_9_execute_fast_sys_speed(target);
1936                                         else
1937                                                 arm7_9_execute_sys_speed(target);
1938                                 }
1939
1940                                 num_accesses += thisrun_accesses;
1941                         }
1942                         break;
1943                 default:
1944                         ERROR("BUG: we shouldn't get here");
1945                         exit(-1);
1946                         break;
1947         }
1948
1949         /* Re-Set DBGACK */
1950         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
1951         embeddedice_store_reg(dbg_ctrl);
1952
1953         for (i=0; i<=last_reg; i++)
1954                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
1955
1956         arm7_9->read_xpsr(target, &cpsr, 0);
1957         if ((retval = jtag_execute_queue()) != ERROR_OK)
1958         {
1959                 ERROR("JTAG error while reading cpsr");
1960                 exit(-1);
1961         }
1962
1963         if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
1964         {
1965                 WARNING("memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
1966
1967                 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1968
1969                 return ERROR_TARGET_DATA_ABORT;
1970         }
1971
1972         return ERROR_OK;
1973 }
1974
1975 int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
1976 {
1977         armv4_5_common_t *armv4_5 = target->arch_info;
1978         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1979         enum armv4_5_state core_state = armv4_5->core_state;
1980         u32 r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
1981         u32 r1 = buf_get_u32(armv4_5->core_cache->reg_list[1].value, 0, 32);
1982         u32 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1983         int i;
1984
1985         u32 dcc_code[] =
1986         {
1987                 /* MRC      TST         BNE         MRC         STR         B */
1988                 0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9
1989         };
1990
1991         if (!arm7_9->dcc_downloads)
1992                 return target->type->write_memory(target, address, 4, count, buffer);
1993
1994         /* regrab previously allocated working_area, or allocate a new one */
1995         if (!arm7_9->dcc_working_area)
1996         {
1997                 u8 dcc_code_buf[6 * 4];
1998
1999                 /* make sure we have a working area */
2000                 if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
2001                 {
2002                         INFO("no working area available, falling back to memory writes");
2003                         return target->type->write_memory(target, address, 4, count, buffer);
2004                 }
2005
2006                 /* copy target instructions to target endianness */
2007                 for (i = 0; i < 6; i++)
2008                 {
2009                         target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
2010                 }
2011
2012                 /* write DCC code to working area */
2013                 target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf);
2014         }
2015
2016         buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address);
2017         armv4_5->core_cache->reg_list[0].valid = 1;
2018         armv4_5->core_cache->reg_list[0].dirty = 1;
2019         armv4_5->core_state = ARMV4_5_STATE_ARM;
2020
2021         arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
2022
2023         for (i = 0; i < count; i++)
2024         {
2025                 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], target_buffer_get_u32(target, buffer));
2026                 buffer += 4;
2027         }
2028
2029         target->type->halt(target);
2030
2031         while (target->state != TARGET_HALTED)
2032                 target->type->poll(target);
2033
2034         /* restore target state */
2035         buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, r0);
2036         armv4_5->core_cache->reg_list[0].valid = 1;
2037         armv4_5->core_cache->reg_list[0].dirty = 1;
2038         buf_set_u32(armv4_5->core_cache->reg_list[1].value, 0, 32, r1);
2039         armv4_5->core_cache->reg_list[1].valid = 1;
2040         armv4_5->core_cache->reg_list[1].dirty = 1;
2041         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, pc);
2042         armv4_5->core_cache->reg_list[15].valid = 1;
2043         armv4_5->core_cache->reg_list[15].dirty = 1;
2044         armv4_5->core_state = core_state;
2045
2046         return ERROR_OK;
2047 }
2048
2049 int arm7_9_register_commands(struct command_context_s *cmd_ctx)
2050 {
2051         command_t *arm7_9_cmd;
2052
2053         arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands");
2054
2055         register_command(cmd_ctx, arm7_9_cmd, "etm", handle_arm7_9_etm_command, COMMAND_CONFIG, NULL);
2056         register_command(cmd_ctx, arm7_9_cmd, "etb", handle_arm7_9_etb_command, COMMAND_CONFIG, NULL);
2057
2058         register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register <value> <not cpsr|spsr>");
2059         register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> <rotate> <not cpsr|spsr>");
2060
2061         register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register <num> <mode> <value>");
2062
2063         register_command(cmd_ctx, arm7_9_cmd, "sw_bkpts", handle_arm7_9_sw_bkpts_command, COMMAND_EXEC, "support for software breakpoints <enable|disable>");
2064         register_command(cmd_ctx, arm7_9_cmd, "force_hw_bkpts", handle_arm7_9_force_hw_bkpts_command, COMMAND_EXEC, "use hardware breakpoints for all breakpoints (disables sw breakpoint support) <enable|disable>");
2065         register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command,
2066                 COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable|disable>");
2067         register_command(cmd_ctx, arm7_9_cmd, "fast_writes", handle_arm7_9_fast_memory_access_command,
2068                  COMMAND_ANY, "(deprecated, see: arm7_9 fast_memory_access)");
2069         register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", handle_arm7_9_fast_memory_access_command,
2070                  COMMAND_ANY, "use fast memory accesses instead of slower but potentially unsafe slow accesses <enable|disable>");
2071         register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", handle_arm7_9_dcc_downloads_command,
2072                 COMMAND_ANY, "use DCC downloads for larger memory writes <enable|disable>");
2073
2074         armv4_5_register_commands(cmd_ctx);
2075
2076         return ERROR_OK;
2077 }
2078
2079 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2080 {
2081         u32 value;
2082         int spsr;
2083         int retval;
2084         target_t *target = get_current_target(cmd_ctx);
2085         armv4_5_common_t *armv4_5;
2086         arm7_9_common_t *arm7_9;
2087
2088         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2089         {
2090                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2091                 return ERROR_OK;
2092         }
2093
2094         if (target->state != TARGET_HALTED)
2095         {
2096                 command_print(cmd_ctx, "can't write registers while running");
2097                 return ERROR_OK;
2098         }
2099
2100         if (argc < 2)
2101         {
2102                 command_print(cmd_ctx, "usage: write_xpsr <value> <not cpsr|spsr>");
2103                 return ERROR_OK;
2104         }
2105
2106         value = strtoul(args[0], NULL, 0);
2107         spsr = strtol(args[1], NULL, 0);
2108
2109         /* if we're writing the CPSR, mask the T bit */
2110         if (!spsr)
2111                 value &= ~0x20;
2112
2113         arm7_9->write_xpsr(target, value, spsr);
2114         if ((retval = jtag_execute_queue()) != ERROR_OK)
2115         {
2116                 ERROR("JTAG error while writing to xpsr");
2117                 exit(-1);
2118         }
2119
2120         return ERROR_OK;
2121 }
2122
2123 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2124 {
2125         u32 value;
2126         int rotate;
2127         int spsr;
2128         int retval;
2129         target_t *target = get_current_target(cmd_ctx);
2130         armv4_5_common_t *armv4_5;
2131         arm7_9_common_t *arm7_9;
2132
2133         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2134         {
2135                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2136                 return ERROR_OK;
2137         }
2138
2139         if (target->state != TARGET_HALTED)
2140         {
2141                 command_print(cmd_ctx, "can't write registers while running");
2142                 return ERROR_OK;
2143         }
2144
2145         if (argc < 3)
2146         {
2147                 command_print(cmd_ctx, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr|spsr>");
2148                 return ERROR_OK;
2149         }
2150
2151         value = strtoul(args[0], NULL, 0);
2152         rotate = strtol(args[1], NULL, 0);
2153         spsr = strtol(args[2], NULL, 0);
2154
2155         arm7_9->write_xpsr_im8(target, value, rotate, spsr);
2156         if ((retval = jtag_execute_queue()) != ERROR_OK)
2157         {
2158                 ERROR("JTAG error while writing 8-bit immediate to xpsr");
2159                 exit(-1);
2160         }
2161
2162         return ERROR_OK;
2163 }
2164
2165 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2166 {
2167         u32 value;
2168         u32 mode;
2169         int num;
2170         target_t *target = get_current_target(cmd_ctx);
2171         armv4_5_common_t *armv4_5;
2172         arm7_9_common_t *arm7_9;
2173
2174         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2175         {
2176                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2177                 return ERROR_OK;
2178         }
2179
2180         if (target->state != TARGET_HALTED)
2181         {
2182                 command_print(cmd_ctx, "can't write registers while running");
2183                 return ERROR_OK;
2184         }
2185
2186         if (argc < 3)
2187         {
2188                 command_print(cmd_ctx, "usage: write_core_reg <num> <mode> <value>");
2189                 return ERROR_OK;
2190         }
2191
2192         num = strtol(args[0], NULL, 0);
2193         mode = strtoul(args[1], NULL, 0);
2194         value = strtoul(args[2], NULL, 0);
2195
2196         arm7_9_write_core_reg(target, num, mode, value);
2197
2198         return ERROR_OK;
2199 }
2200
2201 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2202 {
2203         target_t *target = get_current_target(cmd_ctx);
2204         armv4_5_common_t *armv4_5;
2205         arm7_9_common_t *arm7_9;
2206
2207         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2208         {
2209                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2210                 return ERROR_OK;
2211         }
2212
2213         if (argc == 0)
2214         {
2215                 command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2216                 return ERROR_OK;
2217         }
2218
2219         if (strcmp("enable", args[0]) == 0)
2220         {
2221                 if (arm7_9->sw_bkpts_use_wp)
2222                 {
2223                         arm7_9_enable_sw_bkpts(target);
2224                 }
2225                 else
2226                 {
2227                         arm7_9->sw_bkpts_enabled = 1;
2228                 }
2229         }
2230         else if (strcmp("disable", args[0]) == 0)
2231         {
2232                 if (arm7_9->sw_bkpts_use_wp)
2233                 {
2234                         arm7_9_disable_sw_bkpts(target);
2235                 }
2236                 else
2237                 {
2238                         arm7_9->sw_bkpts_enabled = 0;
2239                 }
2240         }
2241         else
2242         {
2243                 command_print(cmd_ctx, "usage: arm7_9 sw_bkpts <enable|disable>");
2244         }
2245
2246         command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2247
2248         return ERROR_OK;
2249 }
2250
2251 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2252 {
2253         target_t *target = get_current_target(cmd_ctx);
2254         armv4_5_common_t *armv4_5;
2255         arm7_9_common_t *arm7_9;
2256
2257         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2258         {
2259                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2260                 return ERROR_OK;
2261         }
2262
2263         if ((argc >= 1) && (strcmp("enable", args[0]) == 0))
2264         {
2265                 arm7_9->force_hw_bkpts = 1;
2266                 if (arm7_9->sw_bkpts_use_wp)
2267                 {
2268                         arm7_9_disable_sw_bkpts(target);
2269                 }
2270         }
2271         else if ((argc >= 1) && (strcmp("disable", args[0]) == 0))
2272         {
2273                 arm7_9->force_hw_bkpts = 0;
2274         }
2275         else
2276         {
2277                 command_print(cmd_ctx, "usage: arm7_9 force_hw_bkpts <enable|disable>");
2278         }
2279
2280         command_print(cmd_ctx, "force hardware breakpoints %s", (arm7_9->force_hw_bkpts) ? "enabled" : "disabled");
2281
2282         return ERROR_OK;
2283 }
2284
2285 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2286 {
2287         target_t *target = get_current_target(cmd_ctx);
2288         armv4_5_common_t *armv4_5;
2289         arm7_9_common_t *arm7_9;
2290
2291         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2292         {
2293                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2294                 return ERROR_OK;
2295         }
2296
2297         if (argc > 0)
2298         {
2299                 if (strcmp("enable", args[0]) == 0)
2300                 {
2301                         arm7_9->use_dbgrq = 1;
2302                 }
2303                 else if (strcmp("disable", args[0]) == 0)
2304                 {
2305                         arm7_9->use_dbgrq = 0;
2306                 }
2307                 else
2308                 {
2309                         command_print(cmd_ctx, "usage: arm7_9 dbgrq <enable|disable>");
2310                 }
2311         }
2312
2313         command_print(cmd_ctx, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
2314
2315         return ERROR_OK;
2316 }
2317
2318 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2319 {
2320         target_t *target = get_current_target(cmd_ctx);
2321         armv4_5_common_t *armv4_5;
2322         arm7_9_common_t *arm7_9;
2323
2324         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2325         {
2326                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2327                 return ERROR_OK;
2328         }
2329
2330         if (argc > 0)
2331         {
2332                 if (strcmp("enable", args[0]) == 0)
2333                 {
2334                         arm7_9->fast_memory_access = 1;
2335                 }
2336                 else if (strcmp("disable", args[0]) == 0)
2337                 {
2338                         arm7_9->fast_memory_access = 0;
2339                 }
2340                 else
2341                 {
2342                         command_print(cmd_ctx, "usage: arm7_9 fast_memory_access <enable|disable>");
2343                 }
2344         }
2345
2346         command_print(cmd_ctx, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");
2347
2348         return ERROR_OK;
2349 }
2350
2351 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2352 {
2353         target_t *target = get_current_target(cmd_ctx);
2354         armv4_5_common_t *armv4_5;
2355         arm7_9_common_t *arm7_9;
2356
2357         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2358         {
2359                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2360                 return ERROR_OK;
2361         }
2362
2363         if (argc > 0)
2364         {
2365                 if (strcmp("enable", args[0]) == 0)
2366                 {
2367                         arm7_9->dcc_downloads = 1;
2368                 }
2369                 else if (strcmp("disable", args[0]) == 0)
2370                 {
2371                         arm7_9->dcc_downloads = 0;
2372                 }
2373                 else
2374                 {
2375                         command_print(cmd_ctx, "usage: arm7_9 dcc_downloads <enable|disable>");
2376                 }
2377         }
2378
2379         command_print(cmd_ctx, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");
2380
2381         return ERROR_OK;
2382 }
2383
2384 int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2385 {
2386         target_t *target;
2387         armv4_5_common_t *armv4_5;
2388         arm7_9_common_t *arm7_9;
2389
2390         if (argc != 1)
2391         {
2392                 ERROR("incomplete 'arm7_9 etm <target>' command");
2393                 exit(-1);
2394         }
2395
2396         target = get_target_by_num(strtoul(args[0], NULL, 0));
2397
2398         if (!target)
2399         {
2400                 ERROR("target number '%s' not defined", args[0]);
2401                 exit(-1);
2402         }
2403
2404         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2405         {
2406                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2407                 return ERROR_OK;
2408         }
2409
2410         arm7_9->has_etm = 1;
2411
2412         return ERROR_OK;
2413 }
2414
2415 int handle_arm7_9_etb_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2416 {
2417         target_t *target;
2418         jtag_device_t *jtag_device;
2419         armv4_5_common_t *armv4_5;
2420         arm7_9_common_t *arm7_9;
2421
2422         if (argc != 2)
2423         {
2424                 ERROR("incomplete 'arm7_9 etb <target> <chain_pos>' command");
2425                 exit(-1);
2426         }
2427
2428         target = get_target_by_num(strtoul(args[0], NULL, 0));
2429
2430         if (!target)
2431         {
2432                 ERROR("target number '%s' not defined", args[0]);
2433                 exit(-1);
2434         }
2435
2436         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2437         {
2438                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2439                 return ERROR_OK;
2440         }
2441
2442         jtag_device = jtag_get_device(strtoul(args[1], NULL, 0));
2443
2444         if (!jtag_device)
2445         {
2446                 ERROR("jtag device number '%s' not defined", args[1]);
2447                 exit(-1);
2448         }
2449
2450         arm7_9->etb = malloc(sizeof(etb_t));
2451
2452         arm7_9->etb->chain_pos = strtoul(args[1], NULL, 0);
2453         arm7_9->etb->cur_scan_chain = -1;
2454         arm7_9->etb->reg_cache = NULL;
2455
2456         return ERROR_OK;
2457 }
2458
2459 int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
2460 {
2461         armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common;
2462
2463         arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
2464
2465         arm_jtag_setup_connection(&arm7_9->jtag_info);
2466         arm7_9->wp_available = 2;
2467         arm7_9->wp0_used = 0;
2468         arm7_9->wp1_used = 0;
2469         arm7_9->force_hw_bkpts = 0;
2470         arm7_9->use_dbgrq = 0;
2471
2472         arm7_9->has_etm = 0;
2473         arm7_9->etb = NULL;
2474         arm7_9->has_single_step = 0;
2475         arm7_9->has_monitor_mode = 0;
2476         arm7_9->has_vector_catch = 0;
2477
2478         arm7_9->reinit_embeddedice = 0;
2479
2480         arm7_9->dcc_working_area = NULL;
2481
2482         arm7_9->fast_memory_access = 0;
2483         arm7_9->dcc_downloads = 0;
2484
2485         jtag_register_event_callback(arm7_9_jtag_callback, target);
2486
2487         armv4_5->arch_info = arm7_9;
2488         armv4_5->read_core_reg = arm7_9_read_core_reg;
2489         armv4_5->write_core_reg = arm7_9_write_core_reg;
2490         armv4_5->full_context = arm7_9_full_context;
2491
2492         armv4_5_init_arch_info(target, armv4_5);
2493
2494         return ERROR_OK;
2495 }