1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2007,2008 Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * Copyright (C) 2008 by Hongtao Zheng *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program; if not, write to the *
26 * Free Software Foundation, Inc., *
27 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
28 ***************************************************************************/
33 #include "replacements.h"
35 #include "embeddedice.h"
37 #include "target_request.h"
42 #include "arm7_9_common.h"
43 #include "breakpoints.h"
44 #include "time_support.h"
45 #include "arm_simulator.h"
51 #include <sys/types.h>
56 int arm7_9_debug_entry(target_t *target);
57 int arm7_9_enable_sw_bkpts(struct target_s *target);
59 /* command handler forward declarations */
60 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
61 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
62 int handle_arm7_9_read_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
63 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
64 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
65 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
66 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
67 int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
70 static int arm7_9_clear_watchpoints(arm7_9_common_t *arm7_9)
72 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
73 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
74 arm7_9->sw_breakpoints_added = 0;
76 arm7_9->wp1_used = arm7_9->wp1_used_default;
77 arm7_9->wp_available = arm7_9->wp_available_max;
79 return jtag_execute_queue();
82 /* set up embedded ice registers */
83 static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9)
85 if (arm7_9->sw_breakpoints_added)
89 if (arm7_9->wp_available < 1)
91 LOG_WARNING("can't enable sw breakpoints with no watchpoint unit available");
92 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
94 arm7_9->wp_available--;
96 /* pick a breakpoint unit */
97 if (!arm7_9->wp0_used)
99 arm7_9->sw_breakpoints_added=1;
100 arm7_9->wp0_used = 3;
101 } else if (!arm7_9->wp1_used)
103 arm7_9->sw_breakpoints_added=2;
104 arm7_9->wp1_used = 3;
108 LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
112 if (arm7_9->sw_breakpoints_added==1)
114 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
115 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
116 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
117 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
118 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
120 else if (arm7_9->sw_breakpoints_added==2)
122 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
123 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
124 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
125 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
126 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
130 LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
134 return jtag_execute_queue();
137 /* set things up after a reset / on startup */
138 int arm7_9_setup(target_t *target)
140 armv4_5_common_t *armv4_5 = target->arch_info;
141 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
143 return arm7_9_clear_watchpoints(arm7_9);
147 int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p)
149 armv4_5_common_t *armv4_5 = target->arch_info;
150 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
152 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
157 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
162 *armv4_5_p = armv4_5;
168 /* we set up the breakpoint even if it is already set. Some action, e.g. reset
169 * might have erased the values in embedded ice
171 int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
173 armv4_5_common_t *armv4_5 = target->arch_info;
174 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
177 if (target->state != TARGET_HALTED)
179 LOG_WARNING("target not halted");
180 return ERROR_TARGET_NOT_HALTED;
183 if (breakpoint->type == BKPT_HARD)
185 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
186 u32 mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
187 if (breakpoint->set==1)
189 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
190 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
191 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);
192 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
193 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
195 else if (breakpoint->set==2)
197 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
198 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
199 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);
200 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
201 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
205 LOG_ERROR("BUG: no hardware comparator available");
209 retval=jtag_execute_queue();
211 else if (breakpoint->type == BKPT_SOFT)
213 if ((retval=arm7_9_set_software_breakpoints(arm7_9))!=ERROR_OK)
216 /* did we already set this breakpoint? */
220 if (breakpoint->length == 4)
222 u32 verify = 0xffffffff;
223 /* keep the original instruction in target endianness */
224 if ((retval = target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
228 /* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
229 if ((retval = target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt)) != ERROR_OK)
234 if ((retval = target->type->read_memory(target, breakpoint->address, 4, 1, (u8 *)&verify)) != ERROR_OK)
238 if (verify != arm7_9->arm_bkpt)
240 LOG_ERROR("Unable to set 32 bit software breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
247 /* keep the original instruction in target endianness */
248 if ((retval = target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
252 /* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
253 if ((retval = target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt)) != ERROR_OK)
258 if ((retval = target->type->read_memory(target, breakpoint->address, 2, 1, (u8 *)&verify)) != ERROR_OK)
262 if (verify != arm7_9->thumb_bkpt)
264 LOG_ERROR("Unable to set thumb software breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
275 int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
277 int retval = ERROR_OK;
279 armv4_5_common_t *armv4_5 = target->arch_info;
280 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
282 if (!breakpoint->set)
284 LOG_WARNING("breakpoint not set");
288 if (breakpoint->type == BKPT_HARD)
290 if (breakpoint->set == 1)
292 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
293 arm7_9->wp0_used = 0;
295 else if (breakpoint->set == 2)
297 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
298 arm7_9->wp1_used = 0;
300 retval = jtag_execute_queue();
305 /* restore original instruction (kept in target endianness) */
306 if (breakpoint->length == 4)
309 /* check that user program as not modified breakpoint instruction */
310 if ((retval = target->type->read_memory(target, breakpoint->address, 4, 1, (u8*)¤t_instr)) != ERROR_OK)
314 if (current_instr==arm7_9->arm_bkpt)
315 if ((retval = target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
323 /* check that user program as not modified breakpoint instruction */
324 if ((retval = target->type->read_memory(target, breakpoint->address, 2, 1, (u8*)¤t_instr)) != ERROR_OK)
328 if (current_instr==arm7_9->thumb_bkpt)
329 if ((retval = target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
340 int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
342 armv4_5_common_t *armv4_5 = target->arch_info;
343 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
345 if (target->state != TARGET_HALTED)
347 LOG_WARNING("target not halted");
348 return ERROR_TARGET_NOT_HALTED;
351 if (arm7_9->breakpoint_count==0)
353 /* make sure we don't have any dangling breakpoints. This is vital upon
354 * GDB connect/disconnect
356 arm7_9_clear_watchpoints(arm7_9);
359 if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1))
361 LOG_INFO("no watchpoint unit available for hardware breakpoint");
362 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
365 if ((breakpoint->length != 2) && (breakpoint->length != 4))
367 LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
368 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
371 if (breakpoint->type == BKPT_HARD)
373 arm7_9->wp_available--;
375 if (!arm7_9->wp0_used)
377 arm7_9->wp0_used = 1;
380 else if (!arm7_9->wp1_used)
382 arm7_9->wp1_used = 1;
387 LOG_ERROR("BUG: no hardware comparator available");
392 arm7_9->breakpoint_count++;
394 return arm7_9_set_breakpoint(target, breakpoint);
397 int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
399 int retval = ERROR_OK;
400 armv4_5_common_t *armv4_5 = target->arch_info;
401 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
403 if((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
408 if (breakpoint->type == BKPT_HARD)
409 arm7_9->wp_available++;
411 arm7_9->breakpoint_count--;
412 if (arm7_9->breakpoint_count==0)
414 /* make sure we don't have any dangling breakpoints */
415 if((retval = arm7_9_clear_watchpoints(arm7_9)) != ERROR_OK)
424 int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
426 int retval = ERROR_OK;
427 armv4_5_common_t *armv4_5 = target->arch_info;
428 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
432 mask = watchpoint->length - 1;
434 if (target->state != TARGET_HALTED)
436 LOG_WARNING("target not halted");
437 return ERROR_TARGET_NOT_HALTED;
440 if (watchpoint->rw == WPT_ACCESS)
445 if (!arm7_9->wp0_used)
447 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
448 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
449 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
450 if( watchpoint->mask != 0xffffffffu )
451 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
452 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
453 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
455 if((retval = jtag_execute_queue()) != ERROR_OK)
460 arm7_9->wp0_used = 2;
462 else if (!arm7_9->wp1_used)
464 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
465 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
466 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
467 if( watchpoint->mask != 0xffffffffu )
468 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
469 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
470 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
472 if((retval = jtag_execute_queue()) != ERROR_OK)
477 arm7_9->wp1_used = 2;
481 LOG_ERROR("BUG: no hardware comparator available");
488 int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
490 int retval = ERROR_OK;
491 armv4_5_common_t *armv4_5 = target->arch_info;
492 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
494 if (target->state != TARGET_HALTED)
496 LOG_WARNING("target not halted");
497 return ERROR_TARGET_NOT_HALTED;
500 if (!watchpoint->set)
502 LOG_WARNING("breakpoint not set");
506 if (watchpoint->set == 1)
508 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
509 if((retval = jtag_execute_queue()) != ERROR_OK)
513 arm7_9->wp0_used = 0;
515 else if (watchpoint->set == 2)
517 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
518 if((retval = jtag_execute_queue()) != ERROR_OK)
522 arm7_9->wp1_used = 0;
529 int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
531 armv4_5_common_t *armv4_5 = target->arch_info;
532 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
534 if (target->state != TARGET_HALTED)
536 LOG_WARNING("target not halted");
537 return ERROR_TARGET_NOT_HALTED;
540 if (arm7_9->wp_available < 1)
542 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
545 if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
547 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
550 arm7_9->wp_available--;
555 int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
557 int retval = ERROR_OK;
558 armv4_5_common_t *armv4_5 = target->arch_info;
559 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
563 if((retval = arm7_9_unset_watchpoint(target, watchpoint)) != ERROR_OK)
569 arm7_9->wp_available++;
577 int arm7_9_execute_sys_speed(struct target_s *target)
581 armv4_5_common_t *armv4_5 = target->arch_info;
582 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
583 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
584 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
586 /* set RESTART instruction */
587 jtag_add_end_state(TAP_RTI);
588 if (arm7_9->need_bypass_before_restart) {
589 arm7_9->need_bypass_before_restart = 0;
590 arm_jtag_set_instr(jtag_info, 0xf, NULL);
592 arm_jtag_set_instr(jtag_info, 0x4, NULL);
594 long long then=timeval_ms();
596 while (!(timeout=((timeval_ms()-then)>1000)))
598 /* read debug status register */
599 embeddedice_read_reg(dbg_stat);
600 if ((retval = jtag_execute_queue()) != ERROR_OK)
602 if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
603 && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
615 LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
616 return ERROR_TARGET_TIMEOUT;
622 int arm7_9_execute_fast_sys_speed(struct target_s *target)
625 static u8 check_value[4], check_mask[4];
627 armv4_5_common_t *armv4_5 = target->arch_info;
628 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
629 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
630 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
632 /* set RESTART instruction */
633 jtag_add_end_state(TAP_RTI);
634 if (arm7_9->need_bypass_before_restart) {
635 arm7_9->need_bypass_before_restart = 0;
636 arm_jtag_set_instr(jtag_info, 0xf, NULL);
638 arm_jtag_set_instr(jtag_info, 0x4, NULL);
642 /* check for DBGACK and SYSCOMP set (others don't care) */
644 /* NB! These are constants that must be available until after next jtag_execute() and
645 we evaluate the values upon first execution in lieu of setting up these constants
648 buf_set_u32(check_value, 0, 32, 0x9);
649 buf_set_u32(check_mask, 0, 32, 0x9);
653 /* read debug status register */
654 embeddedice_read_reg_w_check(dbg_stat, check_value, check_value);
659 int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer)
661 armv4_5_common_t *armv4_5 = target->arch_info;
662 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
663 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
665 int i, retval = ERROR_OK;
667 data = malloc(size * (sizeof(u32)));
669 retval = embeddedice_receive(jtag_info, data, size);
671 for (i = 0; i < size; i++)
673 h_u32_to_le(buffer + (i * 4), data[i]);
681 int arm7_9_handle_target_request(void *priv)
683 int retval = ERROR_OK;
684 target_t *target = priv;
685 if (!target->type->examined)
687 armv4_5_common_t *armv4_5 = target->arch_info;
688 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
689 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
690 reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
693 if (!target->dbg_msg_enabled)
696 if (target->state == TARGET_RUNNING)
698 /* read DCC control register */
699 embeddedice_read_reg(dcc_control);
700 if ((retval = jtag_execute_queue()) != ERROR_OK)
706 if (buf_get_u32(dcc_control->value, 1, 1) == 1)
710 if ((retval = embeddedice_receive(jtag_info, &request, 1)) != ERROR_OK)
714 if ((retval = target_request(target, request)) != ERROR_OK)
724 int arm7_9_poll(target_t *target)
727 armv4_5_common_t *armv4_5 = target->arch_info;
728 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
729 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
731 /* read debug status register */
732 embeddedice_read_reg(dbg_stat);
733 if ((retval = jtag_execute_queue()) != ERROR_OK)
738 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
740 /* LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));*/
741 if (target->state == TARGET_UNKNOWN)
743 target->state = TARGET_RUNNING;
744 LOG_WARNING("DBGACK set while target was in unknown state. Reset or initialize target.");
746 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
749 if (target->state == TARGET_RESET)
751 if (target->reset_halt)
753 if ((jtag_reset_config & RESET_SRST_PULLS_TRST)==0)
760 target->state = TARGET_HALTED;
762 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
767 reg_t *reg = register_get_by_name(target->reg_cache, "pc", 1);
768 u32 t=*((u32 *)reg->value);
771 LOG_ERROR("PC was not 0. Does this target need srst_pulls_trst?");
775 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
780 if (target->state == TARGET_DEBUG_RUNNING)
782 target->state = TARGET_HALTED;
783 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
786 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED)) != ERROR_OK)
791 if (target->state != TARGET_HALTED)
793 LOG_WARNING("DBGACK set, but the target did not end up in the halted stated %d", target->state);
798 if (target->state != TARGET_DEBUG_RUNNING)
799 target->state = TARGET_RUNNING;
806 Some -S targets (ARM966E-S in the STR912 isn't affected, ARM926EJ-S
807 in the LPC3180 and AT91SAM9260 is affected) completely stop the JTAG clock
808 while the core is held in reset(SRST). It isn't possible to program the halt
809 condition once reset was asserted, hence a hook that allows the target to set
810 up its reset-halt condition prior to asserting reset.
813 int arm7_9_assert_reset(target_t *target)
815 armv4_5_common_t *armv4_5 = target->arch_info;
816 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
817 LOG_DEBUG("target->state: %s",
818 Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name);
820 if (!(jtag_reset_config & RESET_HAS_SRST))
822 LOG_ERROR("Can't assert SRST");
826 if (target->reset_halt)
829 * Some targets do not support communication while SRST is asserted. We need to
830 * set up the reset vector catch here.
832 * If TRST is asserted, then these settings will be reset anyway, so setting them
835 if (arm7_9->has_vector_catch)
837 /* program vector catch register to catch reset vector */
838 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
842 /* program watchpoint unit to match on reset vector address */
843 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], 0x0);
844 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);
845 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
846 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
847 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
851 /* here we should issue a srst only, but we may have to assert trst as well */
852 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
854 jtag_add_reset(1, 1);
857 jtag_add_reset(0, 1);
861 target->state = TARGET_RESET;
862 jtag_add_sleep(50000);
864 armv4_5_invalidate_core_regs(target);
866 if ((target->reset_halt)&&((jtag_reset_config & RESET_SRST_PULLS_TRST)==0))
868 /* debug entry was already prepared in arm7_9_assert_reset() */
869 target->debug_reason = DBG_REASON_DBGRQ;
876 int arm7_9_deassert_reset(target_t *target)
879 LOG_DEBUG("target->state: %s",
880 Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name);
883 /* deassert reset lines */
884 jtag_add_reset(0, 0);
886 if (target->reset_halt&&(jtag_reset_config & RESET_SRST_PULLS_TRST)!=0)
888 LOG_WARNING("srst pulls trst - can not reset into halted mode. Issuing halt after reset.");
889 /* set up embedded ice registers again */
890 if ((retval=target->type->examine(target))!=ERROR_OK)
893 if ((retval=target_poll(target))!=ERROR_OK)
898 if ((retval=target_halt(target))!=ERROR_OK)
907 int arm7_9_clear_halt(target_t *target)
909 armv4_5_common_t *armv4_5 = target->arch_info;
910 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
911 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
913 /* we used DBGRQ only if we didn't come out of reset */
914 if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq)
916 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
918 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
919 embeddedice_store_reg(dbg_ctrl);
923 if (arm7_9->debug_entry_from_reset && arm7_9->has_vector_catch)
925 /* if we came out of reset, and vector catch is supported, we used
926 * vector catch to enter debug state
927 * restore the register in that case
929 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH]);
933 /* restore registers if watchpoint unit 0 was in use
935 if (arm7_9->wp0_used)
937 if (arm7_9->debug_entry_from_reset)
939 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]);
941 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
942 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
943 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
945 /* control value always has to be restored, as it was either disabled,
946 * or enabled with possibly different bits
948 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
955 int arm7_9_soft_reset_halt(struct target_s *target)
957 armv4_5_common_t *armv4_5 = target->arch_info;
958 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
959 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
960 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
964 if ((retval=target_halt(target))!=ERROR_OK)
967 long long then=timeval_ms();
969 while (!(timeout=((timeval_ms()-then)>1000)))
971 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0)
973 embeddedice_read_reg(dbg_stat);
974 if ((retval=jtag_execute_queue())!=ERROR_OK)
986 LOG_ERROR("Failed to halt CPU after 1 sec");
987 return ERROR_TARGET_TIMEOUT;
989 target->state = TARGET_HALTED;
991 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
992 * ensure that DBGRQ is cleared
994 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
995 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
996 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
997 embeddedice_store_reg(dbg_ctrl);
999 if ((retval = arm7_9_clear_halt(target)) != ERROR_OK)
1004 /* if the target is in Thumb state, change to ARM state */
1005 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
1007 u32 r0_thumb, pc_thumb;
1008 LOG_DEBUG("target entered debug from Thumb state, changing to ARM");
1009 /* Entered debug from Thumb mode */
1010 armv4_5->core_state = ARMV4_5_STATE_THUMB;
1011 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
1014 /* all register content is now invalid */
1015 if ((retval = armv4_5_invalidate_core_regs(target)) != ERROR_OK)
1020 /* SVC, ARM state, IRQ and FIQ disabled */
1021 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
1022 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
1023 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1025 /* start fetching from 0x0 */
1026 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
1027 armv4_5->core_cache->reg_list[15].dirty = 1;
1028 armv4_5->core_cache->reg_list[15].valid = 1;
1030 armv4_5->core_mode = ARMV4_5_MODE_SVC;
1031 armv4_5->core_state = ARMV4_5_STATE_ARM;
1033 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1036 /* reset registers */
1037 for (i = 0; i <= 14; i++)
1039 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, 0xffffffff);
1040 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
1041 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
1044 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
1052 int arm7_9_halt(target_t *target)
1054 if (target->state==TARGET_RESET)
1056 LOG_ERROR("BUG: arm7/9 does not support halt during reset. This is handled in arm7_9_assert_reset()");
1060 armv4_5_common_t *armv4_5 = target->arch_info;
1061 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1062 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1064 LOG_DEBUG("target->state: %s",
1065 Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name);
1067 if (target->state == TARGET_HALTED)
1069 LOG_DEBUG("target was already halted");
1073 if (target->state == TARGET_UNKNOWN)
1075 LOG_WARNING("target was in unknown state when halt was requested");
1078 if (arm7_9->use_dbgrq)
1080 /* program EmbeddedICE Debug Control Register to assert DBGRQ
1082 if (arm7_9->set_special_dbgrq) {
1083 arm7_9->set_special_dbgrq(target);
1085 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);
1086 embeddedice_store_reg(dbg_ctrl);
1091 /* program watchpoint unit to match on any address
1093 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1094 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1095 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1096 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1099 target->debug_reason = DBG_REASON_DBGRQ;
1104 int arm7_9_debug_entry(target_t *target)
1109 u32 r0_thumb, pc_thumb;
1112 /* get pointers to arch-specific information */
1113 armv4_5_common_t *armv4_5 = target->arch_info;
1114 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1115 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
1116 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1118 #ifdef _DEBUG_ARM7_9_
1122 if (arm7_9->pre_debug_entry)
1123 arm7_9->pre_debug_entry(target);
1125 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1126 * ensure that DBGRQ is cleared
1128 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
1129 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
1130 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
1131 embeddedice_store_reg(dbg_ctrl);
1133 if ((retval = arm7_9_clear_halt(target)) != ERROR_OK)
1138 if ((retval = jtag_execute_queue()) != ERROR_OK)
1143 if ((retval = arm7_9->examine_debug_reason(target)) != ERROR_OK)
1147 if (target->state != TARGET_HALTED)
1149 LOG_WARNING("target not halted");
1150 return ERROR_TARGET_NOT_HALTED;
1153 /* if the target is in Thumb state, change to ARM state */
1154 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
1156 LOG_DEBUG("target entered debug from Thumb state");
1157 /* Entered debug from Thumb mode */
1158 armv4_5->core_state = ARMV4_5_STATE_THUMB;
1159 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
1160 LOG_DEBUG("r0_thumb: 0x%8.8x, pc_thumb: 0x%8.8x", r0_thumb, pc_thumb);
1164 LOG_DEBUG("target entered debug from ARM state");
1165 /* Entered debug from ARM mode */
1166 armv4_5->core_state = ARMV4_5_STATE_ARM;
1169 for (i = 0; i < 16; i++)
1170 context_p[i] = &context[i];
1171 /* save core registers (r0 - r15 of current core mode) */
1172 arm7_9->read_core_regs(target, 0xffff, context_p);
1174 arm7_9->read_xpsr(target, &cpsr, 0);
1176 if ((retval = jtag_execute_queue()) != ERROR_OK)
1179 /* if the core has been executing in Thumb state, set the T bit */
1180 if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1183 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
1184 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1185 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1187 armv4_5->core_mode = cpsr & 0x1f;
1189 if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
1191 target->state = TARGET_UNKNOWN;
1192 LOG_ERROR("cpsr contains invalid mode value - communication failure");
1193 return ERROR_TARGET_FAILURE;
1196 LOG_DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
1198 if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1200 LOG_DEBUG("thumb state, applying fixups");
1201 context[0] = r0_thumb;
1202 context[15] = pc_thumb;
1203 } else if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1205 /* adjust value stored by STM */
1206 context[15] -= 3 * 4;
1209 if ((target->debug_reason == DBG_REASON_BREAKPOINT)
1210 || (target->debug_reason == DBG_REASON_SINGLESTEP)
1211 || (target->debug_reason == DBG_REASON_WATCHPOINT)
1212 || (target->debug_reason == DBG_REASON_WPTANDBKPT)
1213 || ((target->debug_reason == DBG_REASON_DBGRQ) && (arm7_9->use_dbgrq == 0)))
1214 context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1215 else if (target->debug_reason == DBG_REASON_DBGRQ)
1216 context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1219 LOG_ERROR("unknown debug reason: %i", target->debug_reason);
1222 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1225 for (i=0; i<=15; i++)
1227 LOG_DEBUG("r%i: 0x%8.8x", i, context[i]);
1228 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]);
1229 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
1230 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
1233 LOG_DEBUG("entered debug state at PC 0x%x", context[15]);
1235 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1238 /* exceptions other than USR & SYS have a saved program status register */
1239 if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS))
1242 arm7_9->read_xpsr(target, &spsr, 1);
1243 if ((retval = jtag_execute_queue()) != ERROR_OK)
1247 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, spsr);
1248 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
1249 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
1252 /* r0 and r15 (pc) have to be restored later */
1253 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
1254 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).valid;
1256 if ((retval = jtag_execute_queue()) != ERROR_OK)
1259 if (arm7_9->post_debug_entry)
1260 arm7_9->post_debug_entry(target);
1265 int arm7_9_full_context(target_t *target)
1269 armv4_5_common_t *armv4_5 = target->arch_info;
1270 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1274 if (target->state != TARGET_HALTED)
1276 LOG_WARNING("target not halted");
1277 return ERROR_TARGET_NOT_HALTED;
1280 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1283 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1284 * SYS shares registers with User, so we don't touch SYS
1286 for(i = 0; i < 6; i++)
1293 /* check if there are invalid registers in the current mode
1295 for (j = 0; j <= 16; j++)
1297 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1305 /* change processor mode (and mask T bit) */
1306 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1307 tmp_cpsr |= armv4_5_number_to_mode(i);
1309 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1311 for (j = 0; j < 15; j++)
1313 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1315 reg_p[j] = (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value;
1317 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
1318 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1322 /* if only the PSR is invalid, mask is all zeroes */
1324 arm7_9->read_core_regs(target, mask, reg_p);
1326 /* check if the PSR has to be read */
1327 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid == 0)
1329 arm7_9->read_xpsr(target, (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1);
1330 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
1331 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1336 /* restore processor mode (mask T bit) */
1337 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1339 if ((retval = jtag_execute_queue()) != ERROR_OK)
1346 int arm7_9_restore_context(target_t *target)
1348 armv4_5_common_t *armv4_5 = target->arch_info;
1349 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1351 armv4_5_core_reg_t *reg_arch_info;
1352 enum armv4_5_mode current_mode = armv4_5->core_mode;
1359 if (target->state != TARGET_HALTED)
1361 LOG_WARNING("target not halted");
1362 return ERROR_TARGET_NOT_HALTED;
1365 if (arm7_9->pre_restore_context)
1366 arm7_9->pre_restore_context(target);
1368 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1371 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1372 * SYS shares registers with User, so we don't touch SYS
1374 for (i = 0; i < 6; i++)
1376 LOG_DEBUG("examining %s mode", armv4_5_mode_strings[i]);
1379 /* check if there are dirty registers in the current mode
1381 for (j = 0; j <= 16; j++)
1383 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1384 reg_arch_info = reg->arch_info;
1385 if (reg->dirty == 1)
1387 if (reg->valid == 1)
1390 LOG_DEBUG("examining dirty reg: %s", reg->name);
1391 if ((reg_arch_info->mode != ARMV4_5_MODE_ANY)
1392 && (reg_arch_info->mode != current_mode)
1393 && !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS))
1394 && !((reg_arch_info->mode == ARMV4_5_MODE_SYS) && (armv4_5->core_mode == ARMV4_5_MODE_USR)))
1397 LOG_DEBUG("require mode change");
1402 LOG_ERROR("BUG: dirty register '%s', but no valid data", reg->name);
1417 /* change processor mode (mask T bit) */
1418 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1419 tmp_cpsr |= armv4_5_number_to_mode(i);
1421 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1422 current_mode = armv4_5_number_to_mode(i);
1425 for (j = 0; j <= 14; j++)
1427 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1428 reg_arch_info = reg->arch_info;
1431 if (reg->dirty == 1)
1433 regs[j] = buf_get_u32(reg->value, 0, 32);
1438 LOG_DEBUG("writing register %i of mode %s with value 0x%8.8x", j, armv4_5_mode_strings[i], regs[j]);
1444 arm7_9->write_core_regs(target, mask, regs);
1447 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
1448 reg_arch_info = reg->arch_info;
1449 if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
1451 LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8x", i, buf_get_u32(reg->value, 0, 32));
1452 arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
1457 if ((armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 0) && (armv4_5->core_mode != current_mode))
1459 /* restore processor mode (mask T bit) */
1462 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1463 tmp_cpsr |= armv4_5_number_to_mode(i);
1465 LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", tmp_cpsr);
1466 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1468 else if (armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 1)
1470 /* CPSR has been changed, full restore necessary (mask T bit) */
1471 LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1472 arm7_9->write_xpsr(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32) & ~0x20, 0);
1473 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1474 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1478 LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1479 arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1480 armv4_5->core_cache->reg_list[15].dirty = 0;
1482 if (arm7_9->post_restore_context)
1483 arm7_9->post_restore_context(target);
1488 int arm7_9_restart_core(struct target_s *target)
1490 armv4_5_common_t *armv4_5 = target->arch_info;
1491 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1492 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
1494 /* set RESTART instruction */
1495 jtag_add_end_state(TAP_RTI);
1496 if (arm7_9->need_bypass_before_restart) {
1497 arm7_9->need_bypass_before_restart = 0;
1498 arm_jtag_set_instr(jtag_info, 0xf, NULL);
1500 arm_jtag_set_instr(jtag_info, 0x4, NULL);
1502 jtag_add_runtest(1, TAP_RTI);
1503 return jtag_execute_queue();
1506 void arm7_9_enable_watchpoints(struct target_s *target)
1508 watchpoint_t *watchpoint = target->watchpoints;
1512 if (watchpoint->set == 0)
1513 arm7_9_set_watchpoint(target, watchpoint);
1514 watchpoint = watchpoint->next;
1518 void arm7_9_enable_breakpoints(struct target_s *target)
1520 breakpoint_t *breakpoint = target->breakpoints;
1522 /* set any pending breakpoints */
1525 arm7_9_set_breakpoint(target, breakpoint);
1526 breakpoint = breakpoint->next;
1531 int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
1533 armv4_5_common_t *armv4_5 = target->arch_info;
1534 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1535 breakpoint_t *breakpoint = target->breakpoints;
1536 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1537 int err, retval = ERROR_OK;
1541 if (target->state != TARGET_HALTED)
1543 LOG_WARNING("target not halted");
1544 return ERROR_TARGET_NOT_HALTED;
1547 if (!debug_execution)
1549 target_free_all_working_areas(target);
1552 /* current = 1: continue on current pc, otherwise continue at <address> */
1554 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1556 /* the front-end may request us not to handle breakpoints */
1557 if (handle_breakpoints)
1559 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1561 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
1562 if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
1567 LOG_DEBUG("enable single-step");
1568 arm7_9->enable_single_step(target);
1570 target->debug_reason = DBG_REASON_SINGLESTEP;
1572 if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
1577 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1578 arm7_9->branch_resume(target);
1579 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1581 arm7_9->branch_resume_thumb(target);
1585 LOG_ERROR("unhandled core state");
1589 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1590 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1591 err = arm7_9_execute_sys_speed(target);
1593 LOG_DEBUG("disable single-step");
1594 arm7_9->disable_single_step(target);
1596 if (err != ERROR_OK)
1598 if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
1602 target->state = TARGET_UNKNOWN;
1606 arm7_9_debug_entry(target);
1607 LOG_DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1609 LOG_DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
1610 if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
1617 /* enable any pending breakpoints and watchpoints */
1618 arm7_9_enable_breakpoints(target);
1619 arm7_9_enable_watchpoints(target);
1621 if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
1626 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1628 arm7_9->branch_resume(target);
1630 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1632 arm7_9->branch_resume_thumb(target);
1636 LOG_ERROR("unhandled core state");
1640 /* deassert DBGACK and INTDIS */
1641 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1642 /* INTDIS only when we really resume, not during debug execution */
1643 if (!debug_execution)
1644 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);
1645 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1647 if ((retval = arm7_9_restart_core(target)) != ERROR_OK)
1652 target->debug_reason = DBG_REASON_NOTHALTED;
1654 if (!debug_execution)
1656 /* registers are now invalid */
1657 armv4_5_invalidate_core_regs(target);
1658 target->state = TARGET_RUNNING;
1659 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
1666 target->state = TARGET_DEBUG_RUNNING;
1667 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED)) != ERROR_OK)
1673 LOG_DEBUG("target resumed");
1678 void arm7_9_enable_eice_step(target_t *target)
1680 armv4_5_common_t *armv4_5 = target->arch_info;
1681 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1685 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1688 if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
1691 target_read_u32(target, current_pc, ¤t_opcode);
1692 LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode);
1696 if(next_pc != current_pc)
1698 /* setup an inverse breakpoint on the current PC
1699 * - comparator 1 matches the current address
1700 * - rangeout from comparator 1 is connected to comparator 0 rangein
1701 * - comparator 0 matches any address, as long as rangein is low */
1702 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1703 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1704 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1705 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~(EICE_W_CTRL_RANGE|EICE_W_CTRL_nOPC) & 0xff);
1706 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], current_pc);
1707 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
1708 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
1709 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
1710 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1714 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1715 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1716 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
1717 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff);
1718 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], next_pc);
1719 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
1720 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
1721 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1722 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1726 void arm7_9_disable_eice_step(target_t *target)
1728 armv4_5_common_t *armv4_5 = target->arch_info;
1729 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1731 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
1732 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
1733 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
1734 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
1735 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE]);
1736 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK]);
1737 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK]);
1738 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK]);
1739 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
1742 int arm7_9_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
1744 armv4_5_common_t *armv4_5 = target->arch_info;
1745 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1746 breakpoint_t *breakpoint = NULL;
1749 if (target->state != TARGET_HALTED)
1751 LOG_WARNING("target not halted");
1752 return ERROR_TARGET_NOT_HALTED;
1755 /* current = 1: continue on current pc, otherwise continue at <address> */
1757 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1759 /* the front-end may request us not to handle breakpoints */
1760 if (handle_breakpoints)
1761 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1762 if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
1767 target->debug_reason = DBG_REASON_SINGLESTEP;
1769 if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
1774 arm7_9->enable_single_step(target);
1776 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1778 arm7_9->branch_resume(target);
1780 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1782 arm7_9->branch_resume_thumb(target);
1786 LOG_ERROR("unhandled core state");
1790 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
1795 err = arm7_9_execute_sys_speed(target);
1796 arm7_9->disable_single_step(target);
1798 /* registers are now invalid */
1799 armv4_5_invalidate_core_regs(target);
1801 if (err != ERROR_OK)
1803 target->state = TARGET_UNKNOWN;
1805 arm7_9_debug_entry(target);
1806 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
1810 LOG_DEBUG("target stepped");
1814 if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
1823 int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
1828 armv4_5_common_t *armv4_5 = target->arch_info;
1829 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1831 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1834 enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1836 if ((num < 0) || (num > 16))
1837 return ERROR_INVALID_ARGUMENTS;
1839 if ((mode != ARMV4_5_MODE_ANY)
1840 && (mode != armv4_5->core_mode)
1841 && (reg_mode != ARMV4_5_MODE_ANY))
1845 /* change processor mode (mask T bit) */
1846 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1849 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1852 if ((num >= 0) && (num <= 15))
1854 /* read a normal core register */
1855 reg_p[num] = &value;
1857 arm7_9->read_core_regs(target, 1 << num, reg_p);
1861 /* read a program status register
1862 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
1864 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1865 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1867 arm7_9->read_xpsr(target, &value, spsr);
1870 if ((retval = jtag_execute_queue()) != ERROR_OK)
1875 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1876 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1877 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).value, 0, 32, value);
1879 if ((mode != ARMV4_5_MODE_ANY)
1880 && (mode != armv4_5->core_mode)
1881 && (reg_mode != ARMV4_5_MODE_ANY)) {
1882 /* restore processor mode (mask T bit) */
1883 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1890 int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value)
1893 armv4_5_common_t *armv4_5 = target->arch_info;
1894 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1896 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1899 enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1901 if ((num < 0) || (num > 16))
1902 return ERROR_INVALID_ARGUMENTS;
1904 if ((mode != ARMV4_5_MODE_ANY)
1905 && (mode != armv4_5->core_mode)
1906 && (reg_mode != ARMV4_5_MODE_ANY)) {
1909 /* change processor mode (mask T bit) */
1910 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1913 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1916 if ((num >= 0) && (num <= 15))
1918 /* write a normal core register */
1921 arm7_9->write_core_regs(target, 1 << num, reg);
1925 /* write a program status register
1926 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
1928 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1929 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1931 /* if we're writing the CPSR, mask the T bit */
1935 arm7_9->write_xpsr(target, value, spsr);
1938 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1939 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1941 if ((mode != ARMV4_5_MODE_ANY)
1942 && (mode != armv4_5->core_mode)
1943 && (reg_mode != ARMV4_5_MODE_ANY)) {
1944 /* restore processor mode (mask T bit) */
1945 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1948 return jtag_execute_queue();
1951 int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1953 armv4_5_common_t *armv4_5 = target->arch_info;
1954 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1957 int num_accesses = 0;
1958 int thisrun_accesses;
1964 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1966 if (target->state != TARGET_HALTED)
1968 LOG_WARNING("target not halted");
1969 return ERROR_TARGET_NOT_HALTED;
1972 /* sanitize arguments */
1973 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1974 return ERROR_INVALID_ARGUMENTS;
1976 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1977 return ERROR_TARGET_UNALIGNED_ACCESS;
1979 /* load the base register with the address of the first word */
1981 arm7_9->write_core_regs(target, 0x1, reg);
1988 while (num_accesses < count)
1991 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1992 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1994 if (last_reg <= thisrun_accesses)
1995 last_reg = thisrun_accesses;
1997 arm7_9->load_word_regs(target, reg_list);
1999 /* fast memory reads are only safe when the target is running
2000 * from a sufficiently high clock (32 kHz is usually too slow)
2002 if (arm7_9->fast_memory_access)
2003 arm7_9_execute_fast_sys_speed(target);
2005 arm7_9_execute_sys_speed(target);
2007 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4);
2009 /* advance buffer, count number of accesses */
2010 buffer += thisrun_accesses * 4;
2011 num_accesses += thisrun_accesses;
2020 while (num_accesses < count)
2023 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2024 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2026 for (i = 1; i <= thisrun_accesses; i++)
2030 arm7_9->load_hword_reg(target, i);
2031 /* fast memory reads are only safe when the target is running
2032 * from a sufficiently high clock (32 kHz is usually too slow)
2034 if (arm7_9->fast_memory_access)
2035 retval = arm7_9_execute_fast_sys_speed(target);
2037 retval = arm7_9_execute_sys_speed(target);
2038 if(retval != ERROR_OK)
2045 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2);
2047 /* advance buffer, count number of accesses */
2048 buffer += thisrun_accesses * 2;
2049 num_accesses += thisrun_accesses;
2058 while (num_accesses < count)
2061 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2062 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2064 for (i = 1; i <= thisrun_accesses; i++)
2068 arm7_9->load_byte_reg(target, i);
2069 /* fast memory reads are only safe when the target is running
2070 * from a sufficiently high clock (32 kHz is usually too slow)
2072 if (arm7_9->fast_memory_access)
2073 retval = arm7_9_execute_fast_sys_speed(target);
2075 retval = arm7_9_execute_sys_speed(target);
2076 if(retval != ERROR_OK)
2082 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1);
2084 /* advance buffer, count number of accesses */
2085 buffer += thisrun_accesses * 1;
2086 num_accesses += thisrun_accesses;
2095 LOG_ERROR("BUG: we shouldn't get here");
2100 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
2103 for (i=0; i<=last_reg; i++)
2104 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
2106 arm7_9->read_xpsr(target, &cpsr, 0);
2107 if ((retval = jtag_execute_queue()) != ERROR_OK)
2109 LOG_ERROR("JTAG error while reading cpsr");
2110 return ERROR_TARGET_DATA_ABORT;
2113 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
2115 LOG_WARNING("memory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
2117 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
2119 return ERROR_TARGET_DATA_ABORT;
2125 int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
2127 armv4_5_common_t *armv4_5 = target->arch_info;
2128 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
2129 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
2132 int num_accesses = 0;
2133 int thisrun_accesses;
2139 #ifdef _DEBUG_ARM7_9_
2140 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
2143 if (target->state != TARGET_HALTED)
2145 LOG_WARNING("target not halted");
2146 return ERROR_TARGET_NOT_HALTED;
2149 /* sanitize arguments */
2150 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
2151 return ERROR_INVALID_ARGUMENTS;
2153 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
2154 return ERROR_TARGET_UNALIGNED_ACCESS;
2156 /* load the base register with the address of the first word */
2158 arm7_9->write_core_regs(target, 0x1, reg);
2160 /* Clear DBGACK, to make sure memory fetches work as expected */
2161 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
2162 embeddedice_store_reg(dbg_ctrl);
2167 while (num_accesses < count)
2170 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2171 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2173 for (i = 1; i <= thisrun_accesses; i++)
2177 reg[i] = target_buffer_get_u32(target, buffer);
2181 arm7_9->write_core_regs(target, reg_list, reg);
2183 arm7_9->store_word_regs(target, reg_list);
2185 /* fast memory writes are only safe when the target is running
2186 * from a sufficiently high clock (32 kHz is usually too slow)
2188 if (arm7_9->fast_memory_access)
2189 retval = arm7_9_execute_fast_sys_speed(target);
2191 retval = arm7_9_execute_sys_speed(target);
2192 if(retval != ERROR_OK)
2197 num_accesses += thisrun_accesses;
2201 while (num_accesses < count)
2204 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2205 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2207 for (i = 1; i <= thisrun_accesses; i++)
2211 reg[i] = target_buffer_get_u16(target, buffer) & 0xffff;
2215 arm7_9->write_core_regs(target, reg_list, reg);
2217 for (i = 1; i <= thisrun_accesses; i++)
2219 arm7_9->store_hword_reg(target, i);
2221 /* fast memory writes are only safe when the target is running
2222 * from a sufficiently high clock (32 kHz is usually too slow)
2224 if (arm7_9->fast_memory_access)
2225 retval = arm7_9_execute_fast_sys_speed(target);
2227 retval = arm7_9_execute_sys_speed(target);
2228 if(retval != ERROR_OK)
2234 num_accesses += thisrun_accesses;
2238 while (num_accesses < count)
2241 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2242 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2244 for (i = 1; i <= thisrun_accesses; i++)
2248 reg[i] = *buffer++ & 0xff;
2251 arm7_9->write_core_regs(target, reg_list, reg);
2253 for (i = 1; i <= thisrun_accesses; i++)
2255 arm7_9->store_byte_reg(target, i);
2256 /* fast memory writes are only safe when the target is running
2257 * from a sufficiently high clock (32 kHz is usually too slow)
2259 if (arm7_9->fast_memory_access)
2260 retval = arm7_9_execute_fast_sys_speed(target);
2262 retval = arm7_9_execute_sys_speed(target);
2263 if(retval != ERROR_OK)
2270 num_accesses += thisrun_accesses;
2274 LOG_ERROR("BUG: we shouldn't get here");
2280 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
2281 embeddedice_store_reg(dbg_ctrl);
2283 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
2286 for (i=0; i<=last_reg; i++)
2287 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
2289 arm7_9->read_xpsr(target, &cpsr, 0);
2290 if ((retval = jtag_execute_queue()) != ERROR_OK)
2292 LOG_ERROR("JTAG error while reading cpsr");
2293 return ERROR_TARGET_DATA_ABORT;
2296 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
2298 LOG_WARNING("memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
2300 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
2302 return ERROR_TARGET_DATA_ABORT;
2308 static int dcc_count;
2309 static u8 *dcc_buffer;
2312 static int arm7_9_dcc_completion(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info)
2314 int retval = ERROR_OK;
2315 armv4_5_common_t *armv4_5 = target->arch_info;
2316 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
2318 if ((retval=target_wait_state(target, TARGET_DEBUG_RUNNING, 500))!=ERROR_OK)
2321 int little=target->endianness==TARGET_LITTLE_ENDIAN;
2322 int count=dcc_count;
2323 u8 *buffer=dcc_buffer;
2326 /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
2327 core function repeated.
2329 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2332 embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
2333 u8 reg_addr = ice_reg->addr & 0x1f;
2334 int chain_pos = ice_reg->jtag_info->chain_pos;
2336 embeddedice_write_dcc(chain_pos, reg_addr, buffer, little, count-2);
2337 buffer += (count-2)*4;
2339 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2343 for (i = 0; i < count; i++)
2345 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2350 if((retval = target_halt(target))!= ERROR_OK)
2354 return target_wait_state(target, TARGET_HALTED, 500);
2358 static const u32 dcc_code[] =
2360 /* MRC TST BNE MRC STR B */
2361 0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9
2364 int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info));
2367 int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
2370 armv4_5_common_t *armv4_5 = target->arch_info;
2371 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
2374 if (!arm7_9->dcc_downloads)
2375 return target->type->write_memory(target, address, 4, count, buffer);
2377 /* regrab previously allocated working_area, or allocate a new one */
2378 if (!arm7_9->dcc_working_area)
2380 u8 dcc_code_buf[6 * 4];
2382 /* make sure we have a working area */
2383 if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
2385 LOG_INFO("no working area available, falling back to memory writes");
2386 return target->type->write_memory(target, address, 4, count, buffer);
2389 /* copy target instructions to target endianness */
2390 for (i = 0; i < 6; i++)
2392 target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
2395 /* write DCC code to working area */
2396 if ((retval = target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf)) != ERROR_OK)
2402 armv4_5_algorithm_t armv4_5_info;
2403 reg_param_t reg_params[1];
2405 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
2406 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
2407 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
2409 init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT);
2411 buf_set_u32(reg_params[0].value, 0, 32, address);
2413 //armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params,
2414 // int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info))
2417 retval = armv4_5_run_algorithm_inner(target, 0, NULL, 1, reg_params,
2418 arm7_9->dcc_working_area->address, arm7_9->dcc_working_area->address+6*4, 20*1000, &armv4_5_info, arm7_9_dcc_completion);
2420 if (retval==ERROR_OK)
2422 u32 endaddress=buf_get_u32(reg_params[0].value, 0, 32);
2423 if (endaddress!=(address+count*4))
2425 LOG_ERROR("DCC write failed, expected end address 0x%08x got 0x%0x", (address+count*4), endaddress);
2430 destroy_reg_param(®_params[0]);
2435 int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
2437 working_area_t *crc_algorithm;
2438 armv4_5_algorithm_t armv4_5_info;
2439 reg_param_t reg_params[2];
2442 u32 arm7_9_crc_code[] = {
2443 0xE1A02000, /* mov r2, r0 */
2444 0xE3E00000, /* mov r0, #0xffffffff */
2445 0xE1A03001, /* mov r3, r1 */
2446 0xE3A04000, /* mov r4, #0 */
2447 0xEA00000B, /* b ncomp */
2449 0xE7D21004, /* ldrb r1, [r2, r4] */
2450 0xE59F7030, /* ldr r7, CRC32XOR */
2451 0xE0200C01, /* eor r0, r0, r1, asl 24 */
2452 0xE3A05000, /* mov r5, #0 */
2454 0xE3500000, /* cmp r0, #0 */
2455 0xE1A06080, /* mov r6, r0, asl #1 */
2456 0xE2855001, /* add r5, r5, #1 */
2457 0xE1A00006, /* mov r0, r6 */
2458 0xB0260007, /* eorlt r0, r6, r7 */
2459 0xE3550008, /* cmp r5, #8 */
2460 0x1AFFFFF8, /* bne loop */
2461 0xE2844001, /* add r4, r4, #1 */
2463 0xE1540003, /* cmp r4, r3 */
2464 0x1AFFFFF1, /* bne nbyte */
2466 0xEAFFFFFE, /* b end */
2467 0x04C11DB7 /* CRC32XOR: .word 0x04C11DB7 */
2472 if (target_alloc_working_area(target, sizeof(arm7_9_crc_code), &crc_algorithm) != ERROR_OK)
2474 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2477 /* convert flash writing code into a buffer in target endianness */
2478 for (i = 0; i < (sizeof(arm7_9_crc_code)/sizeof(u32)); i++)
2480 if ((retval=target_write_u32(target, crc_algorithm->address + i*sizeof(u32), arm7_9_crc_code[i]))!=ERROR_OK)
2486 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
2487 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
2488 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
2490 init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT);
2491 init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
2493 buf_set_u32(reg_params[0].value, 0, 32, address);
2494 buf_set_u32(reg_params[1].value, 0, 32, count);
2496 if ((retval = target->type->run_algorithm(target, 0, NULL, 2, reg_params,
2497 crc_algorithm->address, crc_algorithm->address + (sizeof(arm7_9_crc_code) - 8), 20000, &armv4_5_info)) != ERROR_OK)
2499 LOG_ERROR("error executing arm7_9 crc algorithm");
2500 destroy_reg_param(®_params[0]);
2501 destroy_reg_param(®_params[1]);
2502 target_free_working_area(target, crc_algorithm);
2506 *checksum = buf_get_u32(reg_params[0].value, 0, 32);
2508 destroy_reg_param(®_params[0]);
2509 destroy_reg_param(®_params[1]);
2511 target_free_working_area(target, crc_algorithm);
2516 int arm7_9_blank_check_memory(struct target_s *target, u32 address, u32 count, u32* blank)
2518 working_area_t *erase_check_algorithm;
2519 reg_param_t reg_params[3];
2520 armv4_5_algorithm_t armv4_5_info;
2524 u32 erase_check_code[] =
2527 0xe4d03001, /* ldrb r3, [r0], #1 */
2528 0xe0022003, /* and r2, r2, r3 */
2529 0xe2511001, /* subs r1, r1, #1 */
2530 0x1afffffb, /* bne loop */
2532 0xeafffffe /* b end */
2535 /* make sure we have a working area */
2536 if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK)
2538 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2541 /* convert flash writing code into a buffer in target endianness */
2542 for (i = 0; i < (sizeof(erase_check_code)/sizeof(u32)); i++)
2543 if ((retval = target_write_u32(target, erase_check_algorithm->address + i*sizeof(u32), erase_check_code[i])) != ERROR_OK)
2548 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
2549 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
2550 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
2552 init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
2553 buf_set_u32(reg_params[0].value, 0, 32, address);
2555 init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
2556 buf_set_u32(reg_params[1].value, 0, 32, count);
2558 init_reg_param(®_params[2], "r2", 32, PARAM_IN_OUT);
2559 buf_set_u32(reg_params[2].value, 0, 32, 0xff);
2561 if ((retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params,
2562 erase_check_algorithm->address, erase_check_algorithm->address + (sizeof(erase_check_code) - 4), 10000, &armv4_5_info)) != ERROR_OK)
2564 destroy_reg_param(®_params[0]);
2565 destroy_reg_param(®_params[1]);
2566 destroy_reg_param(®_params[2]);
2567 target_free_working_area(target, erase_check_algorithm);
2571 *blank = buf_get_u32(reg_params[2].value, 0, 32);
2573 destroy_reg_param(®_params[0]);
2574 destroy_reg_param(®_params[1]);
2575 destroy_reg_param(®_params[2]);
2577 target_free_working_area(target, erase_check_algorithm);
2582 int arm7_9_register_commands(struct command_context_s *cmd_ctx)
2584 command_t *arm7_9_cmd;
2586 arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands");
2588 register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register <value> <not cpsr|spsr>");
2589 register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> <rotate> <not cpsr|spsr>");
2591 register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register <num> <mode> <value>");
2593 register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command,
2594 COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable|disable>");
2595 register_command(cmd_ctx, arm7_9_cmd, "fast_writes", handle_arm7_9_fast_memory_access_command,
2596 COMMAND_ANY, "(deprecated, see: arm7_9 fast_memory_access)");
2597 register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", handle_arm7_9_fast_memory_access_command,
2598 COMMAND_ANY, "use fast memory accesses instead of slower but potentially unsafe slow accesses <enable|disable>");
2599 register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", handle_arm7_9_dcc_downloads_command,
2600 COMMAND_ANY, "use DCC downloads for larger memory writes <enable|disable>");
2602 armv4_5_register_commands(cmd_ctx);
2604 etm_register_commands(cmd_ctx);
2609 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2614 target_t *target = get_current_target(cmd_ctx);
2615 armv4_5_common_t *armv4_5;
2616 arm7_9_common_t *arm7_9;
2618 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2620 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2624 if (target->state != TARGET_HALTED)
2626 command_print(cmd_ctx, "can't write registers while running");
2632 command_print(cmd_ctx, "usage: write_xpsr <value> <not cpsr|spsr>");
2636 value = strtoul(args[0], NULL, 0);
2637 spsr = strtol(args[1], NULL, 0);
2639 /* if we're writing the CPSR, mask the T bit */
2643 arm7_9->write_xpsr(target, value, spsr);
2644 if ((retval = jtag_execute_queue()) != ERROR_OK)
2646 LOG_ERROR("JTAG error while writing to xpsr");
2653 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2659 target_t *target = get_current_target(cmd_ctx);
2660 armv4_5_common_t *armv4_5;
2661 arm7_9_common_t *arm7_9;
2663 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2665 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2669 if (target->state != TARGET_HALTED)
2671 command_print(cmd_ctx, "can't write registers while running");
2677 command_print(cmd_ctx, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr|spsr>");
2681 value = strtoul(args[0], NULL, 0);
2682 rotate = strtol(args[1], NULL, 0);
2683 spsr = strtol(args[2], NULL, 0);
2685 arm7_9->write_xpsr_im8(target, value, rotate, spsr);
2686 if ((retval = jtag_execute_queue()) != ERROR_OK)
2688 LOG_ERROR("JTAG error while writing 8-bit immediate to xpsr");
2695 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2700 target_t *target = get_current_target(cmd_ctx);
2701 armv4_5_common_t *armv4_5;
2702 arm7_9_common_t *arm7_9;
2704 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2706 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2710 if (target->state != TARGET_HALTED)
2712 command_print(cmd_ctx, "can't write registers while running");
2718 command_print(cmd_ctx, "usage: write_core_reg <num> <mode> <value>");
2722 num = strtol(args[0], NULL, 0);
2723 mode = strtoul(args[1], NULL, 0);
2724 value = strtoul(args[2], NULL, 0);
2726 return arm7_9_write_core_reg(target, num, mode, value);
2731 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2733 target_t *target = get_current_target(cmd_ctx);
2734 armv4_5_common_t *armv4_5;
2735 arm7_9_common_t *arm7_9;
2737 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2739 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2745 if (strcmp("enable", args[0]) == 0)
2747 arm7_9->use_dbgrq = 1;
2749 else if (strcmp("disable", args[0]) == 0)
2751 arm7_9->use_dbgrq = 0;
2755 command_print(cmd_ctx, "usage: arm7_9 dbgrq <enable|disable>");
2759 command_print(cmd_ctx, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
2764 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2766 target_t *target = get_current_target(cmd_ctx);
2767 armv4_5_common_t *armv4_5;
2768 arm7_9_common_t *arm7_9;
2770 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2772 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2778 if (strcmp("enable", args[0]) == 0)
2780 arm7_9->fast_memory_access = 1;
2782 else if (strcmp("disable", args[0]) == 0)
2784 arm7_9->fast_memory_access = 0;
2788 command_print(cmd_ctx, "usage: arm7_9 fast_memory_access <enable|disable>");
2792 command_print(cmd_ctx, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");
2797 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2799 target_t *target = get_current_target(cmd_ctx);
2800 armv4_5_common_t *armv4_5;
2801 arm7_9_common_t *arm7_9;
2803 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2805 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2811 if (strcmp("enable", args[0]) == 0)
2813 arm7_9->dcc_downloads = 1;
2815 else if (strcmp("disable", args[0]) == 0)
2817 arm7_9->dcc_downloads = 0;
2821 command_print(cmd_ctx, "usage: arm7_9 dcc_downloads <enable|disable>");
2825 command_print(cmd_ctx, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");
2830 int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
2832 int retval = ERROR_OK;
2833 armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common;
2835 arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
2837 if((retval = arm_jtag_setup_connection(&arm7_9->jtag_info)) != ERROR_OK)
2842 arm7_9->wp_available = 0; /* this is set up in arm7_9_clear_watchpoints() */
2843 arm7_9->wp_available_max = 2;
2844 arm7_9->sw_breakpoints_added = 0;
2845 arm7_9->breakpoint_count = 0;
2846 arm7_9->wp0_used = 0;
2847 arm7_9->wp1_used = 0;
2848 arm7_9->wp1_used_default = 0;
2849 arm7_9->use_dbgrq = 0;
2851 arm7_9->etm_ctx = NULL;
2852 arm7_9->has_single_step = 0;
2853 arm7_9->has_monitor_mode = 0;
2854 arm7_9->has_vector_catch = 0;
2856 arm7_9->debug_entry_from_reset = 0;
2858 arm7_9->dcc_working_area = NULL;
2860 arm7_9->fast_memory_access = fast_and_dangerous;
2861 arm7_9->dcc_downloads = fast_and_dangerous;
2863 arm7_9->need_bypass_before_restart = 0;
2865 armv4_5->arch_info = arm7_9;
2866 armv4_5->read_core_reg = arm7_9_read_core_reg;
2867 armv4_5->write_core_reg = arm7_9_write_core_reg;
2868 armv4_5->full_context = arm7_9_full_context;
2870 if((retval = armv4_5_init_arch_info(target, armv4_5)) != ERROR_OK)
2875 if((retval = target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target)) != ERROR_OK)