1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2007,2008 Øyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
32 #include "arm7_9_common.h"
36 #include "embeddedice.h"
46 #define _DEBUG_INSTRUCTION_EXECUTION_
49 /* forward declarations */
51 int arm7tdmi_target_create(struct target_s *target,Jim_Interp *interp);
52 int arm7tdmi_quit(void);
54 /* target function declarations */
55 int arm7tdmi_poll(struct target_s *target);
56 int arm7tdmi_halt(target_t *target);
58 target_type_t arm7tdmi_target =
63 .arch_state = armv4_5_arch_state,
65 .target_request_data = arm7_9_target_request_data,
68 .resume = arm7_9_resume,
71 .assert_reset = arm7_9_assert_reset,
72 .deassert_reset = arm7_9_deassert_reset,
73 .soft_reset_halt = arm7_9_soft_reset_halt,
75 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
77 .read_memory = arm7_9_read_memory,
78 .write_memory = arm7_9_write_memory,
79 .bulk_write_memory = arm7_9_bulk_write_memory,
80 .checksum_memory = arm7_9_checksum_memory,
81 .blank_check_memory = arm7_9_blank_check_memory,
83 .run_algorithm = armv4_5_run_algorithm,
85 .add_breakpoint = arm7_9_add_breakpoint,
86 .remove_breakpoint = arm7_9_remove_breakpoint,
87 .add_watchpoint = arm7_9_add_watchpoint,
88 .remove_watchpoint = arm7_9_remove_watchpoint,
90 .register_commands = arm7tdmi_register_commands,
91 .target_create = arm7tdmi_target_create,
92 .init_target = arm7tdmi_init_target,
93 .examine = arm7tdmi_examine,
97 int arm7tdmi_examine_debug_reason(target_t *target)
99 int retval = ERROR_OK;
100 /* get pointers to arch-specific information */
101 armv4_5_common_t *armv4_5 = target->arch_info;
102 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
104 /* only check the debug reason if we don't know it already */
105 if ((target->debug_reason != DBG_REASON_DBGRQ)
106 && (target->debug_reason != DBG_REASON_SINGLESTEP))
108 scan_field_t fields[2];
112 jtag_add_end_state(TAP_DRPAUSE);
114 fields[0].tap = arm7_9->jtag_info.tap;
115 fields[0].num_bits = 1;
116 fields[0].out_value = NULL;
117 fields[0].in_value = &breakpoint;
118 fields[0].in_handler = NULL;
120 fields[1].tap = arm7_9->jtag_info.tap;
121 fields[1].num_bits = 32;
122 fields[1].out_value = NULL;
123 fields[1].in_value = databus;
124 fields[1].in_handler = NULL;
126 if((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK)
130 arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
132 jtag_add_dr_scan(2, fields, TAP_DRPAUSE);
133 if((retval = jtag_execute_queue()) != ERROR_OK)
138 fields[0].in_value = NULL;
139 fields[0].out_value = &breakpoint;
140 fields[1].in_value = NULL;
141 fields[1].out_value = databus;
143 jtag_add_dr_scan(2, fields, TAP_DRPAUSE);
146 target->debug_reason = DBG_REASON_WATCHPOINT;
148 target->debug_reason = DBG_REASON_BREAKPOINT;
154 static int arm7tdmi_num_bits[]={1, 32};
155 static __inline int arm7tdmi_clock_out_inner(arm_jtag_t *jtag_info, u32 out, int breakpoint)
157 u32 values[2]={breakpoint, flip_u32(out, 32)};
159 jtag_add_dr_out(jtag_info->tap,
165 jtag_add_runtest(0, TAP_INVALID);
170 /* put an instruction in the ARM7TDMI pipeline or write the data bus, and optionally read data */
171 static __inline int arm7tdmi_clock_out(arm_jtag_t *jtag_info, u32 out, u32 *deprecated, int breakpoint)
173 jtag_add_end_state(TAP_DRPAUSE);
174 arm_jtag_scann(jtag_info, 0x1);
175 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
177 return arm7tdmi_clock_out_inner(jtag_info, out, breakpoint);
180 /* clock the target, reading the databus */
181 int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
183 int retval = ERROR_OK;
184 scan_field_t fields[2];
186 jtag_add_end_state(TAP_DRPAUSE);
187 if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
191 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
193 fields[0].tap = jtag_info->tap;
194 fields[0].num_bits = 1;
195 fields[0].out_value = NULL;
196 fields[0].in_value = NULL;
197 fields[0].in_handler = NULL;
200 fields[1].tap = jtag_info->tap;
201 fields[1].num_bits = 32;
202 fields[1].out_value = NULL;
204 fields[1].in_value = tmp;
205 fields[1].in_handler = NULL;
207 jtag_add_dr_scan_now(2, fields, TAP_INVALID);
209 if (jtag_error==ERROR_OK)
211 *in=flip_u32(le_to_h_u32(tmp), 32);
214 jtag_add_runtest(0, TAP_INVALID);
216 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
218 if((retval = jtag_execute_queue()) != ERROR_OK)
225 LOG_DEBUG("in: 0x%8.8x", *in);
229 LOG_ERROR("BUG: called with in == NULL");
237 /* clock the target, and read the databus
238 * the *in pointer points to a buffer where elements of 'size' bytes
239 * are stored in big (be==1) or little (be==0) endianness
241 int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
243 int retval = ERROR_OK;
244 scan_field_t fields[2];
246 jtag_add_end_state(TAP_DRPAUSE);
247 if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
251 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
253 fields[0].tap = jtag_info->tap;
254 fields[0].num_bits = 1;
255 fields[0].out_value = NULL;
256 fields[0].in_value = NULL;
257 fields[0].in_handler = NULL;
259 fields[1].tap = jtag_info->tap;
260 fields[1].num_bits = 32;
261 fields[1].out_value = NULL;
263 fields[1].in_value = tmp;
264 fields[1].in_handler = NULL;
266 jtag_add_dr_scan_now(2, fields, TAP_INVALID);
273 h_u32_to_be(((u8*)in), flip_u32(le_to_h_u32(tmp), 32));
276 h_u32_to_le(((u8*)in), flip_u32(le_to_h_u32(tmp), 32));
282 h_u16_to_be(((u8*)in), flip_u32(le_to_h_u32(tmp), 32) & 0xffff);
285 h_u16_to_le(((u8*)in), flip_u32(le_to_h_u32(tmp), 32) & 0xffff);
289 *((u8 *)in)= flip_u32(le_to_h_u32(tmp), 32) & 0xff;
293 jtag_add_runtest(0, TAP_INVALID);
295 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
297 if((retval = jtag_execute_queue()) != ERROR_OK)
304 LOG_DEBUG("in: 0x%8.8x", *(u32*)in);
308 LOG_ERROR("BUG: called with in == NULL");
316 void arm7tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
318 /* get pointers to arch-specific information */
319 armv4_5_common_t *armv4_5 = target->arch_info;
320 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
321 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
323 /* save r0 before using it and put system in ARM state
324 * to allow common handling of ARM and THUMB debugging */
326 /* fetch STR r0, [r0] */
327 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), NULL, 0);
328 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
329 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
330 /* nothing fetched, STR r0, [r0] in Execute (2) */
331 arm7tdmi_clock_data_in(jtag_info, r0);
333 /* MOV r0, r15 fetched, STR in Decode */
334 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), NULL, 0);
335 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), NULL, 0);
336 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
337 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
338 /* nothing fetched, STR r0, [r0] in Execute (2) */
339 arm7tdmi_clock_data_in(jtag_info, pc);
341 /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
342 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), NULL, 0);
343 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
344 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
345 /* nothing fetched, data for LDR r0, [PC, #0] */
346 arm7tdmi_clock_out(jtag_info, 0x0, NULL, 0);
347 /* nothing fetched, data from previous cycle is written to register */
348 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
351 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), NULL, 0);
352 /* NOP fetched, BX in Decode, MOV in Execute */
353 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
354 /* NOP fetched, BX in Execute (1) */
355 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
357 jtag_execute_queue();
359 /* fix program counter:
360 * MOV r0, r15 was the 4th instruction (+6)
361 * reading PC in Thumb state gives address of instruction + 4
366 void arm7tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
369 /* get pointers to arch-specific information */
370 armv4_5_common_t *armv4_5 = target->arch_info;
371 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
372 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
374 /* STMIA r0-15, [r0] at debug speed
375 * register values will start to appear on 4th DCLK
377 arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), NULL, 0);
379 /* fetch NOP, STM in DECODE stage */
380 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
381 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
382 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
384 for (i = 0; i <= 15; i++)
387 /* nothing fetched, STM still in EXECUTE (1+i cycle) */
388 arm7tdmi_clock_data_in(jtag_info, core_regs[i]);
392 void arm7tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
395 /* get pointers to arch-specific information */
396 armv4_5_common_t *armv4_5 = target->arch_info;
397 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
398 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
399 int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
400 u32 *buf_u32 = buffer;
401 u16 *buf_u16 = buffer;
404 /* STMIA r0-15, [r0] at debug speed
405 * register values will start to appear on 4th DCLK
407 arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), NULL, 0);
409 /* fetch NOP, STM in DECODE stage */
410 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
411 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
412 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
414 for (i = 0; i <= 15; i++)
416 /* nothing fetched, STM still in EXECUTE (1+i cycle), read databus */
422 arm7tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
425 arm7tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
428 arm7tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
435 void arm7tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
437 /* get pointers to arch-specific information */
438 armv4_5_common_t *armv4_5 = target->arch_info;
439 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
440 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
443 arm7tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), NULL, 0);
446 arm7tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), NULL, 0);
447 /* fetch NOP, STR in DECODE stage */
448 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
449 /* fetch NOP, STR in EXECUTE stage (1st cycle) */
450 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
451 /* nothing fetched, STR still in EXECUTE (2nd cycle) */
452 arm7tdmi_clock_data_in(jtag_info, xpsr);
455 void arm7tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
457 /* get pointers to arch-specific information */
458 armv4_5_common_t *armv4_5 = target->arch_info;
459 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
460 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
462 LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
465 arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), NULL, 0);
466 /* MSR2 fetched, MSR1 in DECODE */
467 arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), NULL, 0);
468 /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
469 arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), NULL, 0);
470 /* nothing fetched, MSR1 in EXECUTE (2) */
471 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
472 /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
473 arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), NULL, 0);
474 /* nothing fetched, MSR2 in EXECUTE (2) */
475 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
476 /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
477 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
478 /* nothing fetched, MSR3 in EXECUTE (2) */
479 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
480 /* NOP fetched, MSR4 in EXECUTE (1) */
481 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
482 /* nothing fetched, MSR4 in EXECUTE (2) */
483 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
486 void arm7tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
488 /* get pointers to arch-specific information */
489 armv4_5_common_t *armv4_5 = target->arch_info;
490 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
491 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
493 LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
496 arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), NULL, 0);
497 /* NOP fetched, MSR in DECODE */
498 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
499 /* NOP fetched, MSR in EXECUTE (1) */
500 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
501 /* nothing fetched, MSR in EXECUTE (2) */
502 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
505 void arm7tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
508 /* get pointers to arch-specific information */
509 armv4_5_common_t *armv4_5 = target->arch_info;
510 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
511 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
513 /* LDMIA r0-15, [r0] at debug speed
514 * register values will start to appear on 4th DCLK
516 arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), NULL, 0);
518 /* fetch NOP, LDM in DECODE stage */
519 arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
520 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
521 arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
523 for (i = 0; i <= 15; i++)
526 /* nothing fetched, LDM still in EXECUTE (1+i cycle) */
527 arm7tdmi_clock_out_inner(jtag_info, core_regs[i], 0);
529 arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
532 void arm7tdmi_load_word_regs(target_t *target, u32 mask)
534 /* get pointers to arch-specific information */
535 armv4_5_common_t *armv4_5 = target->arch_info;
536 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
537 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
539 /* put system-speed load-multiple into the pipeline */
540 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
541 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
542 arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), NULL, 0);
545 void arm7tdmi_load_hword_reg(target_t *target, int num)
547 /* get pointers to arch-specific information */
548 armv4_5_common_t *armv4_5 = target->arch_info;
549 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
550 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
552 /* put system-speed load half-word into the pipeline */
553 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
554 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
555 arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), NULL, 0);
558 void arm7tdmi_load_byte_reg(target_t *target, int num)
560 /* get pointers to arch-specific information */
561 armv4_5_common_t *armv4_5 = target->arch_info;
562 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
563 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
565 /* put system-speed load byte into the pipeline */
566 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
567 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
568 arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), NULL, 0);
571 void arm7tdmi_store_word_regs(target_t *target, u32 mask)
573 /* get pointers to arch-specific information */
574 armv4_5_common_t *armv4_5 = target->arch_info;
575 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
576 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
578 /* put system-speed store-multiple into the pipeline */
579 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
580 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
581 arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), NULL, 0);
584 void arm7tdmi_store_hword_reg(target_t *target, int num)
586 /* get pointers to arch-specific information */
587 armv4_5_common_t *armv4_5 = target->arch_info;
588 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
589 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
591 /* put system-speed store half-word into the pipeline */
592 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
593 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
594 arm7tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), NULL, 0);
597 void arm7tdmi_store_byte_reg(target_t *target, int num)
599 /* get pointers to arch-specific information */
600 armv4_5_common_t *armv4_5 = target->arch_info;
601 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
602 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
604 /* put system-speed store byte into the pipeline */
605 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
606 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
607 arm7tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), NULL, 0);
610 void arm7tdmi_write_pc(target_t *target, u32 pc)
612 /* get pointers to arch-specific information */
613 armv4_5_common_t *armv4_5 = target->arch_info;
614 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
615 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
617 /* LDMIA r0-15, [r0] at debug speed
618 * register values will start to appear on 4th DCLK
620 arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), NULL, 0);
621 /* fetch NOP, LDM in DECODE stage */
622 arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
623 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
624 arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
625 /* nothing fetched, LDM in EXECUTE stage (1st cycle) load register */
626 arm7tdmi_clock_out_inner(jtag_info, pc, 0);
627 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) load register */
628 arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
629 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) load register */
630 arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
631 /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
632 arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
633 /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
634 arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
637 void arm7tdmi_branch_resume(target_t *target)
639 /* get pointers to arch-specific information */
640 armv4_5_common_t *armv4_5 = target->arch_info;
641 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
642 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
644 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
645 arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_B(0xfffffa, 0), 0);
648 void arm7tdmi_branch_resume_thumb(target_t *target)
652 /* get pointers to arch-specific information */
653 armv4_5_common_t *armv4_5 = target->arch_info;
654 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
655 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
656 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
658 /* LDMIA r0, [r0] at debug speed
659 * register values will start to appear on 4th DCLK
661 arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x1, 0, 0), NULL, 0);
663 /* fetch NOP, LDM in DECODE stage */
664 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
665 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
666 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
667 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
668 arm7tdmi_clock_out(jtag_info, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) | 1, NULL, 0);
669 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
670 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
672 /* Branch and eXchange */
673 arm7tdmi_clock_out(jtag_info, ARMV4_5_BX(0), NULL, 0);
675 embeddedice_read_reg(dbg_stat);
677 /* fetch NOP, BX in DECODE stage */
678 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
680 /* target is now in Thumb state */
681 embeddedice_read_reg(dbg_stat);
683 /* fetch NOP, BX in EXECUTE stage (1st cycle) */
684 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
686 /* target is now in Thumb state */
687 embeddedice_read_reg(dbg_stat);
690 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), NULL, 0);
691 /* fetch NOP, LDR in Decode */
692 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
693 /* fetch NOP, LDR in Execute */
694 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
695 /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
696 arm7tdmi_clock_out(jtag_info, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0);
697 /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
698 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
700 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
701 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
703 embeddedice_read_reg(dbg_stat);
705 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 1);
706 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f8), NULL, 0);
709 void arm7tdmi_build_reg_cache(target_t *target)
711 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
712 /* get pointers to arch-specific information */
713 armv4_5_common_t *armv4_5 = target->arch_info;
715 (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
716 armv4_5->core_cache = (*cache_p);
719 int arm7tdmi_examine(struct target_s *target)
722 armv4_5_common_t *armv4_5 = target->arch_info;
723 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
724 if (!target->type->examined)
726 /* get pointers to arch-specific information */
727 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
728 reg_cache_t *t=embeddedice_build_reg_cache(target, arm7_9);
733 arm7_9->eice_cache = (*cache_p);
737 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
738 (*cache_p)->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx);
739 arm7_9->etm_ctx->reg_cache = (*cache_p)->next;
741 target->type->examined = 1;
743 if ((retval=embeddedice_setup(target))!=ERROR_OK)
745 if ((retval=arm7_9_setup(target))!=ERROR_OK)
749 if ((retval=etm_setup(target))!=ERROR_OK)
755 int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
757 arm7tdmi_build_reg_cache(target);
762 int arm7tdmi_quit(void)
767 int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_tap_t *tap)
769 armv4_5_common_t *armv4_5;
770 arm7_9_common_t *arm7_9;
772 arm7_9 = &arm7tdmi->arm7_9_common;
773 armv4_5 = &arm7_9->armv4_5_common;
775 /* prepare JTAG information for the new target */
776 arm7_9->jtag_info.tap = tap;
777 arm7_9->jtag_info.scann_size = 4;
779 /* register arch-specific functions */
780 arm7_9->examine_debug_reason = arm7tdmi_examine_debug_reason;
781 arm7_9->change_to_arm = arm7tdmi_change_to_arm;
782 arm7_9->read_core_regs = arm7tdmi_read_core_regs;
783 arm7_9->read_core_regs_target_buffer = arm7tdmi_read_core_regs_target_buffer;
784 arm7_9->read_xpsr = arm7tdmi_read_xpsr;
786 arm7_9->write_xpsr = arm7tdmi_write_xpsr;
787 arm7_9->write_xpsr_im8 = arm7tdmi_write_xpsr_im8;
788 arm7_9->write_core_regs = arm7tdmi_write_core_regs;
790 arm7_9->load_word_regs = arm7tdmi_load_word_regs;
791 arm7_9->load_hword_reg = arm7tdmi_load_hword_reg;
792 arm7_9->load_byte_reg = arm7tdmi_load_byte_reg;
794 arm7_9->store_word_regs = arm7tdmi_store_word_regs;
795 arm7_9->store_hword_reg = arm7tdmi_store_hword_reg;
796 arm7_9->store_byte_reg = arm7tdmi_store_byte_reg;
798 arm7_9->write_pc = arm7tdmi_write_pc;
799 arm7_9->branch_resume = arm7tdmi_branch_resume;
800 arm7_9->branch_resume_thumb = arm7tdmi_branch_resume_thumb;
802 arm7_9->enable_single_step = arm7_9_enable_eice_step;
803 arm7_9->disable_single_step = arm7_9_disable_eice_step;
805 arm7_9->pre_debug_entry = NULL;
806 arm7_9->post_debug_entry = NULL;
808 arm7_9->pre_restore_context = NULL;
809 arm7_9->post_restore_context = NULL;
811 /* initialize arch-specific breakpoint handling */
812 arm7_9->arm_bkpt = 0xdeeedeee;
813 arm7_9->thumb_bkpt = 0xdeee;
815 arm7_9->dbgreq_adjust_pc = 2;
816 arm7_9->arch_info = arm7tdmi;
818 arm7tdmi->arch_info = NULL;
819 arm7tdmi->common_magic = ARM7TDMI_COMMON_MAGIC;
821 arm7_9_init_arch_info(target, arm7_9);
826 int arm7tdmi_target_create( struct target_s *target, Jim_Interp *interp )
828 arm7tdmi_common_t *arm7tdmi;
830 arm7tdmi = calloc(1,sizeof(arm7tdmi_common_t));
831 arm7tdmi_init_arch_info(target, arm7tdmi, target->tap);
836 int arm7tdmi_register_commands(struct command_context_s *cmd_ctx)
840 retval = arm7_9_register_commands(cmd_ctx);