1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "arm926ejs.h"
27 #include "time_support.h"
33 #define _DEBUG_INSTRUCTION_EXECUTION_
37 int arm926ejs_register_commands(struct command_context_s *cmd_ctx);
39 int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
40 int arm926ejs_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
41 int arm926ejs_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
42 int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
43 int arm926ejs_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
44 int arm926ejs_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
46 int arm926ejs_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
47 int arm926ejs_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
49 /* forward declarations */
50 int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp);
51 int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
52 int arm926ejs_quit(void);
53 int arm926ejs_arch_state(struct target_s *target);
54 int arm926ejs_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
55 int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
56 int arm926ejs_soft_reset_halt(struct target_s *target);
57 static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical);
58 static int arm926ejs_mmu(struct target_s *target, int *enabled);
60 target_type_t arm926ejs_target =
65 .arch_state = arm926ejs_arch_state,
67 .target_request_data = arm7_9_target_request_data,
70 .resume = arm7_9_resume,
73 .assert_reset = arm7_9_assert_reset,
74 .deassert_reset = arm7_9_deassert_reset,
75 .soft_reset_halt = arm926ejs_soft_reset_halt,
77 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
79 .read_memory = arm7_9_read_memory,
80 .write_memory = arm926ejs_write_memory,
81 .bulk_write_memory = arm7_9_bulk_write_memory,
82 .checksum_memory = arm7_9_checksum_memory,
83 .blank_check_memory = arm7_9_blank_check_memory,
85 .run_algorithm = armv4_5_run_algorithm,
87 .add_breakpoint = arm7_9_add_breakpoint,
88 .remove_breakpoint = arm7_9_remove_breakpoint,
89 .add_watchpoint = arm7_9_add_watchpoint,
90 .remove_watchpoint = arm7_9_remove_watchpoint,
92 .register_commands = arm926ejs_register_commands,
93 .target_create = arm926ejs_target_create,
94 .init_target = arm926ejs_init_target,
95 .examine = arm9tdmi_examine,
96 .quit = arm926ejs_quit,
97 .virt2phys = arm926ejs_virt2phys,
102 int arm926ejs_catch_broken_irscan(u8 *captured, void *priv, scan_field_t *field)
104 /* The ARM926EJ-S' instruction register is 4 bits wide */
105 u8 t = *captured & 0xf;
106 u8 t2 = *field->in_check_value & 0xf;
111 else if ((t == 0x0f) || (t == 0x00))
113 LOG_DEBUG("caught ARM926EJ-S invalid Capture-IR result after CP15 access");
116 return ERROR_JTAG_QUEUE_FAILED;;
119 #define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
121 int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 *value)
123 int retval = ERROR_OK;
124 armv4_5_common_t *armv4_5 = target->arch_info;
125 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
126 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
127 u32 address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
128 scan_field_t fields[4];
133 buf_set_u32(address_buf, 0, 14, address);
135 jtag_add_end_state(TAP_RTI);
136 if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
140 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
142 fields[0].device = jtag_info->chain_pos;
143 fields[0].num_bits = 32;
144 fields[0].out_value = NULL;
145 fields[0].out_mask = NULL;
146 fields[0].in_value = NULL;
147 fields[0].in_check_value = NULL;
148 fields[0].in_check_mask = NULL;
149 fields[0].in_handler = NULL;
150 fields[0].in_handler_priv = NULL;
152 fields[1].device = jtag_info->chain_pos;
153 fields[1].num_bits = 1;
154 fields[1].out_value = &access;
155 fields[1].out_mask = NULL;
156 fields[1].in_value = &access;
157 fields[1].in_check_value = NULL;
158 fields[1].in_check_mask = NULL;
159 fields[1].in_handler = NULL;
160 fields[1].in_handler_priv = NULL;
162 fields[2].device = jtag_info->chain_pos;
163 fields[2].num_bits = 14;
164 fields[2].out_value = address_buf;
165 fields[2].out_mask = NULL;
166 fields[2].in_value = NULL;
167 fields[2].in_check_value = NULL;
168 fields[2].in_check_mask = NULL;
169 fields[2].in_handler = NULL;
170 fields[2].in_handler_priv = NULL;
172 fields[3].device = jtag_info->chain_pos;
173 fields[3].num_bits = 1;
174 fields[3].out_value = &nr_w_buf;
175 fields[3].out_mask = NULL;
176 fields[3].in_value = NULL;
177 fields[3].in_check_value = NULL;
178 fields[3].in_check_mask = NULL;
179 fields[3].in_handler = NULL;
180 fields[3].in_handler_priv = NULL;
182 jtag_add_dr_scan(4, fields, -1);
184 fields[0].in_handler_priv = value;
185 fields[0].in_handler = arm_jtag_buf_to_u32;
187 /*TODO: add timeout*/
190 /* rescan with NOP, to wait for the access to complete */
193 jtag_add_dr_scan(4, fields, -1);
194 if((retval = jtag_execute_queue()) != ERROR_OK)
198 } while (buf_get_u32(&access, 0, 1) != 1);
200 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
201 LOG_DEBUG("addr: 0x%x value: %8.8x", address, *value);
204 arm_jtag_set_instr(jtag_info, 0xc, &arm926ejs_catch_broken_irscan);
209 int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 value)
211 int retval = ERROR_OK;
212 armv4_5_common_t *armv4_5 = target->arch_info;
213 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
214 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
215 u32 address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
216 scan_field_t fields[4];
222 buf_set_u32(address_buf, 0, 14, address);
223 buf_set_u32(value_buf, 0, 32, value);
225 jtag_add_end_state(TAP_RTI);
226 if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
230 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
232 fields[0].device = jtag_info->chain_pos;
233 fields[0].num_bits = 32;
234 fields[0].out_value = value_buf;
235 fields[0].out_mask = NULL;
236 fields[0].in_value = NULL;
237 fields[0].in_check_value = NULL;
238 fields[0].in_check_mask = NULL;
239 fields[0].in_handler = NULL;
240 fields[0].in_handler_priv = NULL;
242 fields[1].device = jtag_info->chain_pos;
243 fields[1].num_bits = 1;
244 fields[1].out_value = &access;
245 fields[1].out_mask = NULL;
246 fields[1].in_value = &access;
247 fields[1].in_check_value = NULL;
248 fields[1].in_check_mask = NULL;
249 fields[1].in_handler = NULL;
250 fields[1].in_handler_priv = NULL;
252 fields[2].device = jtag_info->chain_pos;
253 fields[2].num_bits = 14;
254 fields[2].out_value = address_buf;
255 fields[2].out_mask = NULL;
256 fields[2].in_value = NULL;
257 fields[2].in_check_value = NULL;
258 fields[2].in_check_mask = NULL;
259 fields[2].in_handler = NULL;
260 fields[2].in_handler_priv = NULL;
262 fields[3].device = jtag_info->chain_pos;
263 fields[3].num_bits = 1;
264 fields[3].out_value = &nr_w_buf;
265 fields[3].out_mask = NULL;
266 fields[3].in_value = NULL;
267 fields[3].in_check_value = NULL;
268 fields[3].in_check_mask = NULL;
269 fields[3].in_handler = NULL;
270 fields[3].in_handler_priv = NULL;
272 jtag_add_dr_scan(4, fields, -1);
273 /*TODO: add timeout*/
276 /* rescan with NOP, to wait for the access to complete */
279 jtag_add_dr_scan(4, fields, -1);
280 if((retval = jtag_execute_queue()) != ERROR_OK)
284 } while (buf_get_u32(&access, 0, 1) != 1);
286 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
287 LOG_DEBUG("addr: 0x%x value: %8.8x", address, value);
290 arm_jtag_set_instr(jtag_info, 0xf, &arm926ejs_catch_broken_irscan);
295 int arm926ejs_examine_debug_reason(target_t *target)
297 armv4_5_common_t *armv4_5 = target->arch_info;
298 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
299 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
303 embeddedice_read_reg(dbg_stat);
304 if ((retval = jtag_execute_queue()) != ERROR_OK)
307 debug_reason = buf_get_u32(dbg_stat->value, 6, 4);
309 switch (debug_reason)
312 LOG_DEBUG("breakpoint from EICE unit 0");
313 target->debug_reason = DBG_REASON_BREAKPOINT;
316 LOG_DEBUG("breakpoint from EICE unit 1");
317 target->debug_reason = DBG_REASON_BREAKPOINT;
320 LOG_DEBUG("soft breakpoint (BKPT instruction)");
321 target->debug_reason = DBG_REASON_BREAKPOINT;
324 LOG_DEBUG("vector catch breakpoint");
325 target->debug_reason = DBG_REASON_BREAKPOINT;
328 LOG_DEBUG("external breakpoint");
329 target->debug_reason = DBG_REASON_BREAKPOINT;
332 LOG_DEBUG("watchpoint from EICE unit 0");
333 target->debug_reason = DBG_REASON_WATCHPOINT;
336 LOG_DEBUG("watchpoint from EICE unit 1");
337 target->debug_reason = DBG_REASON_WATCHPOINT;
340 LOG_DEBUG("external watchpoint");
341 target->debug_reason = DBG_REASON_WATCHPOINT;
344 LOG_DEBUG("internal debug request");
345 target->debug_reason = DBG_REASON_DBGRQ;
348 LOG_DEBUG("external debug request");
349 target->debug_reason = DBG_REASON_DBGRQ;
352 LOG_ERROR("BUG: debug re-entry from system speed access shouldn't be handled here");
355 LOG_ERROR("BUG: unknown debug reason: 0x%x", debug_reason);
356 target->debug_reason = DBG_REASON_DBGRQ;
357 retval = ERROR_TARGET_FAILURE;
364 u32 arm926ejs_get_ttb(target_t *target)
366 armv4_5_common_t *armv4_5 = target->arch_info;
367 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
368 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
369 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
373 if ((retval = arm926ejs->read_cp15(target, 0, 0, 2, 0, &ttb)) != ERROR_OK)
379 void arm926ejs_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
381 armv4_5_common_t *armv4_5 = target->arch_info;
382 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
383 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
384 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
387 /* read cp15 control register */
388 arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
389 jtag_execute_queue();
394 arm926ejs->write_cp15(target, 0, 0, 8, 7, 0x0);
396 cp15_control &= ~0x1U;
402 /* read-modify-write CP15 debug override register
403 * to enable "test and clean all" */
404 arm926ejs->read_cp15(target, 0, 0, 15, 0, &debug_override);
405 debug_override |= 0x80000;
406 arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
408 /* clean and invalidate DCache */
409 arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
411 /* write CP15 debug override register
412 * to disable "test and clean all" */
413 debug_override &= ~0x80000;
414 arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
416 cp15_control &= ~0x4U;
421 /* invalidate ICache */
422 arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
424 cp15_control &= ~0x1000U;
427 arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
430 void arm926ejs_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
432 armv4_5_common_t *armv4_5 = target->arch_info;
433 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
434 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
435 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
438 /* read cp15 control register */
439 arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
440 jtag_execute_queue();
443 cp15_control |= 0x1U;
446 cp15_control |= 0x4U;
449 cp15_control |= 0x1000U;
451 arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
454 void arm926ejs_post_debug_entry(target_t *target)
456 armv4_5_common_t *armv4_5 = target->arch_info;
457 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
458 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
459 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
461 /* examine cp15 control reg */
462 arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg);
463 jtag_execute_queue();
464 LOG_DEBUG("cp15_control_reg: %8.8x", arm926ejs->cp15_control_reg);
466 if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1)
469 /* identify caches */
470 arm926ejs->read_cp15(target, 0, 1, 0, 0, &cache_type_reg);
471 jtag_execute_queue();
472 armv4_5_identify_cache(cache_type_reg, &arm926ejs->armv4_5_mmu.armv4_5_cache);
475 arm926ejs->armv4_5_mmu.mmu_enabled = (arm926ejs->cp15_control_reg & 0x1U) ? 1 : 0;
476 arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm926ejs->cp15_control_reg & 0x4U) ? 1 : 0;
477 arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm926ejs->cp15_control_reg & 0x1000U) ? 1 : 0;
479 /* save i/d fault status and address register */
480 arm926ejs->read_cp15(target, 0, 0, 5, 0, &arm926ejs->d_fsr);
481 arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr);
482 arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far);
484 LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x",
485 arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr);
490 /* read-modify-write CP15 cache debug control register
491 * to disable I/D-cache linefills and force WT */
492 arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
493 cache_dbg_ctrl |= 0x7;
494 arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
497 void arm926ejs_pre_restore_context(target_t *target)
499 armv4_5_common_t *armv4_5 = target->arch_info;
500 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
501 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
502 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
504 /* restore i/d fault status and address register */
505 arm926ejs->write_cp15(target, 0, 0, 5, 0, arm926ejs->d_fsr);
506 arm926ejs->write_cp15(target, 0, 1, 5, 0, arm926ejs->i_fsr);
507 arm926ejs->write_cp15(target, 0, 0, 6, 0, arm926ejs->d_far);
511 /* read-modify-write CP15 cache debug control register
512 * to reenable I/D-cache linefills and disable WT */
513 arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
514 cache_dbg_ctrl &= ~0x7;
515 arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
518 int arm926ejs_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm926ejs_common_t **arm926ejs_p)
520 armv4_5_common_t *armv4_5 = target->arch_info;
521 arm7_9_common_t *arm7_9;
522 arm9tdmi_common_t *arm9tdmi;
523 arm926ejs_common_t *arm926ejs;
525 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
530 arm7_9 = armv4_5->arch_info;
531 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
536 arm9tdmi = arm7_9->arch_info;
537 if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
542 arm926ejs = arm9tdmi->arch_info;
543 if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC)
548 *armv4_5_p = armv4_5;
550 *arm9tdmi_p = arm9tdmi;
551 *arm926ejs_p = arm926ejs;
556 int arm926ejs_arch_state(struct target_s *target)
558 armv4_5_common_t *armv4_5 = target->arch_info;
559 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
560 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
561 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
565 "disabled", "enabled"
568 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
570 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
575 "target halted in %s state due to %s, current mode: %s\n"
576 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
577 "MMU: %s, D-Cache: %s, I-Cache: %s",
578 armv4_5_state_strings[armv4_5->core_state],
579 Jim_Nvp_value2name_simple( nvp_target_debug_reason,target->debug_reason)->name,
580 armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
581 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
582 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
583 state[arm926ejs->armv4_5_mmu.mmu_enabled],
584 state[arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
585 state[arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
590 int arm926ejs_soft_reset_halt(struct target_s *target)
592 int retval = ERROR_OK;
593 armv4_5_common_t *armv4_5 = target->arch_info;
594 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
595 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
596 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
597 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
599 if((retval = target_halt(target)) != ERROR_OK)
604 long long then=timeval_ms();
606 while (!(timeout=((timeval_ms()-then)>1000)))
608 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
610 embeddedice_read_reg(dbg_stat);
611 if((retval = jtag_execute_queue()) != ERROR_OK)
621 /* do not eat all CPU, time out after 1 se*/
630 LOG_ERROR("Failed to halt CPU after 1 sec");
631 return ERROR_TARGET_TIMEOUT;
634 target->state = TARGET_HALTED;
636 /* SVC, ARM state, IRQ and FIQ disabled */
637 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
638 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
639 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
641 /* start fetching from 0x0 */
642 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
643 armv4_5->core_cache->reg_list[15].dirty = 1;
644 armv4_5->core_cache->reg_list[15].valid = 1;
646 armv4_5->core_mode = ARMV4_5_MODE_SVC;
647 armv4_5->core_state = ARMV4_5_STATE_ARM;
649 arm926ejs_disable_mmu_caches(target, 1, 1, 1);
650 arm926ejs->armv4_5_mmu.mmu_enabled = 0;
651 arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
652 arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
654 return target_call_event_callbacks(target, TARGET_EVENT_HALTED);
658 int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
661 armv4_5_common_t *armv4_5 = target->arch_info;
662 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
663 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
664 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
666 if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
669 /* If ICache is enabled, we have to invalidate affected ICache lines
670 * the DCache is forced to write-through, so we don't have to clean it here
672 if (arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
676 /* invalidate ICache single entry with MVA */
677 arm926ejs->write_cp15(target, 0, 1, 7, 5, address);
681 /* invalidate ICache */
682 arm926ejs->write_cp15(target, 0, 0, 7, 5, address);
689 int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
691 arm9tdmi_init_target(cmd_ctx, target);
697 int arm926ejs_quit(void)
703 int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, int chain_pos, const char *variant)
705 arm9tdmi_common_t *arm9tdmi = &arm926ejs->arm9tdmi_common;
706 arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
708 /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
710 arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
712 arm9tdmi->arch_info = arm926ejs;
713 arm926ejs->common_magic = ARM926EJS_COMMON_MAGIC;
715 arm7_9->post_debug_entry = arm926ejs_post_debug_entry;
716 arm7_9->pre_restore_context = arm926ejs_pre_restore_context;
718 arm926ejs->read_cp15 = arm926ejs_cp15_read;
719 arm926ejs->write_cp15 = arm926ejs_cp15_write;
720 arm926ejs->armv4_5_mmu.armv4_5_cache.ctype = -1;
721 arm926ejs->armv4_5_mmu.get_ttb = arm926ejs_get_ttb;
722 arm926ejs->armv4_5_mmu.read_memory = arm7_9_read_memory;
723 arm926ejs->armv4_5_mmu.write_memory = arm7_9_write_memory;
724 arm926ejs->armv4_5_mmu.disable_mmu_caches = arm926ejs_disable_mmu_caches;
725 arm926ejs->armv4_5_mmu.enable_mmu_caches = arm926ejs_enable_mmu_caches;
726 arm926ejs->armv4_5_mmu.has_tiny_pages = 1;
727 arm926ejs->armv4_5_mmu.mmu_enabled = 0;
729 arm7_9->examine_debug_reason = arm926ejs_examine_debug_reason;
731 /* The ARM926EJ-S implements the ARMv5TE architecture which
732 * has the BKPT instruction, so we don't have to use a watchpoint comparator
734 arm7_9->arm_bkpt = ARMV5_BKPT(0x0);
735 arm7_9->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
740 int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp)
742 arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t));
744 arm926ejs_init_arch_info(target, arm926ejs, target->chain_position, target->variant);
749 int arm926ejs_register_commands(struct command_context_s *cmd_ctx)
752 command_t *arm926ejs_cmd;
755 retval = arm9tdmi_register_commands(cmd_ctx);
757 arm926ejs_cmd = register_command(cmd_ctx, NULL, "arm926ejs", NULL, COMMAND_ANY, "arm926ejs specific commands");
759 register_command(cmd_ctx, arm926ejs_cmd, "cp15", arm926ejs_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode_1> <opcode_2> <CRn> <CRm> [value]");
761 register_command(cmd_ctx, arm926ejs_cmd, "cache_info", arm926ejs_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
762 register_command(cmd_ctx, arm926ejs_cmd, "virt2phys", arm926ejs_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
764 register_command(cmd_ctx, arm926ejs_cmd, "mdw_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
765 register_command(cmd_ctx, arm926ejs_cmd, "mdh_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
766 register_command(cmd_ctx, arm926ejs_cmd, "mdb_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
768 register_command(cmd_ctx, arm926ejs_cmd, "mww_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
769 register_command(cmd_ctx, arm926ejs_cmd, "mwh_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
770 register_command(cmd_ctx, arm926ejs_cmd, "mwb_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
775 int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
778 target_t *target = get_current_target(cmd_ctx);
779 armv4_5_common_t *armv4_5;
780 arm7_9_common_t *arm7_9;
781 arm9tdmi_common_t *arm9tdmi;
782 arm926ejs_common_t *arm926ejs;
788 if ((argc < 4) || (argc > 5))
790 command_print(cmd_ctx, "usage: arm926ejs cp15 <opcode_1> <opcode_2> <CRn> <CRm> [value]");
794 opcode_1 = strtoul(args[0], NULL, 0);
795 opcode_2 = strtoul(args[1], NULL, 0);
796 CRn = strtoul(args[2], NULL, 0);
797 CRm = strtoul(args[3], NULL, 0);
799 if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
801 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
805 if (target->state != TARGET_HALTED)
807 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
814 if ((retval = arm926ejs->read_cp15(target, opcode_1, opcode_2, CRn, CRm, &value)) != ERROR_OK)
816 command_print(cmd_ctx, "couldn't access register");
819 if((retval = jtag_execute_queue()) != ERROR_OK)
824 command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
828 u32 value = strtoul(args[4], NULL, 0);
829 if ((retval = arm926ejs->write_cp15(target, opcode_1, opcode_2, CRn, CRm, value)) != ERROR_OK)
831 command_print(cmd_ctx, "couldn't access register");
834 command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
840 int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
842 target_t *target = get_current_target(cmd_ctx);
843 armv4_5_common_t *armv4_5;
844 arm7_9_common_t *arm7_9;
845 arm9tdmi_common_t *arm9tdmi;
846 arm926ejs_common_t *arm926ejs;
848 if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
850 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
854 return armv4_5_handle_cache_info_command(cmd_ctx, &arm926ejs->armv4_5_mmu.armv4_5_cache);
857 int arm926ejs_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
859 target_t *target = get_current_target(cmd_ctx);
860 armv4_5_common_t *armv4_5;
861 arm7_9_common_t *arm7_9;
862 arm9tdmi_common_t *arm9tdmi;
863 arm926ejs_common_t *arm926ejs;
864 arm_jtag_t *jtag_info;
866 if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
868 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
872 jtag_info = &arm7_9->jtag_info;
874 if (target->state != TARGET_HALTED)
876 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
880 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
883 int arm926ejs_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
885 target_t *target = get_current_target(cmd_ctx);
886 armv4_5_common_t *armv4_5;
887 arm7_9_common_t *arm7_9;
888 arm9tdmi_common_t *arm9tdmi;
889 arm926ejs_common_t *arm926ejs;
890 arm_jtag_t *jtag_info;
892 if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
894 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
898 jtag_info = &arm7_9->jtag_info;
900 if (target->state != TARGET_HALTED)
902 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
906 return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
909 int arm926ejs_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
911 target_t *target = get_current_target(cmd_ctx);
912 armv4_5_common_t *armv4_5;
913 arm7_9_common_t *arm7_9;
914 arm9tdmi_common_t *arm9tdmi;
915 arm926ejs_common_t *arm926ejs;
916 arm_jtag_t *jtag_info;
918 if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
920 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
924 jtag_info = &arm7_9->jtag_info;
926 if (target->state != TARGET_HALTED)
928 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
932 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
934 static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical)
942 armv4_5_common_t *armv4_5;
943 arm7_9_common_t *arm7_9;
944 arm9tdmi_common_t *arm9tdmi;
945 arm926ejs_common_t *arm926ejs;
946 retval= arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs);
947 if (retval != ERROR_OK)
951 u32 ret = armv4_5_mmu_translate_va(target, &arm926ejs->armv4_5_mmu, virtual, &type, &cb, &domain, &ap);
960 static int arm926ejs_mmu(struct target_s *target, int *enabled)
962 armv4_5_common_t *armv4_5 = target->arch_info;
963 arm926ejs_common_t *arm926ejs = armv4_5->arch_info;
965 if (target->state != TARGET_HALTED)
967 LOG_ERROR("Target not halted");
968 return ERROR_TARGET_INVALID;
970 *enabled = arm926ejs->armv4_5_mmu.mmu_enabled;