1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
26 #include "arm7_9_common.h"
30 #include "embeddedice.h"
41 #define _DEBUG_INSTRUCTION_EXECUTION_
45 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx);
46 int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
48 /* forward declarations */
49 int arm9tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
50 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
53 target_type_t arm9tdmi_target =
58 .arch_state = armv4_5_arch_state,
61 .resume = arm7_9_resume,
64 .assert_reset = arm7_9_assert_reset,
65 .deassert_reset = arm7_9_deassert_reset,
66 .soft_reset_halt = arm7_9_soft_reset_halt,
67 .prepare_reset_halt = arm7_9_prepare_reset_halt,
69 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
71 .read_memory = arm7_9_read_memory,
72 .write_memory = arm7_9_write_memory,
73 .bulk_write_memory = arm7_9_bulk_write_memory,
75 .run_algorithm = armv4_5_run_algorithm,
77 .add_breakpoint = arm7_9_add_breakpoint,
78 .remove_breakpoint = arm7_9_remove_breakpoint,
79 .add_watchpoint = arm7_9_add_watchpoint,
80 .remove_watchpoint = arm7_9_remove_watchpoint,
82 .register_commands = arm9tdmi_register_commands,
83 .target_command = arm9tdmi_target_command,
84 .init_target = arm9tdmi_init_target,
88 arm9tdmi_vector_t arm9tdmi_vectors[] =
90 {"reset", ARM9TDMI_RESET_VECTOR},
91 {"undef", ARM9TDMI_UNDEF_VECTOR},
92 {"swi", ARM9TDMI_SWI_VECTOR},
93 {"pabt", ARM9TDMI_PABT_VECTOR},
94 {"dabt", ARM9TDMI_DABT_VECTOR},
95 {"reserved", ARM9TDMI_RESERVED_VECTOR},
96 {"irq", ARM9TDMI_IRQ_VECTOR},
97 {"fiq", ARM9TDMI_FIQ_VECTOR},
101 int arm9tdmi_jtag_error_handler(u8 *in_value, void *priv)
105 DEBUG("caller: %s", caller);
107 return ERROR_JTAG_QUEUE_FAILED;
110 int arm9tdmi_examine_debug_reason(target_t *target)
112 /* get pointers to arch-specific information */
113 armv4_5_common_t *armv4_5 = target->arch_info;
114 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
116 /* only check the debug reason if we don't know it already */
117 if ((target->debug_reason != DBG_REASON_DBGRQ)
118 && (target->debug_reason != DBG_REASON_SINGLESTEP))
120 scan_field_t fields[3];
122 u8 instructionbus[4];
125 jtag_add_end_state(TAP_PD);
127 fields[0].device = arm7_9->jtag_info.chain_pos;
128 fields[0].num_bits = 32;
129 fields[0].out_value = NULL;
130 fields[0].out_mask = NULL;
131 fields[0].in_value = databus;
132 fields[0].in_check_value = NULL;
133 fields[0].in_check_mask = NULL;
134 fields[0].in_handler = NULL;
135 fields[0].in_handler_priv = NULL;
137 fields[1].device = arm7_9->jtag_info.chain_pos;
138 fields[1].num_bits = 3;
139 fields[1].out_value = NULL;
140 fields[1].out_mask = NULL;
141 fields[1].in_value = &debug_reason;
142 fields[1].in_check_value = NULL;
143 fields[1].in_check_mask = NULL;
144 fields[1].in_handler = NULL;
145 fields[1].in_handler_priv = NULL;
147 fields[2].device = arm7_9->jtag_info.chain_pos;
148 fields[2].num_bits = 32;
149 fields[2].out_value = NULL;
150 fields[2].out_mask = NULL;
151 fields[2].in_value = instructionbus;
152 fields[2].in_check_value = NULL;
153 fields[2].in_check_mask = NULL;
154 fields[2].in_handler = NULL;
155 fields[2].in_handler_priv = NULL;
157 arm_jtag_scann(&arm7_9->jtag_info, 0x1);
158 arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
160 jtag_add_dr_scan(3, fields, TAP_PD, NULL);
161 jtag_execute_queue();
163 fields[0].in_value = NULL;
164 fields[0].out_value = databus;
165 fields[1].in_value = NULL;
166 fields[1].out_value = &debug_reason;
167 fields[2].in_value = NULL;
168 fields[2].out_value = instructionbus;
170 jtag_add_dr_scan(3, fields, TAP_PD, NULL);
172 if (debug_reason & 0x4)
173 if (debug_reason & 0x2)
174 target->debug_reason = DBG_REASON_WPTANDBKPT;
176 target->debug_reason = DBG_REASON_WATCHPOINT;
178 target->debug_reason = DBG_REASON_BREAKPOINT;
184 /* put an instruction in the ARM9TDMI pipeline or write the data bus, and optionally read data */
185 int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int sysspeed)
187 scan_field_t fields[3];
190 u8 sysspeed_buf = 0x0;
193 buf_set_u32(out_buf, 0, 32, out);
195 buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
198 buf_set_u32(&sysspeed_buf, 2, 1, 1);
200 jtag_add_end_state(TAP_PD);
201 arm_jtag_scann(jtag_info, 0x1);
203 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
205 fields[0].device = jtag_info->chain_pos;
206 fields[0].num_bits = 32;
207 fields[0].out_value = out_buf;
208 fields[0].out_mask = NULL;
209 fields[0].in_value = NULL;
212 fields[0].in_handler = arm_jtag_buf_to_u32;
213 fields[0].in_handler_priv = in;
217 fields[0].in_handler = NULL;
218 fields[0].in_handler_priv = NULL;
220 fields[0].in_check_value = NULL;
221 fields[0].in_check_mask = NULL;
223 fields[1].device = jtag_info->chain_pos;
224 fields[1].num_bits = 3;
225 fields[1].out_value = &sysspeed_buf;
226 fields[1].out_mask = NULL;
227 fields[1].in_value = NULL;
228 fields[1].in_check_value = NULL;
229 fields[1].in_check_mask = NULL;
230 fields[1].in_handler = NULL;
231 fields[1].in_handler_priv = NULL;
233 fields[2].device = jtag_info->chain_pos;
234 fields[2].num_bits = 32;
235 fields[2].out_value = instr_buf;
236 fields[2].out_mask = NULL;
237 fields[2].in_value = NULL;
238 fields[2].in_check_value = NULL;
239 fields[2].in_check_mask = NULL;
240 fields[2].in_handler = NULL;
241 fields[2].in_handler_priv = NULL;
243 jtag_add_dr_scan(3, fields, -1, NULL);
245 jtag_add_runtest(0, -1);
247 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
249 jtag_execute_queue();
253 DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr, out, *in);
256 DEBUG("instr: 0x%8.8x, out: 0x%8.8x", instr, out);
263 /* just read data (instruction and data-out = don't care) */
264 int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
266 scan_field_t fields[3];
268 jtag_add_end_state(TAP_PD);
269 arm_jtag_scann(jtag_info, 0x1);
271 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
273 fields[0].device = jtag_info->chain_pos;
274 fields[0].num_bits = 32;
275 fields[0].out_value = NULL;
276 fields[0].out_mask = NULL;
277 fields[0].in_value = NULL;
278 fields[0].in_handler = arm_jtag_buf_to_u32;
279 fields[0].in_handler_priv = in;
280 fields[0].in_check_value = NULL;
281 fields[0].in_check_mask = NULL;
283 fields[1].device = jtag_info->chain_pos;
284 fields[1].num_bits = 3;
285 fields[1].out_value = NULL;
286 fields[1].out_mask = NULL;
287 fields[1].in_value = NULL;
288 fields[1].in_handler = NULL;
289 fields[1].in_handler_priv = NULL;
290 fields[1].in_check_value = NULL;
291 fields[1].in_check_mask = NULL;
293 fields[2].device = jtag_info->chain_pos;
294 fields[2].num_bits = 32;
295 fields[2].out_value = NULL;
296 fields[2].out_mask = NULL;
297 fields[2].in_value = NULL;
298 fields[2].in_check_value = NULL;
299 fields[2].in_check_mask = NULL;
300 fields[2].in_handler = NULL;
301 fields[2].in_handler_priv = NULL;
303 jtag_add_dr_scan(3, fields, -1, NULL);
305 jtag_add_runtest(0, -1);
307 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
309 jtag_execute_queue();
313 DEBUG("in: 0x%8.8x", *in);
317 ERROR("BUG: called with in == NULL");
325 /* clock the target, and read the databus
326 * the *in pointer points to a buffer where elements of 'size' bytes
327 * are stored in big (be==1) or little (be==0) endianness
329 int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
331 scan_field_t fields[3];
333 jtag_add_end_state(TAP_PD);
334 arm_jtag_scann(jtag_info, 0x1);
336 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
338 fields[0].device = jtag_info->chain_pos;
339 fields[0].num_bits = 32;
340 fields[0].out_value = NULL;
341 fields[0].out_mask = NULL;
342 fields[0].in_value = NULL;
346 fields[0].in_handler = (be) ? arm_jtag_buf_to_be32 : arm_jtag_buf_to_le32;
349 fields[0].in_handler = (be) ? arm_jtag_buf_to_be16 : arm_jtag_buf_to_le16;
352 fields[0].in_handler = arm_jtag_buf_to_8;
355 fields[0].in_handler_priv = in;
356 fields[0].in_check_value = NULL;
357 fields[0].in_check_mask = NULL;
359 fields[1].device = jtag_info->chain_pos;
360 fields[1].num_bits = 3;
361 fields[1].out_value = NULL;
362 fields[1].out_mask = NULL;
363 fields[1].in_value = NULL;
364 fields[1].in_handler = NULL;
365 fields[1].in_handler_priv = NULL;
366 fields[1].in_check_value = NULL;
367 fields[1].in_check_mask = NULL;
369 fields[2].device = jtag_info->chain_pos;
370 fields[2].num_bits = 32;
371 fields[2].out_value = NULL;
372 fields[2].out_mask = NULL;
373 fields[2].in_value = NULL;
374 fields[2].in_check_value = NULL;
375 fields[2].in_check_mask = NULL;
376 fields[2].in_handler = NULL;
377 fields[2].in_handler_priv = NULL;
379 jtag_add_dr_scan(3, fields, -1, NULL);
381 jtag_add_runtest(0, -1);
383 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
385 jtag_execute_queue();
389 DEBUG("in: 0x%8.8x", *in);
393 ERROR("BUG: called with in == NULL");
401 void arm9tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
403 /* get pointers to arch-specific information */
404 armv4_5_common_t *armv4_5 = target->arch_info;
405 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
406 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
408 /* save r0 before using it and put system in ARM state
409 * to allow common handling of ARM and THUMB debugging */
411 /* fetch STR r0, [r0] */
412 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
413 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
414 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
415 /* STR r0, [r0] in Memory */
416 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, r0, 0);
418 /* MOV r0, r15 fetched, STR in Decode */
419 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), 0, NULL, 0);
420 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
421 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
422 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
423 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
424 /* nothing fetched, STR r0, [r0] in Memory */
425 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, pc, 0);
427 /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
428 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
430 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
432 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
433 /* LDR in Memory (to account for interlock) */
434 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
437 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), 0, NULL, 0);
438 /* NOP fetched, BX in Decode, MOV in Execute */
439 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
440 /* NOP fetched, BX in Execute (1) */
441 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
443 jtag_execute_queue();
445 /* fix program counter:
446 * MOV r0, r15 was the 5th instruction (+8)
447 * reading PC in Thumb state gives address of instruction + 4
452 void arm9tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
455 /* get pointers to arch-specific information */
456 armv4_5_common_t *armv4_5 = target->arch_info;
457 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
458 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
460 /* STMIA r0-15, [r0] at debug speed
461 * register values will start to appear on 4th DCLK
463 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
465 /* fetch NOP, STM in DECODE stage */
466 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
467 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
468 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
470 for (i = 0; i <= 15; i++)
473 /* nothing fetched, STM in MEMORY (i'th cycle) */
474 arm9tdmi_clock_data_in(jtag_info, core_regs[i]);
479 void arm9tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
482 /* get pointers to arch-specific information */
483 armv4_5_common_t *armv4_5 = target->arch_info;
484 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
485 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
486 int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
487 u32 *buf_u32 = buffer;
488 u16 *buf_u16 = buffer;
491 /* STMIA r0-15, [r0] at debug speed
492 * register values will start to appear on 4th DCLK
494 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
496 /* fetch NOP, STM in DECODE stage */
497 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
498 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
499 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
501 for (i = 0; i <= 15; i++)
504 /* nothing fetched, STM in MEMORY (i'th cycle) */
508 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
511 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
514 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
521 void arm9tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
523 /* get pointers to arch-specific information */
524 armv4_5_common_t *armv4_5 = target->arch_info;
525 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
526 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
529 arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
530 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
531 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
532 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
533 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
536 arm9tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), 0, NULL, 0);
537 /* fetch NOP, STR in DECODE stage */
538 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
539 /* fetch NOP, STR in EXECUTE stage (1st cycle) */
540 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
541 /* nothing fetched, STR in MEMORY */
542 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
546 void arm9tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
548 /* get pointers to arch-specific information */
549 armv4_5_common_t *armv4_5 = target->arch_info;
550 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
551 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
553 DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
556 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
557 /* MSR2 fetched, MSR1 in DECODE */
558 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), 0, NULL, 0);
559 /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
560 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), 0, NULL, 0);
561 /* nothing fetched, MSR1 in EXECUTE (2) */
562 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
563 /* nothing fetched, MSR1 in EXECUTE (3) */
564 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
565 /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
566 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), 0, NULL, 0);
567 /* nothing fetched, MSR2 in EXECUTE (2) */
568 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
569 /* nothing fetched, MSR2 in EXECUTE (3) */
570 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
571 /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
572 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
573 /* nothing fetched, MSR3 in EXECUTE (2) */
574 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
575 /* nothing fetched, MSR3 in EXECUTE (3) */
576 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
577 /* NOP fetched, MSR4 in EXECUTE (1) */
578 /* last MSR writes flags, which takes only one cycle */
579 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
582 void arm9tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
584 /* get pointers to arch-specific information */
585 armv4_5_common_t *armv4_5 = target->arch_info;
586 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
587 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
589 DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
592 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0);
593 /* NOP fetched, MSR in DECODE */
594 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
595 /* NOP fetched, MSR in EXECUTE (1) */
596 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
598 /* rot == 4 writes flags, which takes only one cycle */
601 /* nothing fetched, MSR in EXECUTE (2) */
602 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
603 /* nothing fetched, MSR in EXECUTE (3) */
604 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
608 void arm9tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
611 /* get pointers to arch-specific information */
612 armv4_5_common_t *armv4_5 = target->arch_info;
613 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
614 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
616 /* LDMIA r0-15, [r0] at debug speed
617 * register values will start to appear on 4th DCLK
619 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
621 /* fetch NOP, LDM in DECODE stage */
622 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
623 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
624 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
626 for (i = 0; i <= 15; i++)
629 /* nothing fetched, LDM still in EXECUTE (1+i cycle) */
630 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0);
632 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
636 void arm9tdmi_load_word_regs(target_t *target, u32 mask)
638 /* get pointers to arch-specific information */
639 armv4_5_common_t *armv4_5 = target->arch_info;
640 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
641 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
643 /* put system-speed load-multiple into the pipeline */
644 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), 0, NULL, 0);
645 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
649 void arm9tdmi_load_hword_reg(target_t *target, int num)
651 /* get pointers to arch-specific information */
652 armv4_5_common_t *armv4_5 = target->arch_info;
653 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
654 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
656 /* put system-speed load half-word into the pipeline */
657 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), 0, NULL, 0);
658 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
661 void arm9tdmi_load_byte_reg(target_t *target, int num)
663 /* get pointers to arch-specific information */
664 armv4_5_common_t *armv4_5 = target->arch_info;
665 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
666 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
668 /* put system-speed load byte into the pipeline */
669 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), 0, NULL, 0);
670 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
674 void arm9tdmi_store_word_regs(target_t *target, u32 mask)
676 /* get pointers to arch-specific information */
677 armv4_5_common_t *armv4_5 = target->arch_info;
678 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
679 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
681 /* put system-speed store-multiple into the pipeline */
682 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), 0, NULL, 0);
683 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
687 void arm9tdmi_store_hword_reg(target_t *target, int num)
689 /* get pointers to arch-specific information */
690 armv4_5_common_t *armv4_5 = target->arch_info;
691 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
692 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
694 /* put system-speed store half-word into the pipeline */
695 arm9tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), 0, NULL, 0);
696 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
700 void arm9tdmi_store_byte_reg(target_t *target, int num)
702 /* get pointers to arch-specific information */
703 armv4_5_common_t *armv4_5 = target->arch_info;
704 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
705 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
707 /* put system-speed store byte into the pipeline */
708 arm9tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), 0, NULL, 0);
709 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
713 void arm9tdmi_write_pc(target_t *target, u32 pc)
715 /* get pointers to arch-specific information */
716 armv4_5_common_t *armv4_5 = target->arch_info;
717 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
718 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
720 /* LDMIA r0-15, [r0] at debug speed
721 * register values will start to appear on 4th DCLK
723 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0, NULL, 0);
725 /* fetch NOP, LDM in DECODE stage */
726 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
727 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
728 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
729 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) (output data) */
730 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, pc, NULL, 0);
731 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
732 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
733 /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
734 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
735 /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
736 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
740 void arm9tdmi_branch_resume(target_t *target)
742 /* get pointers to arch-specific information */
743 armv4_5_common_t *armv4_5 = target->arch_info;
744 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
745 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
747 arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0);
748 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
752 void arm9tdmi_branch_resume_thumb(target_t *target)
756 /* get pointers to arch-specific information */
757 armv4_5_common_t *armv4_5 = target->arch_info;
758 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
759 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
760 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
762 /* LDMIA r0-15, [r0] at debug speed
763 * register values will start to appear on 4th DCLK
765 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x1, 0, 0), 0, NULL, 0);
767 /* fetch NOP, LDM in DECODE stage */
768 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
769 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
770 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
771 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
772 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) | 1, NULL, 0);
773 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
774 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
776 /* Branch and eXchange */
777 arm9tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0, NULL, 0);
779 embeddedice_read_reg(dbg_stat);
781 /* fetch NOP, BX in DECODE stage */
782 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
784 embeddedice_read_reg(dbg_stat);
786 /* fetch NOP, BX in EXECUTE stage (1st cycle) */
787 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
789 /* target is now in Thumb state */
790 embeddedice_read_reg(dbg_stat);
792 /* load r0 value, MOV_IM in Decode*/
793 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
794 /* fetch NOP, LDR in Decode, MOV_IM in Execute */
795 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
796 /* fetch NOP, LDR in Execute */
797 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
798 /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
799 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0);
800 /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
801 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
803 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
804 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
806 embeddedice_read_reg(dbg_stat);
808 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f7), 0, NULL, 1);
809 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
813 void arm9tdmi_enable_single_step(target_t *target)
815 /* get pointers to arch-specific information */
816 armv4_5_common_t *armv4_5 = target->arch_info;
817 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
819 if (arm7_9->has_single_step)
821 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 1);
822 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
826 arm7_9_enable_eice_step(target);
830 void arm9tdmi_disable_single_step(target_t *target)
832 /* get pointers to arch-specific information */
833 armv4_5_common_t *armv4_5 = target->arch_info;
834 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
836 if (arm7_9->has_single_step)
838 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 0);
839 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
843 arm7_9_disable_eice_step(target);
847 void arm9tdmi_build_reg_cache(target_t *target)
849 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
850 /* get pointers to arch-specific information */
851 armv4_5_common_t *armv4_5 = target->arch_info;
852 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
853 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
855 (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
856 armv4_5->core_cache = (*cache_p);
858 /* one extra register (vector catch) */
859 (*cache_p)->next = embeddedice_build_reg_cache(target, arm7_9);
860 arm7_9->eice_cache = (*cache_p)->next;
864 (*cache_p)->next->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx);
865 arm7_9->etm_ctx->reg_cache = (*cache_p)->next->next;
869 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
872 arm9tdmi_build_reg_cache(target);
884 int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, int chain_pos, char *variant)
886 armv4_5_common_t *armv4_5;
887 arm7_9_common_t *arm7_9;
889 arm7_9 = &arm9tdmi->arm7_9_common;
890 armv4_5 = &arm7_9->armv4_5_common;
892 /* prepare JTAG information for the new target */
893 arm7_9->jtag_info.chain_pos = chain_pos;
894 arm7_9->jtag_info.scann_size = 5;
896 /* register arch-specific functions */
897 arm7_9->examine_debug_reason = arm9tdmi_examine_debug_reason;
898 arm7_9->change_to_arm = arm9tdmi_change_to_arm;
899 arm7_9->read_core_regs = arm9tdmi_read_core_regs;
900 arm7_9->read_core_regs_target_buffer = arm9tdmi_read_core_regs_target_buffer;
901 arm7_9->read_xpsr = arm9tdmi_read_xpsr;
903 arm7_9->write_xpsr = arm9tdmi_write_xpsr;
904 arm7_9->write_xpsr_im8 = arm9tdmi_write_xpsr_im8;
905 arm7_9->write_core_regs = arm9tdmi_write_core_regs;
907 arm7_9->load_word_regs = arm9tdmi_load_word_regs;
908 arm7_9->load_hword_reg = arm9tdmi_load_hword_reg;
909 arm7_9->load_byte_reg = arm9tdmi_load_byte_reg;
911 arm7_9->store_word_regs = arm9tdmi_store_word_regs;
912 arm7_9->store_hword_reg = arm9tdmi_store_hword_reg;
913 arm7_9->store_byte_reg = arm9tdmi_store_byte_reg;
915 arm7_9->write_pc = arm9tdmi_write_pc;
916 arm7_9->branch_resume = arm9tdmi_branch_resume;
917 arm7_9->branch_resume_thumb = arm9tdmi_branch_resume_thumb;
919 arm7_9->enable_single_step = arm9tdmi_enable_single_step;
920 arm7_9->disable_single_step = arm9tdmi_disable_single_step;
922 arm7_9->pre_debug_entry = NULL;
923 arm7_9->post_debug_entry = NULL;
925 arm7_9->pre_restore_context = NULL;
926 arm7_9->post_restore_context = NULL;
928 /* initialize arch-specific breakpoint handling */
929 arm7_9->arm_bkpt = 0xdeeedeee;
930 arm7_9->thumb_bkpt = 0xdeee;
932 arm7_9->sw_bkpts_use_wp = 1;
933 arm7_9->sw_bkpts_enabled = 0;
934 arm7_9->dbgreq_adjust_pc = 3;
935 arm7_9->arch_info = arm9tdmi;
937 arm9tdmi->common_magic = ARM9TDMI_COMMON_MAGIC;
938 arm9tdmi->arch_info = NULL;
942 arm9tdmi->variant = strdup(variant);
946 arm9tdmi->variant = strdup("");
949 arm7_9_init_arch_info(target, arm7_9);
951 /* override use of DBGRQ, this is safe on ARM9TDMI */
952 arm7_9->use_dbgrq = 1;
954 /* all ARM9s have the vector catch register */
955 arm7_9->has_vector_catch = 1;
960 int arm9tdmi_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p)
962 armv4_5_common_t *armv4_5 = target->arch_info;
963 arm7_9_common_t *arm7_9;
964 arm9tdmi_common_t *arm9tdmi;
966 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
971 arm7_9 = armv4_5->arch_info;
972 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
977 arm9tdmi = arm7_9->arch_info;
978 if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
983 *armv4_5_p = armv4_5;
985 *arm9tdmi_p = arm9tdmi;
991 /* target arm9tdmi <endianess> <startup_mode> <chain_pos> <variant>*/
992 int arm9tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
995 char *variant = NULL;
996 arm9tdmi_common_t *arm9tdmi = malloc(sizeof(arm9tdmi_common_t));
1000 ERROR("'target arm9tdmi' requires at least one additional argument");
1004 chain_pos = strtoul(args[3], NULL, 0);
1009 arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
1014 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx)
1018 command_t *arm9tdmi_cmd;
1021 retval = arm7_9_register_commands(cmd_ctx);
1023 arm9tdmi_cmd = register_command(cmd_ctx, NULL, "arm9tdmi", NULL, COMMAND_ANY, "arm9tdmi specific commands");
1025 register_command(cmd_ctx, arm9tdmi_cmd, "vector_catch", handle_arm9tdmi_catch_vectors_command, COMMAND_EXEC, "catch arm920t vectors ['all'|'none'|'<vec1 vec2 ...>']");
1032 int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1034 target_t *target = get_current_target(cmd_ctx);
1035 armv4_5_common_t *armv4_5;
1036 arm7_9_common_t *arm7_9;
1037 arm9tdmi_common_t *arm9tdmi;
1038 reg_t *vector_catch;
1039 u32 vector_catch_value;
1042 if (arm9tdmi_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi) != ERROR_OK)
1044 command_print(cmd_ctx, "current target isn't an ARM9TDMI based target");
1048 vector_catch = &arm7_9->eice_cache->reg_list[EICE_VEC_CATCH];
1050 /* read the vector catch register if necessary */
1051 if (!vector_catch->valid)
1052 embeddedice_read_reg(vector_catch);
1054 /* get the current setting */
1055 vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
1059 vector_catch_value = 0x0;
1060 if (strcmp(args[0], "all") == 0)
1062 vector_catch_value = 0xdf;
1064 else if (strcmp(args[0], "none") == 0)
1070 for (i = 0; i < argc; i++)
1072 /* go through list of vectors */
1073 for(j = 0; arm9tdmi_vectors[j].name; j++)
1075 if (strcmp(args[i], arm9tdmi_vectors[j].name) == 0)
1077 vector_catch_value |= arm9tdmi_vectors[j].value;
1082 /* complain if vector wasn't found */
1083 if (!arm9tdmi_vectors[j].name)
1085 command_print(cmd_ctx, "vector '%s' not found, leaving current setting unchanged", args[i]);
1087 /* reread current setting */
1088 vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
1095 /* store new settings */
1096 buf_set_u32(vector_catch->value, 0, 32, vector_catch_value);
1097 embeddedice_store_reg(vector_catch);
1100 /* output current settings (skip RESERVED vector) */
1101 for (i = 0; i < 8; i++)
1105 command_print(cmd_ctx, "%s: %s", arm9tdmi_vectors[i].name,
1106 (vector_catch_value & (1 << i)) ? "catch" : "don't catch");