git.sur5r.net Git - openocd/blob - src/target/arm9tdmi.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Hongtao Zheng                                   *
   9  *   hontor@126.com                                                        *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26 #ifdef HAVE_CONFIG_H
  27 #include "config.h"
  28 #endif
  29
  30 #include "arm9tdmi.h"
  31
  32 #include "arm7_9_common.h"
  33 #include "register.h"
  34 #include "target.h"
  35 #include "armv4_5.h"
  36 #include "embeddedice.h"
  37 #include "etm.h"
  38 #include "etb.h"
  39 #include "log.h"
  40 #include "jtag.h"
  41 #include "arm_jtag.h"
  42
  43 #include <stdlib.h>
  44 #include <string.h>
  45
  46 #if 0
  47 #define _DEBUG_INSTRUCTION_EXECUTION_
  48 #endif
  49
  50 /* cli handling */
  51 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx);
  52 int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  53
  54 /* forward declarations */
  55 int arm9tdmi_target_create( struct target_s *target, Jim_Interp *interp );
  56
  57 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
  58 int arm9tdmi_quit(void);
  59
  60 target_type_t arm9tdmi_target =
  61 {
  62         .name = "arm9tdmi",
  63
  64         .poll = arm7_9_poll,
  65         .arch_state = armv4_5_arch_state,
  66
  67         .target_request_data = arm7_9_target_request_data,
  68
  69         .halt = arm7_9_halt,
  70         .resume = arm7_9_resume,
  71         .step = arm7_9_step,
  72
  73         .assert_reset = arm7_9_assert_reset,
  74         .deassert_reset = arm7_9_deassert_reset,
  75         .soft_reset_halt = arm7_9_soft_reset_halt,
  76
  77         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
  78
  79         .read_memory = arm7_9_read_memory,
  80         .write_memory = arm7_9_write_memory,
  81         .bulk_write_memory = arm7_9_bulk_write_memory,
  82         .checksum_memory = arm7_9_checksum_memory,
  83         .blank_check_memory = arm7_9_blank_check_memory,
  84
  85         .run_algorithm = armv4_5_run_algorithm,
  86
  87         .add_breakpoint = arm7_9_add_breakpoint,
  88         .remove_breakpoint = arm7_9_remove_breakpoint,
  89         .add_watchpoint = arm7_9_add_watchpoint,
  90         .remove_watchpoint = arm7_9_remove_watchpoint,
  91
  92         .register_commands = arm9tdmi_register_commands,
  93         .target_create = arm9tdmi_target_create,
  94         .init_target = arm9tdmi_init_target,
  95         .examine = arm9tdmi_examine,
  96         .quit = arm9tdmi_quit
  97 };
  98
  99 arm9tdmi_vector_t arm9tdmi_vectors[] =
 100 {
 101         {"reset", ARM9TDMI_RESET_VECTOR},
 102         {"undef", ARM9TDMI_UNDEF_VECTOR},
 103         {"swi", ARM9TDMI_SWI_VECTOR},
 104         {"pabt", ARM9TDMI_PABT_VECTOR},
 105         {"dabt", ARM9TDMI_DABT_VECTOR},
 106         {"reserved", ARM9TDMI_RESERVED_VECTOR},
 107         {"irq", ARM9TDMI_IRQ_VECTOR},
 108         {"fiq", ARM9TDMI_FIQ_VECTOR},
 109         {0, 0},
 110 };
 111
 112 int arm9tdmi_examine_debug_reason(target_t *target)
 113 {
 114         int retval = ERROR_OK;
 115         /* get pointers to arch-specific information */
 116         armv4_5_common_t *armv4_5 = target->arch_info;
 117         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 118
 119         /* only check the debug reason if we don't know it already */
 120         if ((target->debug_reason != DBG_REASON_DBGRQ)
 121                         && (target->debug_reason != DBG_REASON_SINGLESTEP))
 122         {
 123                 scan_field_t fields[3];
 124                 u8 databus[4];
 125                 u8 instructionbus[4];
 126                 u8 debug_reason;
 127
 128                 jtag_add_end_state(TAP_PD);
 129
 130                 fields[0].tap = arm7_9->jtag_info.tap;
 131                 fields[0].num_bits = 32;
 132                 fields[0].out_value = NULL;
 133                 fields[0].out_mask = NULL;
 134                 fields[0].in_value = databus;
 135                 fields[0].in_check_value = NULL;
 136                 fields[0].in_check_mask = NULL;
 137                 fields[0].in_handler = NULL;
 138                 fields[0].in_handler_priv = NULL;
 139
 140                 fields[1].tap = arm7_9->jtag_info.tap;
 141                 fields[1].num_bits = 3;
 142                 fields[1].out_value = NULL;
 143                 fields[1].out_mask = NULL;
 144                 fields[1].in_value = &debug_reason;
 145                 fields[1].in_check_value = NULL;
 146                 fields[1].in_check_mask = NULL;
 147                 fields[1].in_handler = NULL;
 148                 fields[1].in_handler_priv = NULL;
 149
 150                 fields[2].tap = arm7_9->jtag_info.tap;
 151                 fields[2].num_bits = 32;
 152                 fields[2].out_value = NULL;
 153                 fields[2].out_mask = NULL;
 154                 fields[2].in_value = instructionbus;
 155                 fields[2].in_check_value = NULL;
 156                 fields[2].in_check_mask = NULL;
 157                 fields[2].in_handler = NULL;
 158                 fields[2].in_handler_priv = NULL;
 159
 160                 if((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK)
 161                 {
 162                         return retval;
 163                 }
 164                 arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
 165
 166                 jtag_add_dr_scan(3, fields, TAP_PD);
 167                 if((retval = jtag_execute_queue()) != ERROR_OK)
 168                 {
 169                         return retval;
 170                 }
 171
 172                 fields[0].in_value = NULL;
 173                 fields[0].out_value = databus;
 174                 fields[1].in_value = NULL;
 175                 fields[1].out_value = &debug_reason;
 176                 fields[2].in_value = NULL;
 177                 fields[2].out_value = instructionbus;
 178
 179                 jtag_add_dr_scan(3, fields, TAP_PD);
 180
 181                 if (debug_reason & 0x4)
 182                         if (debug_reason & 0x2)
 183                                 target->debug_reason = DBG_REASON_WPTANDBKPT;
 184                 else
 185                         target->debug_reason = DBG_REASON_WATCHPOINT;
 186                 else
 187                         target->debug_reason = DBG_REASON_BREAKPOINT;
 188         }
 189
 190         return ERROR_OK;
 191 }
 192
 193 /* put an instruction in the ARM9TDMI pipeline or write the data bus, and optionally read data */
 194 int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int sysspeed)
 195 {
 196         int retval = ERROR_OK;
 197         scan_field_t fields[3];
 198         u8 out_buf[4];
 199         u8 instr_buf[4];
 200         u8 sysspeed_buf = 0x0;
 201
 202         /* prepare buffer */
 203         buf_set_u32(out_buf, 0, 32, out);
 204
 205         buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
 206
 207         if (sysspeed)
 208                 buf_set_u32(&sysspeed_buf, 2, 1, 1);
 209
 210         jtag_add_end_state(TAP_PD);
 211         if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
 212         {
 213                 return retval;
 214         }
 215
 216         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 217
 218         fields[0].tap = jtag_info->tap;
 219         fields[0].num_bits = 32;
 220         fields[0].out_value = out_buf;
 221         fields[0].out_mask = NULL;
 222         fields[0].in_value = NULL;
 223         if (in)
 224         {
 225                 fields[0].in_handler = arm_jtag_buf_to_u32;
 226                 fields[0].in_handler_priv = in;
 227         }
 228         else
 229         {
 230                 fields[0].in_handler = NULL;
 231                 fields[0].in_handler_priv = NULL;
 232         }
 233         fields[0].in_check_value = NULL;
 234         fields[0].in_check_mask = NULL;
 235
 236         fields[1].tap = jtag_info->tap;
 237         fields[1].num_bits = 3;
 238         fields[1].out_value = &sysspeed_buf;
 239         fields[1].out_mask = NULL;
 240         fields[1].in_value = NULL;
 241         fields[1].in_check_value = NULL;
 242         fields[1].in_check_mask = NULL;
 243         fields[1].in_handler = NULL;
 244         fields[1].in_handler_priv = NULL;
 245
 246         fields[2].tap = jtag_info->tap;
 247         fields[2].num_bits = 32;
 248         fields[2].out_value = instr_buf;
 249         fields[2].out_mask = NULL;
 250         fields[2].in_value = NULL;
 251         fields[2].in_check_value = NULL;
 252         fields[2].in_check_mask = NULL;
 253         fields[2].in_handler = NULL;
 254         fields[2].in_handler_priv = NULL;
 255
 256         jtag_add_dr_scan(3, fields, -1);
 257
 258         jtag_add_runtest(0, -1);
 259
 260 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 261         {
 262                 if((retval = jtag_execute_queue()) != ERROR_OK)
 263                 {
 264                         return retval;
 265                 }
 266
 267                 if (in)
 268                 {
 269                         LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr, out, *in);
 270                 }
 271                 else
 272                         LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x", instr, out);
 273         }
 274 #endif
 275
 276         return ERROR_OK;
 277 }
 278
 279 /* just read data (instruction and data-out = don't care) */
 280 int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
 281 {
 282         int retval = ERROR_OK;;
 283         scan_field_t fields[3];
 284
 285         jtag_add_end_state(TAP_PD);
 286         if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
 287         {
 288                 return retval;
 289         }
 290
 291         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 292
 293         fields[0].tap = jtag_info->tap;
 294         fields[0].num_bits = 32;
 295         fields[0].out_value = NULL;
 296         fields[0].out_mask = NULL;
 297         fields[0].in_value = NULL;
 298         fields[0].in_handler = arm_jtag_buf_to_u32;
 299         fields[0].in_handler_priv = in;
 300         fields[0].in_check_value = NULL;
 301         fields[0].in_check_mask = NULL;
 302
 303         fields[1].tap = jtag_info->tap;
 304         fields[1].num_bits = 3;
 305         fields[1].out_value = NULL;
 306         fields[1].out_mask = NULL;
 307         fields[1].in_value = NULL;
 308         fields[1].in_handler = NULL;
 309         fields[1].in_handler_priv = NULL;
 310         fields[1].in_check_value = NULL;
 311         fields[1].in_check_mask = NULL;
 312
 313         fields[2].tap = jtag_info->tap;
 314         fields[2].num_bits = 32;
 315         fields[2].out_value = NULL;
 316         fields[2].out_mask = NULL;
 317         fields[2].in_value = NULL;
 318         fields[2].in_check_value = NULL;
 319         fields[2].in_check_mask = NULL;
 320         fields[2].in_handler = NULL;
 321         fields[2].in_handler_priv = NULL;
 322
 323         jtag_add_dr_scan(3, fields, -1);
 324
 325         jtag_add_runtest(0, -1);
 326
 327 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 328         {
 329                 if((retval = jtag_execute_queue()) != ERROR_OK)
 330                 {
 331                         return retval;
 332                 }
 333
 334                 if (in)
 335                 {
 336                         LOG_DEBUG("in: 0x%8.8x", *in);
 337                 }
 338                 else
 339                 {
 340                         LOG_ERROR("BUG: called with in == NULL");
 341                 }
 342         }
 343 #endif
 344
 345         return ERROR_OK;
 346 }
 347
 348 /* clock the target, and read the databus
 349  * the *in pointer points to a buffer where elements of 'size' bytes
 350  * are stored in big (be==1) or little (be==0) endianness
 351  */
 352 int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
 353 {
 354         int retval = ERROR_OK;
 355         scan_field_t fields[3];
 356
 357         jtag_add_end_state(TAP_PD);
 358         if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
 359         {
 360                 return retval;
 361         }
 362
 363         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 364
 365         fields[0].tap = jtag_info->tap;
 366         fields[0].num_bits = 32;
 367         fields[0].out_value = NULL;
 368         fields[0].out_mask = NULL;
 369         fields[0].in_value = NULL;
 370         switch (size)
 371         {
 372                 case 4:
 373                         fields[0].in_handler = (be) ? arm_jtag_buf_to_be32 : arm_jtag_buf_to_le32;
 374                         break;
 375                 case 2:
 376                         fields[0].in_handler = (be) ? arm_jtag_buf_to_be16 : arm_jtag_buf_to_le16;
 377                         break;
 378                 case 1:
 379                         fields[0].in_handler = arm_jtag_buf_to_8;
 380                         break;
 381         }
 382         fields[0].in_handler_priv = in;
 383         fields[0].in_check_value = NULL;
 384         fields[0].in_check_mask = NULL;
 385
 386         fields[1].tap = jtag_info->tap;
 387         fields[1].num_bits = 3;
 388         fields[1].out_value = NULL;
 389         fields[1].out_mask = NULL;
 390         fields[1].in_value = NULL;
 391         fields[1].in_handler = NULL;
 392         fields[1].in_handler_priv = NULL;
 393         fields[1].in_check_value = NULL;
 394         fields[1].in_check_mask = NULL;
 395
 396         fields[2].tap = jtag_info->tap;
 397         fields[2].num_bits = 32;
 398         fields[2].out_value = NULL;
 399         fields[2].out_mask = NULL;
 400         fields[2].in_value = NULL;
 401         fields[2].in_check_value = NULL;
 402         fields[2].in_check_mask = NULL;
 403         fields[2].in_handler = NULL;
 404         fields[2].in_handler_priv = NULL;
 405
 406         jtag_add_dr_scan(3, fields, -1);
 407
 408         jtag_add_runtest(0, -1);
 409
 410 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 411         {
 412                 if((retval = jtag_execute_queue()) != ERROR_OK)
 413                 {
 414                         return retval;
 415                 }
 416
 417                 if (in)
 418                 {
 419                         LOG_DEBUG("in: 0x%8.8x", *(u32*)in);
 420                 }
 421                 else
 422                 {
 423                         LOG_ERROR("BUG: called with in == NULL");
 424                 }
 425         }
 426 #endif
 427
 428         return ERROR_OK;
 429 }
 430
 431 void arm9tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
 432 {
 433         int retval = ERROR_OK;
 434         /* get pointers to arch-specific information */
 435         armv4_5_common_t *armv4_5 = target->arch_info;
 436         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 437         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 438
 439         /* save r0 before using it and put system in ARM state
 440          * to allow common handling of ARM and THUMB debugging */
 441
 442         /* fetch STR r0, [r0] */
 443         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
 444         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 445         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 446         /* STR r0, [r0] in Memory */
 447         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, r0, 0);
 448
 449         /* MOV r0, r15 fetched, STR in Decode */
 450         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), 0, NULL, 0);
 451         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 452         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
 453         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 454         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 455         /* nothing fetched, STR r0, [r0] in Memory */
 456         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, pc, 0);
 457
 458         /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
 459         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
 460         /* LDR in Decode */
 461         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 462         /* LDR in Execute */
 463         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 464         /* LDR in Memory (to account for interlock) */
 465         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 466
 467         /* fetch BX */
 468         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), 0, NULL, 0);
 469         /* NOP fetched, BX in Decode, MOV in Execute */
 470         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 471         /* NOP fetched, BX in Execute (1) */
 472         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 473
 474         if((retval = jtag_execute_queue()) != ERROR_OK)
 475         {
 476                 return;
 477         }
 478
 479         /* fix program counter:
 480          * MOV r0, r15 was the 5th instruction (+8)
 481          * reading PC in Thumb state gives address of instruction + 4
 482          */
 483         *pc -= 0xc;
 484 }
 485
 486 void arm9tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
 487 {
 488         int i;
 489         /* get pointers to arch-specific information */
 490         armv4_5_common_t *armv4_5 = target->arch_info;
 491         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 492         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 493
 494         /* STMIA r0-15, [r0] at debug speed
 495          * register values will start to appear on 4th DCLK
 496          */
 497         arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
 498
 499         /* fetch NOP, STM in DECODE stage */
 500         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 501         /* fetch NOP, STM in EXECUTE stage (1st cycle) */
 502         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 503
 504         for (i = 0; i <= 15; i++)
 505         {
 506                 if (mask & (1 << i))
 507                         /* nothing fetched, STM in MEMORY (i'th cycle) */
 508                         arm9tdmi_clock_data_in(jtag_info, core_regs[i]);
 509         }
 510
 511 }
 512
 513 void arm9tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
 514 {
 515         int i;
 516         /* get pointers to arch-specific information */
 517         armv4_5_common_t *armv4_5 = target->arch_info;
 518         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 519         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 520         int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
 521         u32 *buf_u32 = buffer;
 522         u16 *buf_u16 = buffer;
 523         u8 *buf_u8 = buffer;
 524
 525         /* STMIA r0-15, [r0] at debug speed
 526          * register values will start to appear on 4th DCLK
 527          */
 528         arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
 529
 530         /* fetch NOP, STM in DECODE stage */
 531         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 532         /* fetch NOP, STM in EXECUTE stage (1st cycle) */
 533         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 534
 535         for (i = 0; i <= 15; i++)
 536         {
 537                 if (mask & (1 << i))
 538                         /* nothing fetched, STM in MEMORY (i'th cycle) */
 539                         switch (size)
 540                         {
 541                                 case 4:
 542                                         arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
 543                                         break;
 544                                 case 2:
 545                                         arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
 546                                         break;
 547                                 case 1:
 548                                         arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
 549                                         break;
 550                         }
 551         }
 552
 553 }
 554
 555 void arm9tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
 556 {
 557         /* get pointers to arch-specific information */
 558         armv4_5_common_t *armv4_5 = target->arch_info;
 559         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 560         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 561
 562         /* MRS r0, cpsr */
 563         arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
 564         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 565         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 566         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 567         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 568
 569         /* STR r0, [r15] */
 570         arm9tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), 0, NULL, 0);
 571         /* fetch NOP, STR in DECODE stage */
 572         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 573         /* fetch NOP, STR in EXECUTE stage (1st cycle) */
 574         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 575         /* nothing fetched, STR in MEMORY */
 576         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
 577
 578 }
 579
 580 void arm9tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
 581 {
 582         /* get pointers to arch-specific information */
 583         armv4_5_common_t *armv4_5 = target->arch_info;
 584         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 585         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 586
 587         LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
 588
 589         /* MSR1 fetched */
 590         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
 591         /* MSR2 fetched, MSR1 in DECODE */
 592         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), 0, NULL, 0);
 593         /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
 594         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), 0, NULL, 0);
 595         /* nothing fetched, MSR1 in EXECUTE (2) */
 596         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 597         /* nothing fetched, MSR1 in EXECUTE (3) */
 598         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 599         /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
 600         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), 0, NULL, 0);
 601         /* nothing fetched, MSR2 in EXECUTE (2) */
 602         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 603         /* nothing fetched, MSR2 in EXECUTE (3) */
 604         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 605         /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
 606         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 607         /* nothing fetched, MSR3 in EXECUTE (2) */
 608         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 609         /* nothing fetched, MSR3 in EXECUTE (3) */
 610         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 611         /* NOP fetched, MSR4 in EXECUTE (1) */
 612         /* last MSR writes flags, which takes only one cycle */
 613         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 614 }
 615
 616 void arm9tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
 617 {
 618         /* get pointers to arch-specific information */
 619         armv4_5_common_t *armv4_5 = target->arch_info;
 620         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 621         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 622
 623         LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
 624
 625         /* MSR fetched */
 626         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0);
 627         /* NOP fetched, MSR in DECODE */
 628         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 629         /* NOP fetched, MSR in EXECUTE (1) */
 630         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 631
 632         /* rot == 4 writes flags, which takes only one cycle */
 633         if (rot != 4)
 634         {
 635                 /* nothing fetched, MSR in EXECUTE (2) */
 636                 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 637                 /* nothing fetched, MSR in EXECUTE (3) */
 638                 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 639         }
 640 }
 641
 642 void arm9tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
 643 {
 644         int i;
 645         /* get pointers to arch-specific information */
 646         armv4_5_common_t *armv4_5 = target->arch_info;
 647         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 648         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 649
 650         /* LDMIA r0-15, [r0] at debug speed
 651         * register values will start to appear on 4th DCLK
 652         */
 653         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
 654
 655         /* fetch NOP, LDM in DECODE stage */
 656         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 657         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 658         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 659
 660         for (i = 0; i <= 15; i++)
 661         {
 662                 if (mask & (1 << i))
 663                         /* nothing fetched, LDM still in EXECUTE (1+i cycle) */
 664                         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0);
 665         }
 666         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 667
 668 }
 669
 670 void arm9tdmi_load_word_regs(target_t *target, u32 mask)
 671 {
 672         /* get pointers to arch-specific information */
 673         armv4_5_common_t *armv4_5 = target->arch_info;
 674         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 675         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 676
 677         /* put system-speed load-multiple into the pipeline */
 678         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), 0, NULL, 0);
 679         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 680
 681 }
 682
 683 void arm9tdmi_load_hword_reg(target_t *target, int num)
 684 {
 685         /* get pointers to arch-specific information */
 686         armv4_5_common_t *armv4_5 = target->arch_info;
 687         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 688         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 689
 690         /* put system-speed load half-word into the pipeline */
 691         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), 0, NULL, 0);
 692         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 693 }
 694
 695 void arm9tdmi_load_byte_reg(target_t *target, int num)
 696 {
 697         /* get pointers to arch-specific information */
 698         armv4_5_common_t *armv4_5 = target->arch_info;
 699         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 700         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 701
 702         /* put system-speed load byte into the pipeline */
 703         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), 0, NULL, 0);
 704         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 705
 706 }
 707
 708 void arm9tdmi_store_word_regs(target_t *target, u32 mask)
 709 {
 710         /* get pointers to arch-specific information */
 711         armv4_5_common_t *armv4_5 = target->arch_info;
 712         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 713         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 714
 715         /* put system-speed store-multiple into the pipeline */
 716         arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), 0, NULL, 0);
 717         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 718
 719 }
 720
 721 void arm9tdmi_store_hword_reg(target_t *target, int num)
 722 {
 723         /* get pointers to arch-specific information */
 724         armv4_5_common_t *armv4_5 = target->arch_info;
 725         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 726         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 727
 728         /* put system-speed store half-word into the pipeline */
 729         arm9tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), 0, NULL, 0);
 730         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 731
 732 }
 733
 734 void arm9tdmi_store_byte_reg(target_t *target, int num)
 735 {
 736         /* get pointers to arch-specific information */
 737         armv4_5_common_t *armv4_5 = target->arch_info;
 738         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 739         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 740
 741         /* put system-speed store byte into the pipeline */
 742         arm9tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), 0, NULL, 0);
 743         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 744
 745 }
 746
 747 void arm9tdmi_write_pc(target_t *target, u32 pc)
 748 {
 749         /* get pointers to arch-specific information */
 750         armv4_5_common_t *armv4_5 = target->arch_info;
 751         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 752         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 753
 754         /* LDMIA r0-15, [r0] at debug speed
 755          * register values will start to appear on 4th DCLK
 756          */
 757         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0, NULL, 0);
 758
 759         /* fetch NOP, LDM in DECODE stage */
 760         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 761         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 762         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 763         /* nothing fetched, LDM in EXECUTE stage (2nd cycle) (output data) */
 764         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, pc, NULL, 0);
 765         /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
 766         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 767         /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
 768         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 769         /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
 770         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 771
 772 }
 773
 774 void arm9tdmi_branch_resume(target_t *target)
 775 {
 776         /* get pointers to arch-specific information */
 777         armv4_5_common_t *armv4_5 = target->arch_info;
 778         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 779         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 780
 781         arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0);
 782         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 783
 784 }
 785
 786 void arm9tdmi_branch_resume_thumb(target_t *target)
 787 {
 788         LOG_DEBUG("-");
 789
 790         /* get pointers to arch-specific information */
 791         armv4_5_common_t *armv4_5 = target->arch_info;
 792         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 793         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 794         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 795
 796         /* LDMIA r0-15, [r0] at debug speed
 797         * register values will start to appear on 4th DCLK
 798         */
 799         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x1, 0, 0), 0, NULL, 0);
 800
 801         /* fetch NOP, LDM in DECODE stage */
 802         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 803         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 804         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 805         /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
 806         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) | 1, NULL, 0);
 807         /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
 808         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 809
 810         /* Branch and eXchange */
 811         arm9tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0, NULL, 0);
 812
 813         embeddedice_read_reg(dbg_stat);
 814
 815         /* fetch NOP, BX in DECODE stage */
 816         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 817
 818         embeddedice_read_reg(dbg_stat);
 819
 820         /* fetch NOP, BX in EXECUTE stage (1st cycle) */
 821         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 822
 823         /* target is now in Thumb state */
 824         embeddedice_read_reg(dbg_stat);
 825
 826         /* load r0 value, MOV_IM in Decode*/
 827         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
 828         /* fetch NOP, LDR in Decode, MOV_IM in Execute */
 829         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 830         /* fetch NOP, LDR in Execute */
 831         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 832         /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
 833         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0);
 834         /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
 835         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 836
 837         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 838         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 839
 840         embeddedice_read_reg(dbg_stat);
 841
 842         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f7), 0, NULL, 1);
 843         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 844
 845 }
 846
 847 void arm9tdmi_enable_single_step(target_t *target, u32 next_pc)
 848 {
 849         /* get pointers to arch-specific information */
 850         armv4_5_common_t *armv4_5 = target->arch_info;
 851         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 852
 853         if (arm7_9->has_single_step)
 854         {
 855                 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 1);
 856                 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
 857         }
 858         else
 859         {
 860                 arm7_9_enable_eice_step(target, next_pc);
 861         }
 862 }
 863
 864 void arm9tdmi_disable_single_step(target_t *target)
 865 {
 866         /* get pointers to arch-specific information */
 867         armv4_5_common_t *armv4_5 = target->arch_info;
 868         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 869
 870         if (arm7_9->has_single_step)
 871         {
 872                 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 0);
 873                 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
 874         }
 875         else
 876         {
 877                 arm7_9_disable_eice_step(target);
 878         }
 879 }
 880
 881 void arm9tdmi_build_reg_cache(target_t *target)
 882 {
 883         reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
 884         /* get pointers to arch-specific information */
 885         armv4_5_common_t *armv4_5 = target->arch_info;
 886
 887         (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
 888         armv4_5->core_cache = (*cache_p);
 889 }
 890
 891
 892 int arm9tdmi_examine(struct target_s *target)
 893 {
 894         /* get pointers to arch-specific information */
 895         int retval;
 896         armv4_5_common_t *armv4_5 = target->arch_info;
 897         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 898         if (!target->type->examined)
 899         {
 900                 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
 901                 reg_cache_t *t;
 902                 /* one extra register (vector catch) */
 903                 t=embeddedice_build_reg_cache(target, arm7_9);
 904                 if (t==NULL)
 905                         return ERROR_FAIL;
 906                 (*cache_p) = t;
 907                 arm7_9->eice_cache = (*cache_p);
 908
 909                 if (arm7_9->etm_ctx)
 910                 {
 911                         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 912                         (*cache_p)->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx);
 913                         arm7_9->etm_ctx->reg_cache = (*cache_p)->next;
 914                 }
 915                 target->type->examined = 1;
 916         }
 917         if ((retval=embeddedice_setup(target))!=ERROR_OK)
 918                 return retval;
 919         if ((retval=arm7_9_setup(target))!=ERROR_OK)
 920                 return retval;
 921         if (arm7_9->etm_ctx)
 922         {
 923                 if ((retval=etm_setup(target))!=ERROR_OK)
 924                         return retval;
 925         }
 926         return ERROR_OK;
 927 }
 928
 929 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 930 {
 931
 932         arm9tdmi_build_reg_cache(target);
 933
 934         return ERROR_OK;
 935
 936 }
 937
 938 int arm9tdmi_quit(void)
 939 {
 940
 941         return ERROR_OK;
 942 }
 943
 944 int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, jtag_tap_t *tap, const char *variant)
 945 {
 946         armv4_5_common_t *armv4_5;
 947         arm7_9_common_t *arm7_9;
 948
 949         arm7_9 = &arm9tdmi->arm7_9_common;
 950         armv4_5 = &arm7_9->armv4_5_common;
 951
 952         /* prepare JTAG information for the new target */
 953         arm7_9->jtag_info.tap = tap;
 954         arm7_9->jtag_info.scann_size = 5;
 955
 956         /* register arch-specific functions */
 957         arm7_9->examine_debug_reason = arm9tdmi_examine_debug_reason;
 958         arm7_9->change_to_arm = arm9tdmi_change_to_arm;
 959         arm7_9->read_core_regs = arm9tdmi_read_core_regs;
 960         arm7_9->read_core_regs_target_buffer = arm9tdmi_read_core_regs_target_buffer;
 961         arm7_9->read_xpsr = arm9tdmi_read_xpsr;
 962
 963         arm7_9->write_xpsr = arm9tdmi_write_xpsr;
 964         arm7_9->write_xpsr_im8 = arm9tdmi_write_xpsr_im8;
 965         arm7_9->write_core_regs = arm9tdmi_write_core_regs;
 966
 967         arm7_9->load_word_regs = arm9tdmi_load_word_regs;
 968         arm7_9->load_hword_reg = arm9tdmi_load_hword_reg;
 969         arm7_9->load_byte_reg = arm9tdmi_load_byte_reg;
 970
 971         arm7_9->store_word_regs = arm9tdmi_store_word_regs;
 972         arm7_9->store_hword_reg = arm9tdmi_store_hword_reg;
 973         arm7_9->store_byte_reg = arm9tdmi_store_byte_reg;
 974
 975         arm7_9->write_pc = arm9tdmi_write_pc;
 976         arm7_9->branch_resume = arm9tdmi_branch_resume;
 977         arm7_9->branch_resume_thumb = arm9tdmi_branch_resume_thumb;
 978
 979         arm7_9->enable_single_step = arm9tdmi_enable_single_step;
 980         arm7_9->disable_single_step = arm9tdmi_disable_single_step;
 981
 982         arm7_9->pre_debug_entry = NULL;
 983         arm7_9->post_debug_entry = NULL;
 984
 985         arm7_9->pre_restore_context = NULL;
 986         arm7_9->post_restore_context = NULL;
 987
 988         /* initialize arch-specific breakpoint handling */
 989         arm7_9->arm_bkpt = 0xdeeedeee;
 990         arm7_9->thumb_bkpt = 0xdeee;
 991
 992         arm7_9->dbgreq_adjust_pc = 3;
 993         arm7_9->arch_info = arm9tdmi;
 994
 995         arm9tdmi->common_magic = ARM9TDMI_COMMON_MAGIC;
 996         arm9tdmi->arch_info = NULL;
 997
 998         if (variant)
 999         {
1000                 arm9tdmi->variant = strdup(variant);
1001         }
1002         else
1003         {
1004                 arm9tdmi->variant = strdup("");
1005         }
1006
1007         arm7_9_init_arch_info(target, arm7_9);
1008
1009         /* override use of DBGRQ, this is safe on ARM9TDMI */
1010         arm7_9->use_dbgrq = 1;
1011
1012         /* all ARM9s have the vector catch register */
1013         arm7_9->has_vector_catch = 1;
1014
1015         return ERROR_OK;
1016 }
1017
1018 int arm9tdmi_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p)
1019 {
1020         armv4_5_common_t *armv4_5 = target->arch_info;
1021         arm7_9_common_t *arm7_9;
1022         arm9tdmi_common_t *arm9tdmi;
1023
1024         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
1025         {
1026                 return -1;
1027         }
1028
1029         arm7_9 = armv4_5->arch_info;
1030         if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
1031         {
1032                 return -1;
1033         }
1034
1035         arm9tdmi = arm7_9->arch_info;
1036         if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
1037         {
1038                 return -1;
1039         }
1040
1041         *armv4_5_p = armv4_5;
1042         *arm7_9_p = arm7_9;
1043         *arm9tdmi_p = arm9tdmi;
1044
1045         return ERROR_OK;
1046 }
1047
1048
1049
1050 int arm9tdmi_target_create(struct target_s *target, Jim_Interp *interp)
1051 {
1052         arm9tdmi_common_t *arm9tdmi = calloc(1,sizeof(arm9tdmi_common_t));
1053
1054         arm9tdmi_init_arch_info(target, arm9tdmi, target->tap, target->variant);
1055
1056         return ERROR_OK;
1057 }
1058
1059 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx)
1060 {
1061         int retval;
1062
1063         command_t *arm9tdmi_cmd;
1064
1065
1066         retval = arm7_9_register_commands(cmd_ctx);
1067
1068         arm9tdmi_cmd = register_command(cmd_ctx, NULL, "arm9tdmi", NULL, COMMAND_ANY, "arm9tdmi specific commands");
1069
1070         register_command(cmd_ctx, arm9tdmi_cmd, "vector_catch", handle_arm9tdmi_catch_vectors_command, COMMAND_EXEC, "catch arm920t vectors ['all'|'none'|'<vec1 vec2 ...>']");
1071
1072
1073         return retval;
1074
1075 }
1076
1077 int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1078 {
1079         target_t *target = get_current_target(cmd_ctx);
1080         armv4_5_common_t *armv4_5;
1081         arm7_9_common_t *arm7_9;
1082         arm9tdmi_common_t *arm9tdmi;
1083         reg_t *vector_catch;
1084         u32 vector_catch_value;
1085         int i, j;
1086
1087         if (arm9tdmi_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi) != ERROR_OK)
1088         {
1089                 command_print(cmd_ctx, "current target isn't an ARM9TDMI based target");
1090                 return ERROR_OK;
1091         }
1092
1093         vector_catch = &arm7_9->eice_cache->reg_list[EICE_VEC_CATCH];
1094
1095         /* read the vector catch register if necessary */
1096         if (!vector_catch->valid)
1097                 embeddedice_read_reg(vector_catch);
1098
1099         /* get the current setting */
1100         vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
1101
1102         if (argc > 0)
1103         {
1104                 vector_catch_value = 0x0;
1105                 if (strcmp(args[0], "all") == 0)
1106                 {
1107                         vector_catch_value = 0xdf;
1108                 }
1109                 else if (strcmp(args[0], "none") == 0)
1110                 {
1111                         /* do nothing */
1112                 }
1113                 else
1114                 {
1115                         for (i = 0; i < argc; i++)
1116                         {
1117                                 /* go through list of vectors */
1118                                 for(j = 0; arm9tdmi_vectors[j].name; j++)
1119                                 {
1120                                         if (strcmp(args[i], arm9tdmi_vectors[j].name) == 0)
1121                                         {
1122                                                 vector_catch_value |= arm9tdmi_vectors[j].value;
1123                                                 break;
1124                                         }
1125                                 }
1126
1127                                 /* complain if vector wasn't found */
1128                                 if (!arm9tdmi_vectors[j].name)
1129                                 {
1130                                         command_print(cmd_ctx, "vector '%s' not found, leaving current setting unchanged", args[i]);
1131
1132                                         /* reread current setting */
1133                                         vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
1134
1135                                         break;
1136                                 }
1137                         }
1138                 }
1139
1140                 /* store new settings */
1141                 buf_set_u32(vector_catch->value, 0, 32, vector_catch_value);
1142                 embeddedice_store_reg(vector_catch);
1143         }
1144
1145         /* output current settings (skip RESERVED vector) */
1146         for (i = 0; i < 8; i++)
1147         {
1148                 if (i != 5)
1149                 {
1150                         command_print(cmd_ctx, "%s: %s", arm9tdmi_vectors[i].name,
1151                                 (vector_catch_value & (1 << i)) ? "catch" : "don't catch");
1152                 }
1153         }
1154
1155         return ERROR_OK;
1156 }