1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
26 #include "arm7_9_common.h"
30 #include "embeddedice.h"
39 #define _DEBUG_INSTRUCTION_EXECUTION_
43 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx);
45 /* forward declarations */
46 int arm9tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
47 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
50 target_type_t arm9tdmi_target =
55 .arch_state = armv4_5_arch_state,
58 .resume = arm7_9_resume,
61 .assert_reset = arm7_9_assert_reset,
62 .deassert_reset = arm7_9_deassert_reset,
63 .soft_reset_halt = arm7_9_soft_reset_halt,
65 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
67 .read_memory = arm7_9_read_memory,
68 .write_memory = arm7_9_write_memory,
69 .bulk_write_memory = arm7_9_bulk_write_memory,
71 .add_breakpoint = arm7_9_add_breakpoint,
72 .remove_breakpoint = arm7_9_remove_breakpoint,
73 .add_watchpoint = arm7_9_add_watchpoint,
74 .remove_watchpoint = arm7_9_remove_watchpoint,
76 .register_commands = arm9tdmi_register_commands,
77 .target_command = arm9tdmi_target_command,
78 .init_target = arm9tdmi_init_target,
82 int arm9tdmi_examine_debug_reason(target_t *target)
84 /* get pointers to arch-specific information */
85 armv4_5_common_t *armv4_5 = target->arch_info;
86 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
88 /* only check the debug reason if we don't know it already */
89 if ((target->debug_reason != DBG_REASON_DBGRQ)
90 && (target->debug_reason != DBG_REASON_SINGLESTEP))
92 scan_field_t fields[3];
97 jtag_add_end_state(TAP_PD);
99 fields[0].device = arm7_9->jtag_info.chain_pos;
100 fields[0].num_bits = 32;
101 fields[0].out_value = NULL;
102 fields[0].out_mask = NULL;
103 fields[0].in_value = databus;
104 fields[0].in_check_value = NULL;
105 fields[0].in_check_mask = NULL;
106 fields[0].in_handler = NULL;
107 fields[0].in_handler_priv = NULL;
109 fields[1].device = arm7_9->jtag_info.chain_pos;
110 fields[1].num_bits = 3;
111 fields[1].out_value = NULL;
112 fields[1].out_mask = NULL;
113 fields[1].in_value = &debug_reason;
114 fields[1].in_check_value = NULL;
115 fields[1].in_check_mask = NULL;
116 fields[1].in_handler = NULL;
117 fields[1].in_handler_priv = NULL;
119 fields[2].device = arm7_9->jtag_info.chain_pos;
120 fields[2].num_bits = 32;
121 fields[2].out_value = NULL;
122 fields[2].out_mask = NULL;
123 fields[2].in_value = instructionbus;
124 fields[2].in_check_value = NULL;
125 fields[2].in_check_mask = NULL;
126 fields[2].in_handler = NULL;
127 fields[2].in_handler_priv = NULL;
129 arm_jtag_scann(&arm7_9->jtag_info, 0x1);
130 arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr);
132 jtag_add_dr_scan(3, fields, TAP_PD);
133 jtag_execute_queue();
135 fields[0].in_value = NULL;
136 fields[0].out_value = databus;
137 fields[1].in_value = NULL;
138 fields[1].out_value = &debug_reason;
139 fields[2].in_value = NULL;
140 fields[2].out_value = instructionbus;
142 jtag_add_dr_scan(3, fields, TAP_PD);
144 if (debug_reason & 0x4)
145 if (debug_reason & 0x2)
146 target->debug_reason = DBG_REASON_WPTANDBKPT;
148 target->debug_reason = DBG_REASON_WATCHPOINT;
150 target->debug_reason = DBG_REASON_BREAKPOINT;
156 /* put an instruction in the ARM9TDMI pipeline or write the data bus, and optionally read data */
157 int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int sysspeed)
159 scan_field_t fields[3];
162 u8 sysspeed_buf = 0x0;
165 buf_set_u32(out_buf, 0, 32, out);
167 buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
170 buf_set_u32(&sysspeed_buf, 2, 1, 1);
172 jtag_add_end_state(TAP_PD);
173 arm_jtag_scann(jtag_info, 0x1);
174 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
176 fields[0].device = jtag_info->chain_pos;
177 fields[0].num_bits = 32;
178 fields[0].out_value = out_buf;
179 fields[0].out_mask = NULL;
180 fields[0].in_value = NULL;
183 fields[0].in_handler = arm_jtag_buf_to_u32;
184 fields[0].in_handler_priv = in;
188 fields[0].in_handler = NULL;
189 fields[0].in_handler_priv = NULL;
191 fields[0].in_check_value = NULL;
192 fields[0].in_check_mask = NULL;
194 fields[1].device = jtag_info->chain_pos;
195 fields[1].num_bits = 3;
196 fields[1].out_value = &sysspeed_buf;
197 fields[1].out_mask = NULL;
198 fields[1].in_value = NULL;
199 fields[1].in_check_value = NULL;
200 fields[1].in_check_mask = NULL;
201 fields[1].in_handler = NULL;
202 fields[1].in_handler_priv = NULL;
204 fields[2].device = jtag_info->chain_pos;
205 fields[2].num_bits = 32;
206 fields[2].out_value = instr_buf;
207 fields[2].out_mask = NULL;
208 fields[2].in_value = NULL;
209 fields[2].in_check_value = NULL;
210 fields[2].in_check_mask = NULL;
211 fields[2].in_handler = NULL;
212 fields[2].in_handler_priv = NULL;
214 jtag_add_dr_scan(3, fields, -1);
216 jtag_add_runtest(0, -1);
218 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
220 jtag_execute_queue();
224 DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr, out, *in);
227 DEBUG("instr: 0x%8.8x, out: 0x%8.8x", instr, out);
234 /* just read data (instruction and data-out = don't care) */
235 int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
237 scan_field_t fields[3];
239 jtag_add_end_state(TAP_PD);
240 arm_jtag_scann(jtag_info, 0x1);
241 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
243 fields[0].device = jtag_info->chain_pos;
244 fields[0].num_bits = 32;
245 fields[0].out_value = NULL;
246 fields[0].out_mask = NULL;
247 fields[0].in_value = NULL;
248 fields[0].in_handler = arm_jtag_buf_to_u32;
249 fields[0].in_handler_priv = in;
250 fields[0].in_check_value = NULL;
251 fields[0].in_check_mask = NULL;
253 fields[1].device = jtag_info->chain_pos;
254 fields[1].num_bits = 3;
255 fields[1].out_value = NULL;
256 fields[1].out_mask = NULL;
257 fields[1].in_value = NULL;
258 fields[1].in_handler = NULL;
259 fields[1].in_handler_priv = NULL;
260 fields[1].in_check_value = NULL;
261 fields[1].in_check_mask = NULL;
263 fields[2].device = jtag_info->chain_pos;
264 fields[2].num_bits = 32;
265 fields[2].out_value = NULL;
266 fields[2].out_mask = NULL;
267 fields[2].in_value = NULL;
268 fields[2].in_check_value = NULL;
269 fields[2].in_check_mask = NULL;
270 fields[2].in_handler = NULL;
271 fields[2].in_handler_priv = NULL;
273 jtag_add_dr_scan(3, fields, -1);
275 jtag_add_runtest(0, -1);
277 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
279 jtag_execute_queue();
283 DEBUG("in: 0x%8.8x", *in);
287 ERROR("BUG: called with in == NULL");
295 /* clock the target, and read the databus
296 * the *in pointer points to a buffer where elements of 'size' bytes
297 * are stored in big (be==1) or little (be==0) endianness
299 int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
301 scan_field_t fields[3];
303 jtag_add_end_state(TAP_PD);
304 arm_jtag_scann(jtag_info, 0x1);
305 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
307 fields[0].device = jtag_info->chain_pos;
308 fields[0].num_bits = 32;
309 fields[0].out_value = NULL;
310 fields[0].out_mask = NULL;
311 fields[0].in_value = NULL;
315 fields[0].in_handler = (be) ? arm_jtag_buf_to_be32 : arm_jtag_buf_to_le32;
318 fields[0].in_handler = (be) ? arm_jtag_buf_to_be16 : arm_jtag_buf_to_le16;
321 fields[0].in_handler = arm_jtag_buf_to_8;
324 fields[0].in_handler_priv = in;
325 fields[0].in_check_value = NULL;
326 fields[0].in_check_mask = NULL;
328 fields[1].device = jtag_info->chain_pos;
329 fields[1].num_bits = 3;
330 fields[1].out_value = NULL;
331 fields[1].out_mask = NULL;
332 fields[1].in_value = NULL;
333 fields[1].in_handler = NULL;
334 fields[1].in_handler_priv = NULL;
335 fields[1].in_check_value = NULL;
336 fields[1].in_check_mask = NULL;
338 fields[2].device = jtag_info->chain_pos;
339 fields[2].num_bits = 32;
340 fields[2].out_value = NULL;
341 fields[2].out_mask = NULL;
342 fields[2].in_value = NULL;
343 fields[2].in_check_value = NULL;
344 fields[2].in_check_mask = NULL;
345 fields[2].in_handler = NULL;
346 fields[2].in_handler_priv = NULL;
348 jtag_add_dr_scan(3, fields, -1);
350 jtag_add_runtest(0, -1);
352 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
354 jtag_execute_queue();
358 DEBUG("in: 0x%8.8x", *in);
362 ERROR("BUG: called with in == NULL");
370 void arm9tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
372 /* get pointers to arch-specific information */
373 armv4_5_common_t *armv4_5 = target->arch_info;
374 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
375 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
377 /* save r0 before using it and put system in ARM state
378 * to allow common handling of ARM and THUMB debugging */
380 /* fetch STR r0, [r0] */
381 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
382 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
383 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
384 /* STR r0, [r0] in Memory */
385 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, r0, 0);
387 /* MOV r0, r15 fetched, STR in Decode */
388 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), 0, NULL, 0);
389 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
390 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
391 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
392 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
393 /* nothing fetched, STR r0, [r0] in Memory */
394 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, pc, 0);
396 /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
397 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
399 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
401 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
402 /* LDR in Memory (to account for interlock) */
403 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
406 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), 0, NULL, 0);
407 /* NOP fetched, BX in Decode, MOV in Execute */
408 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
409 /* NOP fetched, BX in Execute (1) */
410 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
412 jtag_execute_queue();
414 /* fix program counter:
415 * MOV r0, r15 was the 5th instruction (+8)
416 * reading PC in Thumb state gives address of instruction + 4
421 void arm9tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
424 /* get pointers to arch-specific information */
425 armv4_5_common_t *armv4_5 = target->arch_info;
426 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
427 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
429 /* STMIA r0-15, [r0] at debug speed
430 * register values will start to appear on 4th DCLK
432 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
434 /* fetch NOP, STM in DECODE stage */
435 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
436 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
437 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
439 for (i = 0; i <= 15; i++)
442 /* nothing fetched, STM in MEMORY (i'th cycle) */
443 arm9tdmi_clock_data_in(jtag_info, core_regs[i]);
448 void arm9tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
451 /* get pointers to arch-specific information */
452 armv4_5_common_t *armv4_5 = target->arch_info;
453 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
454 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
455 int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
456 u32 *buf_u32 = buffer;
457 u16 *buf_u16 = buffer;
460 /* STMIA r0-15, [r0] at debug speed
461 * register values will start to appear on 4th DCLK
463 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
465 /* fetch NOP, STM in DECODE stage */
466 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
467 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
468 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
470 for (i = 0; i <= 15; i++)
473 /* nothing fetched, STM in MEMORY (i'th cycle) */
477 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
480 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
483 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
490 void arm9tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
492 /* get pointers to arch-specific information */
493 armv4_5_common_t *armv4_5 = target->arch_info;
494 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
495 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
498 arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
499 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
500 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
501 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
502 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
505 arm9tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), 0, NULL, 0);
506 /* fetch NOP, STR in DECODE stage */
507 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
508 /* fetch NOP, STR in EXECUTE stage (1st cycle) */
509 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
510 /* nothing fetched, STR in MEMORY */
511 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
515 void arm9tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
517 /* get pointers to arch-specific information */
518 armv4_5_common_t *armv4_5 = target->arch_info;
519 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
520 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
522 DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
525 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
526 /* MSR2 fetched, MSR1 in DECODE */
527 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), 0, NULL, 0);
528 /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
529 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), 0, NULL, 0);
530 /* nothing fetched, MSR1 in EXECUTE (2) */
531 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
532 /* nothing fetched, MSR1 in EXECUTE (3) */
533 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
534 /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
535 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), 0, NULL, 0);
536 /* nothing fetched, MSR2 in EXECUTE (2) */
537 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
538 /* nothing fetched, MSR2 in EXECUTE (3) */
539 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
540 /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
541 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
542 /* nothing fetched, MSR3 in EXECUTE (2) */
543 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
544 /* nothing fetched, MSR3 in EXECUTE (3) */
545 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
546 /* NOP fetched, MSR4 in EXECUTE (1) */
547 /* last MSR writes flags, which takes only one cycle */
548 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
551 void arm9tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
553 /* get pointers to arch-specific information */
554 armv4_5_common_t *armv4_5 = target->arch_info;
555 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
556 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
558 DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
561 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0);
562 /* NOP fetched, MSR in DECODE */
563 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
564 /* NOP fetched, MSR in EXECUTE (1) */
565 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
567 /* rot == 4 writes flags, which takes only one cycle */
570 /* nothing fetched, MSR in EXECUTE (2) */
571 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
572 /* nothing fetched, MSR in EXECUTE (3) */
573 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
577 void arm9tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
580 /* get pointers to arch-specific information */
581 armv4_5_common_t *armv4_5 = target->arch_info;
582 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
583 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
585 /* LDMIA r0-15, [r0] at debug speed
586 * register values will start to appear on 4th DCLK
588 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
590 /* fetch NOP, LDM in DECODE stage */
591 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
592 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
593 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
595 for (i = 0; i <= 15; i++)
598 /* nothing fetched, LDM still in EXECUTE (1+i cycle) */
599 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0);
601 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
605 void arm9tdmi_load_word_regs(target_t *target, u32 mask)
607 /* get pointers to arch-specific information */
608 armv4_5_common_t *armv4_5 = target->arch_info;
609 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
610 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
612 /* put system-speed load-multiple into the pipeline */
613 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), 0, NULL, 0);
614 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
618 void arm9tdmi_load_hword_reg(target_t *target, int num)
620 /* get pointers to arch-specific information */
621 armv4_5_common_t *armv4_5 = target->arch_info;
622 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
623 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
625 /* put system-speed load half-word into the pipeline */
626 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), 0, NULL, 0);
627 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
630 void arm9tdmi_load_byte_reg(target_t *target, int num)
632 /* get pointers to arch-specific information */
633 armv4_5_common_t *armv4_5 = target->arch_info;
634 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
635 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
637 /* put system-speed load byte into the pipeline */
638 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), 0, NULL, 0);
639 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
643 void arm9tdmi_store_word_regs(target_t *target, u32 mask)
645 /* get pointers to arch-specific information */
646 armv4_5_common_t *armv4_5 = target->arch_info;
647 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
648 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
650 /* put system-speed store-multiple into the pipeline */
651 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), 0, NULL, 0);
652 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
656 void arm9tdmi_store_hword_reg(target_t *target, int num)
658 /* get pointers to arch-specific information */
659 armv4_5_common_t *armv4_5 = target->arch_info;
660 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
661 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
663 /* put system-speed store half-word into the pipeline */
664 arm9tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), 0, NULL, 0);
665 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
669 void arm9tdmi_store_byte_reg(target_t *target, int num)
671 /* get pointers to arch-specific information */
672 armv4_5_common_t *armv4_5 = target->arch_info;
673 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
674 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
676 /* put system-speed store byte into the pipeline */
677 arm9tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), 0, NULL, 0);
678 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
682 void arm9tdmi_write_pc(target_t *target, u32 pc)
684 /* get pointers to arch-specific information */
685 armv4_5_common_t *armv4_5 = target->arch_info;
686 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
687 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
689 /* LDMIA r0-15, [r0] at debug speed
690 * register values will start to appear on 4th DCLK
692 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0, NULL, 0);
694 /* fetch NOP, LDM in DECODE stage */
695 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
696 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
697 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
698 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) (output data) */
699 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, pc, NULL, 0);
700 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
701 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
702 /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
703 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
704 /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
705 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
709 void arm9tdmi_branch_resume(target_t *target)
711 /* get pointers to arch-specific information */
712 armv4_5_common_t *armv4_5 = target->arch_info;
713 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
714 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
716 arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0);
717 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
721 void arm9tdmi_branch_resume_thumb(target_t *target)
725 /* get pointers to arch-specific information */
726 armv4_5_common_t *armv4_5 = target->arch_info;
727 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
728 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
729 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
731 /* LDMIA r0-15, [r0] at debug speed
732 * register values will start to appear on 4th DCLK
734 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x1, 0, 0), 0, NULL, 0);
736 /* fetch NOP, LDM in DECODE stage */
737 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
738 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
739 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
740 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
741 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) | 1, NULL, 0);
742 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
743 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
745 /* Branch and eXchange */
746 arm9tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0, NULL, 0);
748 embeddedice_read_reg(dbg_stat);
750 /* fetch NOP, BX in DECODE stage */
751 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
753 embeddedice_read_reg(dbg_stat);
755 /* fetch NOP, BX in EXECUTE stage (1st cycle) */
756 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
758 /* target is now in Thumb state */
759 embeddedice_read_reg(dbg_stat);
761 /* load r0 value, MOV_IM in Decode*/
762 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
763 /* fetch NOP, LDR in Decode, MOV_IM in Execute */
764 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
765 /* fetch NOP, LDR in Execute */
766 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
767 /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
768 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0);
769 /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
770 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
772 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
773 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
775 embeddedice_read_reg(dbg_stat);
777 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f7), 0, NULL, 1);
778 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
782 void arm9tdmi_enable_single_step(target_t *target)
784 /* get pointers to arch-specific information */
785 armv4_5_common_t *armv4_5 = target->arch_info;
786 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
787 arm9tdmi_common_t *arm9 = arm7_9->arch_info;
789 if (arm9->has_single_step)
791 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 1);
792 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
796 arm7_9_enable_eice_step(target);
800 void arm9tdmi_disable_single_step(target_t *target)
802 /* get pointers to arch-specific information */
803 armv4_5_common_t *armv4_5 = target->arch_info;
804 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
805 arm9tdmi_common_t *arm9 = arm7_9->arch_info;
807 if (arm9->has_single_step)
809 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 0);
810 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
814 arm7_9_disable_eice_step(target);
818 void arm9tdmi_build_reg_cache(target_t *target)
820 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
821 /* get pointers to arch-specific information */
822 armv4_5_common_t *armv4_5 = target->arch_info;
823 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
824 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
825 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
827 embeddedice_reg_t *vec_catch_arch_info;
829 (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
830 armv4_5->core_cache = (*cache_p);
832 /* one extra register (vector catch) */
833 (*cache_p)->next = embeddedice_build_reg_cache(target, jtag_info, 1);
834 arm7_9->eice_cache = (*cache_p)->next;
836 if (arm9tdmi->has_monitor_mode)
837 (*cache_p)->next->reg_list[EICE_DBG_CTRL].size = 6;
839 (*cache_p)->next->reg_list[EICE_DBG_CTRL].size = 4;
841 (*cache_p)->next->reg_list[EICE_DBG_STAT].size = 5;
843 (*cache_p)->next->reg_list[EICE_VEC_CATCH].name = "vector catch";
844 (*cache_p)->next->reg_list[EICE_VEC_CATCH].dirty = 0;
845 (*cache_p)->next->reg_list[EICE_VEC_CATCH].valid = 0;
846 (*cache_p)->next->reg_list[EICE_VEC_CATCH].bitfield_desc = NULL;
847 (*cache_p)->next->reg_list[EICE_VEC_CATCH].num_bitfields = 0;
848 (*cache_p)->next->reg_list[EICE_VEC_CATCH].size = 8;
849 (*cache_p)->next->reg_list[EICE_VEC_CATCH].value = calloc(1, 4);
850 vec_catch_arch_info = (*cache_p)->next->reg_list[EICE_VEC_CATCH].arch_info;
851 vec_catch_arch_info->addr = 0x2;
855 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
858 arm9tdmi_build_reg_cache(target);
870 int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, int chain_pos, char *variant)
872 armv4_5_common_t *armv4_5;
873 arm7_9_common_t *arm7_9;
875 arm7_9 = &arm9tdmi->arm7_9_common;
876 armv4_5 = &arm7_9->armv4_5_common;
878 /* prepare JTAG information for the new target */
879 arm7_9->jtag_info.chain_pos = chain_pos;
880 arm7_9->jtag_info.scann_size = 5;
882 /* register arch-specific functions */
883 arm7_9->examine_debug_reason = arm9tdmi_examine_debug_reason;
884 arm7_9->change_to_arm = arm9tdmi_change_to_arm;
885 arm7_9->read_core_regs = arm9tdmi_read_core_regs;
886 arm7_9->read_core_regs_target_buffer = arm9tdmi_read_core_regs_target_buffer;
887 arm7_9->read_xpsr = arm9tdmi_read_xpsr;
889 arm7_9->write_xpsr = arm9tdmi_write_xpsr;
890 arm7_9->write_xpsr_im8 = arm9tdmi_write_xpsr_im8;
891 arm7_9->write_core_regs = arm9tdmi_write_core_regs;
893 arm7_9->load_word_regs = arm9tdmi_load_word_regs;
894 arm7_9->load_hword_reg = arm9tdmi_load_hword_reg;
895 arm7_9->load_byte_reg = arm9tdmi_load_byte_reg;
897 arm7_9->store_word_regs = arm9tdmi_store_word_regs;
898 arm7_9->store_hword_reg = arm9tdmi_store_hword_reg;
899 arm7_9->store_byte_reg = arm9tdmi_store_byte_reg;
901 arm7_9->write_pc = arm9tdmi_write_pc;
902 arm7_9->branch_resume = arm9tdmi_branch_resume;
903 arm7_9->branch_resume_thumb = arm9tdmi_branch_resume_thumb;
905 arm7_9->enable_single_step = arm9tdmi_enable_single_step;
906 arm7_9->disable_single_step = arm9tdmi_disable_single_step;
908 arm7_9->pre_debug_entry = NULL;
909 arm7_9->post_debug_entry = NULL;
911 arm7_9->pre_restore_context = NULL;
912 arm7_9->post_restore_context = NULL;
914 /* initialize arch-specific breakpoint handling */
915 buf_set_u32((u8*)(&arm7_9->arm_bkpt), 0, 32, 0xdeeedeee);
916 buf_set_u32((u8*)(&arm7_9->thumb_bkpt), 0, 16, 0xdeee);
918 arm7_9->sw_bkpts_use_wp = 1;
919 arm7_9->sw_bkpts_enabled = 0;
920 arm7_9->dbgreq_adjust_pc = 3;
921 arm7_9->arch_info = arm9tdmi;
923 arm9tdmi->common_magic = ARM9TDMI_COMMON_MAGIC;
924 arm9tdmi->has_monitor_mode = 0;
925 arm9tdmi->has_single_step = 0;
926 arm9tdmi->arch_info = NULL;
930 if (strcmp(variant, "arm920t") == 0)
931 arm9tdmi->has_single_step = 1;
932 else if (strcmp(variant, "arm922t") == 0)
933 arm9tdmi->has_single_step = 1;
934 else if (strcmp(variant, "arm940t") == 0)
935 arm9tdmi->has_single_step = 1;
936 arm9tdmi->variant = strdup(variant);
939 arm9tdmi->variant = strdup("");
941 arm7_9_init_arch_info(target, arm7_9);
943 /* override use of DBGRQ, this is safe on ARM9TDMI */
944 arm7_9->use_dbgrq = 1;
949 /* target arm9tdmi <endianess> <startup_mode> <chain_pos> <variant>*/
950 int arm9tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
953 char *variant = NULL;
954 arm9tdmi_common_t *arm9tdmi = malloc(sizeof(arm9tdmi_common_t));
958 ERROR("'target arm9tdmi' requires at least one additional argument");
962 chain_pos = strtoul(args[3], NULL, 0);
967 arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
972 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx)
976 retval = arm7_9_register_commands(cmd_ctx);