1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
26 #include "arm7_9_common.h"
30 #include "embeddedice.h"
41 #define _DEBUG_INSTRUCTION_EXECUTION_
45 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx);
47 /* forward declarations */
48 int arm9tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
49 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
52 target_type_t arm9tdmi_target =
57 .arch_state = armv4_5_arch_state,
60 .resume = arm7_9_resume,
63 .assert_reset = arm7_9_assert_reset,
64 .deassert_reset = arm7_9_deassert_reset,
65 .soft_reset_halt = arm7_9_soft_reset_halt,
67 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
69 .read_memory = arm7_9_read_memory,
70 .write_memory = arm7_9_write_memory,
71 .bulk_write_memory = arm7_9_bulk_write_memory,
73 .run_algorithm = armv4_5_run_algorithm,
75 .add_breakpoint = arm7_9_add_breakpoint,
76 .remove_breakpoint = arm7_9_remove_breakpoint,
77 .add_watchpoint = arm7_9_add_watchpoint,
78 .remove_watchpoint = arm7_9_remove_watchpoint,
80 .register_commands = arm9tdmi_register_commands,
81 .target_command = arm9tdmi_target_command,
82 .init_target = arm9tdmi_init_target,
86 int arm9tdmi_examine_debug_reason(target_t *target)
88 /* get pointers to arch-specific information */
89 armv4_5_common_t *armv4_5 = target->arch_info;
90 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
92 /* only check the debug reason if we don't know it already */
93 if ((target->debug_reason != DBG_REASON_DBGRQ)
94 && (target->debug_reason != DBG_REASON_SINGLESTEP))
96 scan_field_t fields[3];
101 jtag_add_end_state(TAP_PD);
103 fields[0].device = arm7_9->jtag_info.chain_pos;
104 fields[0].num_bits = 32;
105 fields[0].out_value = NULL;
106 fields[0].out_mask = NULL;
107 fields[0].in_value = databus;
108 fields[0].in_check_value = NULL;
109 fields[0].in_check_mask = NULL;
110 fields[0].in_handler = NULL;
111 fields[0].in_handler_priv = NULL;
113 fields[1].device = arm7_9->jtag_info.chain_pos;
114 fields[1].num_bits = 3;
115 fields[1].out_value = NULL;
116 fields[1].out_mask = NULL;
117 fields[1].in_value = &debug_reason;
118 fields[1].in_check_value = NULL;
119 fields[1].in_check_mask = NULL;
120 fields[1].in_handler = NULL;
121 fields[1].in_handler_priv = NULL;
123 fields[2].device = arm7_9->jtag_info.chain_pos;
124 fields[2].num_bits = 32;
125 fields[2].out_value = NULL;
126 fields[2].out_mask = NULL;
127 fields[2].in_value = instructionbus;
128 fields[2].in_check_value = NULL;
129 fields[2].in_check_mask = NULL;
130 fields[2].in_handler = NULL;
131 fields[2].in_handler_priv = NULL;
133 arm_jtag_scann(&arm7_9->jtag_info, 0x1);
134 arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr);
136 jtag_add_dr_scan(3, fields, TAP_PD);
137 jtag_execute_queue();
139 fields[0].in_value = NULL;
140 fields[0].out_value = databus;
141 fields[1].in_value = NULL;
142 fields[1].out_value = &debug_reason;
143 fields[2].in_value = NULL;
144 fields[2].out_value = instructionbus;
146 jtag_add_dr_scan(3, fields, TAP_PD);
148 if (debug_reason & 0x4)
149 if (debug_reason & 0x2)
150 target->debug_reason = DBG_REASON_WPTANDBKPT;
152 target->debug_reason = DBG_REASON_WATCHPOINT;
154 target->debug_reason = DBG_REASON_BREAKPOINT;
160 /* put an instruction in the ARM9TDMI pipeline or write the data bus, and optionally read data */
161 int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int sysspeed)
163 scan_field_t fields[3];
166 u8 sysspeed_buf = 0x0;
169 buf_set_u32(out_buf, 0, 32, out);
171 buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
174 buf_set_u32(&sysspeed_buf, 2, 1, 1);
176 jtag_add_end_state(TAP_PD);
177 arm_jtag_scann(jtag_info, 0x1);
178 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
180 fields[0].device = jtag_info->chain_pos;
181 fields[0].num_bits = 32;
182 fields[0].out_value = out_buf;
183 fields[0].out_mask = NULL;
184 fields[0].in_value = NULL;
187 fields[0].in_handler = arm_jtag_buf_to_u32;
188 fields[0].in_handler_priv = in;
192 fields[0].in_handler = NULL;
193 fields[0].in_handler_priv = NULL;
195 fields[0].in_check_value = NULL;
196 fields[0].in_check_mask = NULL;
198 fields[1].device = jtag_info->chain_pos;
199 fields[1].num_bits = 3;
200 fields[1].out_value = &sysspeed_buf;
201 fields[1].out_mask = NULL;
202 fields[1].in_value = NULL;
203 fields[1].in_check_value = NULL;
204 fields[1].in_check_mask = NULL;
205 fields[1].in_handler = NULL;
206 fields[1].in_handler_priv = NULL;
208 fields[2].device = jtag_info->chain_pos;
209 fields[2].num_bits = 32;
210 fields[2].out_value = instr_buf;
211 fields[2].out_mask = NULL;
212 fields[2].in_value = NULL;
213 fields[2].in_check_value = NULL;
214 fields[2].in_check_mask = NULL;
215 fields[2].in_handler = NULL;
216 fields[2].in_handler_priv = NULL;
218 jtag_add_dr_scan(3, fields, -1);
220 jtag_add_runtest(0, -1);
222 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
224 jtag_execute_queue();
228 DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr, out, *in);
231 DEBUG("instr: 0x%8.8x, out: 0x%8.8x", instr, out);
238 /* just read data (instruction and data-out = don't care) */
239 int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
241 scan_field_t fields[3];
243 jtag_add_end_state(TAP_PD);
244 arm_jtag_scann(jtag_info, 0x1);
245 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
247 fields[0].device = jtag_info->chain_pos;
248 fields[0].num_bits = 32;
249 fields[0].out_value = NULL;
250 fields[0].out_mask = NULL;
251 fields[0].in_value = NULL;
252 fields[0].in_handler = arm_jtag_buf_to_u32;
253 fields[0].in_handler_priv = in;
254 fields[0].in_check_value = NULL;
255 fields[0].in_check_mask = NULL;
257 fields[1].device = jtag_info->chain_pos;
258 fields[1].num_bits = 3;
259 fields[1].out_value = NULL;
260 fields[1].out_mask = NULL;
261 fields[1].in_value = NULL;
262 fields[1].in_handler = NULL;
263 fields[1].in_handler_priv = NULL;
264 fields[1].in_check_value = NULL;
265 fields[1].in_check_mask = NULL;
267 fields[2].device = jtag_info->chain_pos;
268 fields[2].num_bits = 32;
269 fields[2].out_value = NULL;
270 fields[2].out_mask = NULL;
271 fields[2].in_value = NULL;
272 fields[2].in_check_value = NULL;
273 fields[2].in_check_mask = NULL;
274 fields[2].in_handler = NULL;
275 fields[2].in_handler_priv = NULL;
277 jtag_add_dr_scan(3, fields, -1);
279 jtag_add_runtest(0, -1);
281 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
283 jtag_execute_queue();
287 DEBUG("in: 0x%8.8x", *in);
291 ERROR("BUG: called with in == NULL");
299 /* clock the target, and read the databus
300 * the *in pointer points to a buffer where elements of 'size' bytes
301 * are stored in big (be==1) or little (be==0) endianness
303 int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
305 scan_field_t fields[3];
307 jtag_add_end_state(TAP_PD);
308 arm_jtag_scann(jtag_info, 0x1);
309 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
311 fields[0].device = jtag_info->chain_pos;
312 fields[0].num_bits = 32;
313 fields[0].out_value = NULL;
314 fields[0].out_mask = NULL;
315 fields[0].in_value = NULL;
319 fields[0].in_handler = (be) ? arm_jtag_buf_to_be32 : arm_jtag_buf_to_le32;
322 fields[0].in_handler = (be) ? arm_jtag_buf_to_be16 : arm_jtag_buf_to_le16;
325 fields[0].in_handler = arm_jtag_buf_to_8;
328 fields[0].in_handler_priv = in;
329 fields[0].in_check_value = NULL;
330 fields[0].in_check_mask = NULL;
332 fields[1].device = jtag_info->chain_pos;
333 fields[1].num_bits = 3;
334 fields[1].out_value = NULL;
335 fields[1].out_mask = NULL;
336 fields[1].in_value = NULL;
337 fields[1].in_handler = NULL;
338 fields[1].in_handler_priv = NULL;
339 fields[1].in_check_value = NULL;
340 fields[1].in_check_mask = NULL;
342 fields[2].device = jtag_info->chain_pos;
343 fields[2].num_bits = 32;
344 fields[2].out_value = NULL;
345 fields[2].out_mask = NULL;
346 fields[2].in_value = NULL;
347 fields[2].in_check_value = NULL;
348 fields[2].in_check_mask = NULL;
349 fields[2].in_handler = NULL;
350 fields[2].in_handler_priv = NULL;
352 jtag_add_dr_scan(3, fields, -1);
354 jtag_add_runtest(0, -1);
356 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
358 jtag_execute_queue();
362 DEBUG("in: 0x%8.8x", *in);
366 ERROR("BUG: called with in == NULL");
374 void arm9tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
376 /* get pointers to arch-specific information */
377 armv4_5_common_t *armv4_5 = target->arch_info;
378 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
379 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
381 /* save r0 before using it and put system in ARM state
382 * to allow common handling of ARM and THUMB debugging */
384 /* fetch STR r0, [r0] */
385 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
386 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
387 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
388 /* STR r0, [r0] in Memory */
389 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, r0, 0);
391 /* MOV r0, r15 fetched, STR in Decode */
392 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), 0, NULL, 0);
393 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
394 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
395 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
396 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
397 /* nothing fetched, STR r0, [r0] in Memory */
398 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, pc, 0);
400 /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
401 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
403 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
405 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
406 /* LDR in Memory (to account for interlock) */
407 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
410 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), 0, NULL, 0);
411 /* NOP fetched, BX in Decode, MOV in Execute */
412 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
413 /* NOP fetched, BX in Execute (1) */
414 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
416 jtag_execute_queue();
418 /* fix program counter:
419 * MOV r0, r15 was the 5th instruction (+8)
420 * reading PC in Thumb state gives address of instruction + 4
425 void arm9tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
428 /* get pointers to arch-specific information */
429 armv4_5_common_t *armv4_5 = target->arch_info;
430 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
431 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
433 /* STMIA r0-15, [r0] at debug speed
434 * register values will start to appear on 4th DCLK
436 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
438 /* fetch NOP, STM in DECODE stage */
439 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
440 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
441 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
443 for (i = 0; i <= 15; i++)
446 /* nothing fetched, STM in MEMORY (i'th cycle) */
447 arm9tdmi_clock_data_in(jtag_info, core_regs[i]);
452 void arm9tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
455 /* get pointers to arch-specific information */
456 armv4_5_common_t *armv4_5 = target->arch_info;
457 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
458 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
459 int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
460 u32 *buf_u32 = buffer;
461 u16 *buf_u16 = buffer;
464 /* STMIA r0-15, [r0] at debug speed
465 * register values will start to appear on 4th DCLK
467 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
469 /* fetch NOP, STM in DECODE stage */
470 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
471 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
472 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
474 for (i = 0; i <= 15; i++)
477 /* nothing fetched, STM in MEMORY (i'th cycle) */
481 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
484 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
487 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
494 void arm9tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
496 /* get pointers to arch-specific information */
497 armv4_5_common_t *armv4_5 = target->arch_info;
498 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
499 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
502 arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
503 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
504 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
505 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
506 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
509 arm9tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), 0, NULL, 0);
510 /* fetch NOP, STR in DECODE stage */
511 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
512 /* fetch NOP, STR in EXECUTE stage (1st cycle) */
513 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
514 /* nothing fetched, STR in MEMORY */
515 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
519 void arm9tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
521 /* get pointers to arch-specific information */
522 armv4_5_common_t *armv4_5 = target->arch_info;
523 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
524 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
526 DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
529 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
530 /* MSR2 fetched, MSR1 in DECODE */
531 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), 0, NULL, 0);
532 /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
533 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), 0, NULL, 0);
534 /* nothing fetched, MSR1 in EXECUTE (2) */
535 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
536 /* nothing fetched, MSR1 in EXECUTE (3) */
537 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
538 /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
539 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), 0, NULL, 0);
540 /* nothing fetched, MSR2 in EXECUTE (2) */
541 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
542 /* nothing fetched, MSR2 in EXECUTE (3) */
543 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
544 /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
545 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
546 /* nothing fetched, MSR3 in EXECUTE (2) */
547 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
548 /* nothing fetched, MSR3 in EXECUTE (3) */
549 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
550 /* NOP fetched, MSR4 in EXECUTE (1) */
551 /* last MSR writes flags, which takes only one cycle */
552 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
555 void arm9tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
557 /* get pointers to arch-specific information */
558 armv4_5_common_t *armv4_5 = target->arch_info;
559 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
560 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
562 DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
565 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0);
566 /* NOP fetched, MSR in DECODE */
567 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
568 /* NOP fetched, MSR in EXECUTE (1) */
569 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
571 /* rot == 4 writes flags, which takes only one cycle */
574 /* nothing fetched, MSR in EXECUTE (2) */
575 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
576 /* nothing fetched, MSR in EXECUTE (3) */
577 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
581 void arm9tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
584 /* get pointers to arch-specific information */
585 armv4_5_common_t *armv4_5 = target->arch_info;
586 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
587 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
589 /* LDMIA r0-15, [r0] at debug speed
590 * register values will start to appear on 4th DCLK
592 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
594 /* fetch NOP, LDM in DECODE stage */
595 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
596 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
597 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
599 for (i = 0; i <= 15; i++)
602 /* nothing fetched, LDM still in EXECUTE (1+i cycle) */
603 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0);
605 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
609 void arm9tdmi_load_word_regs(target_t *target, u32 mask)
611 /* get pointers to arch-specific information */
612 armv4_5_common_t *armv4_5 = target->arch_info;
613 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
614 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
616 /* put system-speed load-multiple into the pipeline */
617 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), 0, NULL, 0);
618 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
622 void arm9tdmi_load_hword_reg(target_t *target, int num)
624 /* get pointers to arch-specific information */
625 armv4_5_common_t *armv4_5 = target->arch_info;
626 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
627 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
629 /* put system-speed load half-word into the pipeline */
630 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), 0, NULL, 0);
631 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
634 void arm9tdmi_load_byte_reg(target_t *target, int num)
636 /* get pointers to arch-specific information */
637 armv4_5_common_t *armv4_5 = target->arch_info;
638 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
639 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
641 /* put system-speed load byte into the pipeline */
642 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), 0, NULL, 0);
643 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
647 void arm9tdmi_store_word_regs(target_t *target, u32 mask)
649 /* get pointers to arch-specific information */
650 armv4_5_common_t *armv4_5 = target->arch_info;
651 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
652 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
654 /* put system-speed store-multiple into the pipeline */
655 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), 0, NULL, 0);
656 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
660 void arm9tdmi_store_hword_reg(target_t *target, int num)
662 /* get pointers to arch-specific information */
663 armv4_5_common_t *armv4_5 = target->arch_info;
664 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
665 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
667 /* put system-speed store half-word into the pipeline */
668 arm9tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), 0, NULL, 0);
669 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
673 void arm9tdmi_store_byte_reg(target_t *target, int num)
675 /* get pointers to arch-specific information */
676 armv4_5_common_t *armv4_5 = target->arch_info;
677 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
678 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
680 /* put system-speed store byte into the pipeline */
681 arm9tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), 0, NULL, 0);
682 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
686 void arm9tdmi_write_pc(target_t *target, u32 pc)
688 /* get pointers to arch-specific information */
689 armv4_5_common_t *armv4_5 = target->arch_info;
690 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
691 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
693 /* LDMIA r0-15, [r0] at debug speed
694 * register values will start to appear on 4th DCLK
696 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0, NULL, 0);
698 /* fetch NOP, LDM in DECODE stage */
699 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
700 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
701 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
702 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) (output data) */
703 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, pc, NULL, 0);
704 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
705 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
706 /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
707 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
708 /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
709 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
713 void arm9tdmi_branch_resume(target_t *target)
715 /* get pointers to arch-specific information */
716 armv4_5_common_t *armv4_5 = target->arch_info;
717 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
718 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
720 arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0);
721 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
725 void arm9tdmi_branch_resume_thumb(target_t *target)
729 /* get pointers to arch-specific information */
730 armv4_5_common_t *armv4_5 = target->arch_info;
731 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
732 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
733 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
735 /* LDMIA r0-15, [r0] at debug speed
736 * register values will start to appear on 4th DCLK
738 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x1, 0, 0), 0, NULL, 0);
740 /* fetch NOP, LDM in DECODE stage */
741 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
742 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
743 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
744 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
745 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) | 1, NULL, 0);
746 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
747 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
749 /* Branch and eXchange */
750 arm9tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0, NULL, 0);
752 embeddedice_read_reg(dbg_stat);
754 /* fetch NOP, BX in DECODE stage */
755 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
757 embeddedice_read_reg(dbg_stat);
759 /* fetch NOP, BX in EXECUTE stage (1st cycle) */
760 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
762 /* target is now in Thumb state */
763 embeddedice_read_reg(dbg_stat);
765 /* load r0 value, MOV_IM in Decode*/
766 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
767 /* fetch NOP, LDR in Decode, MOV_IM in Execute */
768 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
769 /* fetch NOP, LDR in Execute */
770 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
771 /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
772 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0);
773 /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
774 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
776 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
777 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
779 embeddedice_read_reg(dbg_stat);
781 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f7), 0, NULL, 1);
782 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
786 void arm9tdmi_enable_single_step(target_t *target)
788 /* get pointers to arch-specific information */
789 armv4_5_common_t *armv4_5 = target->arch_info;
790 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
792 if (arm7_9->has_single_step)
794 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 1);
795 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
799 arm7_9_enable_eice_step(target);
803 void arm9tdmi_disable_single_step(target_t *target)
805 /* get pointers to arch-specific information */
806 armv4_5_common_t *armv4_5 = target->arch_info;
807 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
809 if (arm7_9->has_single_step)
811 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 0);
812 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
816 arm7_9_disable_eice_step(target);
820 void arm9tdmi_build_reg_cache(target_t *target)
822 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
823 /* get pointers to arch-specific information */
824 armv4_5_common_t *armv4_5 = target->arch_info;
825 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
826 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
828 (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
829 armv4_5->core_cache = (*cache_p);
831 /* one extra register (vector catch) */
832 (*cache_p)->next = embeddedice_build_reg_cache(target, arm7_9);
833 arm7_9->eice_cache = (*cache_p)->next;
837 (*cache_p)->next->next = etm_build_reg_cache(target, jtag_info, 0);
838 arm7_9->etm_cache = (*cache_p)->next->next;
843 (*cache_p)->next->next->next = etb_build_reg_cache(arm7_9->etb);
844 arm7_9->etb->reg_cache = (*cache_p)->next->next->next;
848 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
851 arm9tdmi_build_reg_cache(target);
863 int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, int chain_pos, char *variant)
865 armv4_5_common_t *armv4_5;
866 arm7_9_common_t *arm7_9;
868 arm7_9 = &arm9tdmi->arm7_9_common;
869 armv4_5 = &arm7_9->armv4_5_common;
871 /* prepare JTAG information for the new target */
872 arm7_9->jtag_info.chain_pos = chain_pos;
873 arm7_9->jtag_info.scann_size = 5;
875 /* register arch-specific functions */
876 arm7_9->examine_debug_reason = arm9tdmi_examine_debug_reason;
877 arm7_9->change_to_arm = arm9tdmi_change_to_arm;
878 arm7_9->read_core_regs = arm9tdmi_read_core_regs;
879 arm7_9->read_core_regs_target_buffer = arm9tdmi_read_core_regs_target_buffer;
880 arm7_9->read_xpsr = arm9tdmi_read_xpsr;
882 arm7_9->write_xpsr = arm9tdmi_write_xpsr;
883 arm7_9->write_xpsr_im8 = arm9tdmi_write_xpsr_im8;
884 arm7_9->write_core_regs = arm9tdmi_write_core_regs;
886 arm7_9->load_word_regs = arm9tdmi_load_word_regs;
887 arm7_9->load_hword_reg = arm9tdmi_load_hword_reg;
888 arm7_9->load_byte_reg = arm9tdmi_load_byte_reg;
890 arm7_9->store_word_regs = arm9tdmi_store_word_regs;
891 arm7_9->store_hword_reg = arm9tdmi_store_hword_reg;
892 arm7_9->store_byte_reg = arm9tdmi_store_byte_reg;
894 arm7_9->write_pc = arm9tdmi_write_pc;
895 arm7_9->branch_resume = arm9tdmi_branch_resume;
896 arm7_9->branch_resume_thumb = arm9tdmi_branch_resume_thumb;
898 arm7_9->enable_single_step = arm9tdmi_enable_single_step;
899 arm7_9->disable_single_step = arm9tdmi_disable_single_step;
901 arm7_9->pre_debug_entry = NULL;
902 arm7_9->post_debug_entry = NULL;
904 arm7_9->pre_restore_context = NULL;
905 arm7_9->post_restore_context = NULL;
907 /* initialize arch-specific breakpoint handling */
908 buf_set_u32((u8*)(&arm7_9->arm_bkpt), 0, 32, 0xdeeedeee);
909 buf_set_u32((u8*)(&arm7_9->thumb_bkpt), 0, 16, 0xdeee);
911 arm7_9->sw_bkpts_use_wp = 1;
912 arm7_9->sw_bkpts_enabled = 0;
913 arm7_9->dbgreq_adjust_pc = 3;
914 arm7_9->arch_info = arm9tdmi;
916 arm9tdmi->common_magic = ARM9TDMI_COMMON_MAGIC;
917 arm9tdmi->arch_info = NULL;
921 arm9tdmi->variant = strdup(variant);
925 arm9tdmi->variant = strdup("");
928 arm7_9_init_arch_info(target, arm7_9);
930 /* override use of DBGRQ, this is safe on ARM9TDMI */
931 arm7_9->use_dbgrq = 1;
933 /* all ARM9s have the vector catch register */
934 arm7_9->has_vector_catch = 1;
939 /* target arm9tdmi <endianess> <startup_mode> <chain_pos> <variant>*/
940 int arm9tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
943 char *variant = NULL;
944 arm9tdmi_common_t *arm9tdmi = malloc(sizeof(arm9tdmi_common_t));
948 ERROR("'target arm9tdmi' requires at least one additional argument");
952 chain_pos = strtoul(args[3], NULL, 0);
957 arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
962 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx)
966 retval = arm7_9_register_commands(cmd_ctx);