git.sur5r.net Git - openocd/blob - src/target/arm9tdmi.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "arm9tdmi.h"
  25
  26 #include "arm7_9_common.h"
  27 #include "register.h"
  28 #include "target.h"
  29 #include "armv4_5.h"
  30 #include "embeddedice.h"
  31 #include "log.h"
  32 #include "jtag.h"
  33 #include "arm_jtag.h"
  34
  35 #include <stdlib.h>
  36 #include <string.h>
  37
  38 #if 0
  39 #define _DEBUG_INSTRUCTION_EXECUTION_
  40 #endif
  41
  42 /* cli handling */
  43 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx);
  44
  45 /* forward declarations */
  46 int arm9tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
  47 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
  48 int arm9tdmi_quit();
  49
  50 target_type_t arm9tdmi_target =
  51 {
  52         .name = "arm9tdmi",
  53
  54         .poll = arm7_9_poll,
  55         .arch_state = armv4_5_arch_state,
  56
  57         .halt = arm7_9_halt,
  58         .resume = arm7_9_resume,
  59         .step = arm7_9_step,
  60
  61         .assert_reset = arm7_9_assert_reset,
  62         .deassert_reset = arm7_9_deassert_reset,
  63         .soft_reset_halt = arm7_9_soft_reset_halt,
  64
  65         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
  66
  67         .read_memory = arm7_9_read_memory,
  68         .write_memory = arm7_9_write_memory,
  69         .bulk_write_memory = arm7_9_bulk_write_memory,
  70
  71         .run_algorithm = armv4_5_run_algorithm,
  72
  73         .add_breakpoint = arm7_9_add_breakpoint,
  74         .remove_breakpoint = arm7_9_remove_breakpoint,
  75         .add_watchpoint = arm7_9_add_watchpoint,
  76         .remove_watchpoint = arm7_9_remove_watchpoint,
  77
  78         .register_commands = arm9tdmi_register_commands,
  79         .target_command = arm9tdmi_target_command,
  80         .init_target = arm9tdmi_init_target,
  81         .quit = arm9tdmi_quit
  82 };
  83
  84 int arm9tdmi_examine_debug_reason(target_t *target)
  85 {
  86         /* get pointers to arch-specific information */
  87         armv4_5_common_t *armv4_5 = target->arch_info;
  88         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  89
  90         /* only check the debug reason if we don't know it already */
  91         if ((target->debug_reason != DBG_REASON_DBGRQ)
  92                         && (target->debug_reason != DBG_REASON_SINGLESTEP))
  93         {
  94                 scan_field_t fields[3];
  95                 u8 databus[4];
  96                 u8 instructionbus[4];
  97                 u8 debug_reason;
  98
  99                 jtag_add_end_state(TAP_PD);
 100
 101                 fields[0].device = arm7_9->jtag_info.chain_pos;
 102                 fields[0].num_bits = 32;
 103                 fields[0].out_value = NULL;
 104                 fields[0].out_mask = NULL;
 105                 fields[0].in_value = databus;
 106                 fields[0].in_check_value = NULL;
 107                 fields[0].in_check_mask = NULL;
 108                 fields[0].in_handler = NULL;
 109                 fields[0].in_handler_priv = NULL;
 110
 111                 fields[1].device = arm7_9->jtag_info.chain_pos;
 112                 fields[1].num_bits = 3;
 113                 fields[1].out_value = NULL;
 114                 fields[1].out_mask = NULL;
 115                 fields[1].in_value = &debug_reason;
 116                 fields[1].in_check_value = NULL;
 117                 fields[1].in_check_mask = NULL;
 118                 fields[1].in_handler = NULL;
 119                 fields[1].in_handler_priv = NULL;
 120
 121                 fields[2].device = arm7_9->jtag_info.chain_pos;
 122                 fields[2].num_bits = 32;
 123                 fields[2].out_value = NULL;
 124                 fields[2].out_mask = NULL;
 125                 fields[2].in_value = instructionbus;
 126                 fields[2].in_check_value = NULL;
 127                 fields[2].in_check_mask = NULL;
 128                 fields[2].in_handler = NULL;
 129                 fields[2].in_handler_priv = NULL;
 130
 131                 arm_jtag_scann(&arm7_9->jtag_info, 0x1);
 132                 arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr);
 133
 134                 jtag_add_dr_scan(3, fields, TAP_PD);
 135                 jtag_execute_queue();
 136
 137                 fields[0].in_value = NULL;
 138                 fields[0].out_value = databus;
 139                 fields[1].in_value = NULL;
 140                 fields[1].out_value = &debug_reason;
 141                 fields[2].in_value = NULL;
 142                 fields[2].out_value = instructionbus;
 143
 144                 jtag_add_dr_scan(3, fields, TAP_PD);
 145
 146                 if (debug_reason & 0x4)
 147                         if (debug_reason & 0x2)
 148                                 target->debug_reason = DBG_REASON_WPTANDBKPT;
 149                 else
 150                         target->debug_reason = DBG_REASON_WATCHPOINT;
 151                 else
 152                         target->debug_reason = DBG_REASON_BREAKPOINT;
 153         }
 154
 155         return ERROR_OK;
 156 }
 157
 158 /* put an instruction in the ARM9TDMI pipeline or write the data bus, and optionally read data */
 159 int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int sysspeed)
 160 {
 161         scan_field_t fields[3];
 162         u8 out_buf[4];
 163         u8 instr_buf[4];
 164         u8 sysspeed_buf = 0x0;
 165
 166         /* prepare buffer */
 167         buf_set_u32(out_buf, 0, 32, out);
 168
 169         buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
 170
 171         if (sysspeed)
 172                 buf_set_u32(&sysspeed_buf, 2, 1, 1);
 173
 174         jtag_add_end_state(TAP_PD);
 175         arm_jtag_scann(jtag_info, 0x1);
 176         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
 177
 178         fields[0].device = jtag_info->chain_pos;
 179         fields[0].num_bits = 32;
 180         fields[0].out_value = out_buf;
 181         fields[0].out_mask = NULL;
 182         fields[0].in_value = NULL;
 183         if (in)
 184         {
 185                 fields[0].in_handler = arm_jtag_buf_to_u32;
 186                 fields[0].in_handler_priv = in;
 187         }
 188         else
 189         {
 190                 fields[0].in_handler = NULL;
 191                 fields[0].in_handler_priv = NULL;
 192         }
 193         fields[0].in_check_value = NULL;
 194         fields[0].in_check_mask = NULL;
 195
 196         fields[1].device = jtag_info->chain_pos;
 197         fields[1].num_bits = 3;
 198         fields[1].out_value = &sysspeed_buf;
 199         fields[1].out_mask = NULL;
 200         fields[1].in_value = NULL;
 201         fields[1].in_check_value = NULL;
 202         fields[1].in_check_mask = NULL;
 203         fields[1].in_handler = NULL;
 204         fields[1].in_handler_priv = NULL;
 205
 206         fields[2].device = jtag_info->chain_pos;
 207         fields[2].num_bits = 32;
 208         fields[2].out_value = instr_buf;
 209         fields[2].out_mask = NULL;
 210         fields[2].in_value = NULL;
 211         fields[2].in_check_value = NULL;
 212         fields[2].in_check_mask = NULL;
 213         fields[2].in_handler = NULL;
 214         fields[2].in_handler_priv = NULL;
 215
 216         jtag_add_dr_scan(3, fields, -1);
 217
 218         jtag_add_runtest(0, -1);
 219
 220 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 221         {
 222                 jtag_execute_queue();
 223
 224                 if (in)
 225                 {
 226                         DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr, out, *in);
 227                 }
 228                 else
 229                         DEBUG("instr: 0x%8.8x, out: 0x%8.8x", instr, out);
 230         }
 231 #endif
 232
 233         return ERROR_OK;
 234 }
 235
 236 /* just read data (instruction and data-out = don't care) */
 237 int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
 238 {
 239         scan_field_t fields[3];
 240
 241         jtag_add_end_state(TAP_PD);
 242         arm_jtag_scann(jtag_info, 0x1);
 243         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
 244
 245         fields[0].device = jtag_info->chain_pos;
 246         fields[0].num_bits = 32;
 247         fields[0].out_value = NULL;
 248         fields[0].out_mask = NULL;
 249         fields[0].in_value = NULL;
 250         fields[0].in_handler = arm_jtag_buf_to_u32;
 251         fields[0].in_handler_priv = in;
 252         fields[0].in_check_value = NULL;
 253         fields[0].in_check_mask = NULL;
 254
 255         fields[1].device = jtag_info->chain_pos;
 256         fields[1].num_bits = 3;
 257         fields[1].out_value = NULL;
 258         fields[1].out_mask = NULL;
 259         fields[1].in_value = NULL;
 260         fields[1].in_handler = NULL;
 261         fields[1].in_handler_priv = NULL;
 262         fields[1].in_check_value = NULL;
 263         fields[1].in_check_mask = NULL;
 264
 265         fields[2].device = jtag_info->chain_pos;
 266         fields[2].num_bits = 32;
 267         fields[2].out_value = NULL;
 268         fields[2].out_mask = NULL;
 269         fields[2].in_value = NULL;
 270         fields[2].in_check_value = NULL;
 271         fields[2].in_check_mask = NULL;
 272         fields[2].in_handler = NULL;
 273         fields[2].in_handler_priv = NULL;
 274
 275         jtag_add_dr_scan(3, fields, -1);
 276
 277         jtag_add_runtest(0, -1);
 278
 279 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 280         {
 281                 jtag_execute_queue();
 282
 283                 if (in)
 284                 {
 285                         DEBUG("in: 0x%8.8x", *in);
 286                 }
 287                 else
 288                 {
 289                         ERROR("BUG: called with in == NULL");
 290                 }
 291         }
 292 #endif
 293
 294         return ERROR_OK;
 295 }
 296
 297 /* clock the target, and read the databus
 298  * the *in pointer points to a buffer where elements of 'size' bytes
 299  * are stored in big (be==1) or little (be==0) endianness
 300  */
 301 int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
 302 {
 303         scan_field_t fields[3];
 304
 305         jtag_add_end_state(TAP_PD);
 306         arm_jtag_scann(jtag_info, 0x1);
 307         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
 308
 309         fields[0].device = jtag_info->chain_pos;
 310         fields[0].num_bits = 32;
 311         fields[0].out_value = NULL;
 312         fields[0].out_mask = NULL;
 313         fields[0].in_value = NULL;
 314         switch (size)
 315         {
 316                 case 4:
 317                         fields[0].in_handler = (be) ? arm_jtag_buf_to_be32 : arm_jtag_buf_to_le32;
 318                         break;
 319                 case 2:
 320                         fields[0].in_handler = (be) ? arm_jtag_buf_to_be16 : arm_jtag_buf_to_le16;
 321                         break;
 322                 case 1:
 323                         fields[0].in_handler = arm_jtag_buf_to_8;
 324                         break;
 325         }
 326         fields[0].in_handler_priv = in;
 327         fields[0].in_check_value = NULL;
 328         fields[0].in_check_mask = NULL;
 329
 330         fields[1].device = jtag_info->chain_pos;
 331         fields[1].num_bits = 3;
 332         fields[1].out_value = NULL;
 333         fields[1].out_mask = NULL;
 334         fields[1].in_value = NULL;
 335         fields[1].in_handler = NULL;
 336         fields[1].in_handler_priv = NULL;
 337         fields[1].in_check_value = NULL;
 338         fields[1].in_check_mask = NULL;
 339
 340         fields[2].device = jtag_info->chain_pos;
 341         fields[2].num_bits = 32;
 342         fields[2].out_value = NULL;
 343         fields[2].out_mask = NULL;
 344         fields[2].in_value = NULL;
 345         fields[2].in_check_value = NULL;
 346         fields[2].in_check_mask = NULL;
 347         fields[2].in_handler = NULL;
 348         fields[2].in_handler_priv = NULL;
 349
 350         jtag_add_dr_scan(3, fields, -1);
 351
 352         jtag_add_runtest(0, -1);
 353
 354 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 355         {
 356                 jtag_execute_queue();
 357
 358                 if (in)
 359                 {
 360                         DEBUG("in: 0x%8.8x", *in);
 361                 }
 362                 else
 363                 {
 364                         ERROR("BUG: called with in == NULL");
 365                 }
 366         }
 367 #endif
 368
 369         return ERROR_OK;
 370 }
 371
 372 void arm9tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
 373 {
 374         /* get pointers to arch-specific information */
 375         armv4_5_common_t *armv4_5 = target->arch_info;
 376         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 377         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 378
 379         /* save r0 before using it and put system in ARM state
 380          * to allow common handling of ARM and THUMB debugging */
 381
 382         /* fetch STR r0, [r0] */
 383         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
 384         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 385         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 386         /* STR r0, [r0] in Memory */
 387         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, r0, 0);
 388
 389         /* MOV r0, r15 fetched, STR in Decode */
 390         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), 0, NULL, 0);
 391         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 392         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
 393         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 394         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 395         /* nothing fetched, STR r0, [r0] in Memory */
 396         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, pc, 0);
 397
 398         /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
 399         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
 400         /* LDR in Decode */
 401         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 402         /* LDR in Execute */
 403         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 404         /* LDR in Memory (to account for interlock) */
 405         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 406
 407         /* fetch BX */
 408         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), 0, NULL, 0);
 409         /* NOP fetched, BX in Decode, MOV in Execute */
 410         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 411         /* NOP fetched, BX in Execute (1) */
 412         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 413
 414         jtag_execute_queue();
 415
 416         /* fix program counter:
 417          * MOV r0, r15 was the 5th instruction (+8)
 418          * reading PC in Thumb state gives address of instruction + 4
 419          */
 420         *pc -= 0xc;
 421 }
 422
 423 void arm9tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
 424 {
 425         int i;
 426         /* get pointers to arch-specific information */
 427         armv4_5_common_t *armv4_5 = target->arch_info;
 428         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 429         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 430
 431         /* STMIA r0-15, [r0] at debug speed
 432          * register values will start to appear on 4th DCLK
 433          */
 434         arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
 435
 436         /* fetch NOP, STM in DECODE stage */
 437         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 438         /* fetch NOP, STM in EXECUTE stage (1st cycle) */
 439         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 440
 441         for (i = 0; i <= 15; i++)
 442         {
 443                 if (mask & (1 << i))
 444                         /* nothing fetched, STM in MEMORY (i'th cycle) */
 445                         arm9tdmi_clock_data_in(jtag_info, core_regs[i]);
 446         }
 447
 448 }
 449
 450 void arm9tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
 451 {
 452         int i;
 453         /* get pointers to arch-specific information */
 454         armv4_5_common_t *armv4_5 = target->arch_info;
 455         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 456         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 457         int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
 458         u32 *buf_u32 = buffer;
 459         u16 *buf_u16 = buffer;
 460         u8 *buf_u8 = buffer;
 461
 462         /* STMIA r0-15, [r0] at debug speed
 463          * register values will start to appear on 4th DCLK
 464          */
 465         arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
 466
 467         /* fetch NOP, STM in DECODE stage */
 468         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 469         /* fetch NOP, STM in EXECUTE stage (1st cycle) */
 470         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 471
 472         for (i = 0; i <= 15; i++)
 473         {
 474                 if (mask & (1 << i))
 475                         /* nothing fetched, STM in MEMORY (i'th cycle) */
 476                         switch (size)
 477                         {
 478                                 case 4:
 479                                         arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
 480                                         break;
 481                                 case 2:
 482                                         arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
 483                                         break;
 484                                 case 1:
 485                                         arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
 486                                         break;
 487                         }
 488         }
 489
 490 }
 491
 492 void arm9tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
 493 {
 494         /* get pointers to arch-specific information */
 495         armv4_5_common_t *armv4_5 = target->arch_info;
 496         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 497         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 498
 499         /* MRS r0, cpsr */
 500         arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
 501         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 502         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 503         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 504         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 505
 506         /* STR r0, [r15] */
 507         arm9tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), 0, NULL, 0);
 508         /* fetch NOP, STR in DECODE stage */
 509         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 510         /* fetch NOP, STR in EXECUTE stage (1st cycle) */
 511         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 512         /* nothing fetched, STR in MEMORY */
 513         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
 514
 515 }
 516
 517 void arm9tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
 518 {
 519         /* get pointers to arch-specific information */
 520         armv4_5_common_t *armv4_5 = target->arch_info;
 521         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 522         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 523
 524         DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
 525
 526         /* MSR1 fetched */
 527         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
 528         /* MSR2 fetched, MSR1 in DECODE */
 529         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), 0, NULL, 0);
 530         /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
 531         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), 0, NULL, 0);
 532         /* nothing fetched, MSR1 in EXECUTE (2) */
 533         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 534         /* nothing fetched, MSR1 in EXECUTE (3) */
 535         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 536         /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
 537         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), 0, NULL, 0);
 538         /* nothing fetched, MSR2 in EXECUTE (2) */
 539         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 540         /* nothing fetched, MSR2 in EXECUTE (3) */
 541         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 542         /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
 543         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 544         /* nothing fetched, MSR3 in EXECUTE (2) */
 545         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 546         /* nothing fetched, MSR3 in EXECUTE (3) */
 547         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 548         /* NOP fetched, MSR4 in EXECUTE (1) */
 549         /* last MSR writes flags, which takes only one cycle */
 550         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 551 }
 552
 553 void arm9tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
 554 {
 555         /* get pointers to arch-specific information */
 556         armv4_5_common_t *armv4_5 = target->arch_info;
 557         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 558         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 559
 560         DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
 561
 562         /* MSR fetched */
 563         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0);
 564         /* NOP fetched, MSR in DECODE */
 565         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 566         /* NOP fetched, MSR in EXECUTE (1) */
 567         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 568
 569         /* rot == 4 writes flags, which takes only one cycle */
 570         if (rot != 4)
 571         {
 572                 /* nothing fetched, MSR in EXECUTE (2) */
 573                 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 574                 /* nothing fetched, MSR in EXECUTE (3) */
 575                 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 576         }
 577 }
 578
 579 void arm9tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
 580 {
 581         int i;
 582         /* get pointers to arch-specific information */
 583         armv4_5_common_t *armv4_5 = target->arch_info;
 584         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 585         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 586
 587         /* LDMIA r0-15, [r0] at debug speed
 588         * register values will start to appear on 4th DCLK
 589         */
 590         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
 591
 592         /* fetch NOP, LDM in DECODE stage */
 593         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 594         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 595         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 596
 597         for (i = 0; i <= 15; i++)
 598         {
 599                 if (mask & (1 << i))
 600                         /* nothing fetched, LDM still in EXECUTE (1+i cycle) */
 601                         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0);
 602         }
 603         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 604
 605 }
 606
 607 void arm9tdmi_load_word_regs(target_t *target, u32 mask)
 608 {
 609         /* get pointers to arch-specific information */
 610         armv4_5_common_t *armv4_5 = target->arch_info;
 611         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 612         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 613
 614         /* put system-speed load-multiple into the pipeline */
 615         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), 0, NULL, 0);
 616         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 617
 618 }
 619
 620 void arm9tdmi_load_hword_reg(target_t *target, int num)
 621 {
 622         /* get pointers to arch-specific information */
 623         armv4_5_common_t *armv4_5 = target->arch_info;
 624         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 625         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 626
 627         /* put system-speed load half-word into the pipeline */
 628         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), 0, NULL, 0);
 629         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 630 }
 631
 632 void arm9tdmi_load_byte_reg(target_t *target, int num)
 633 {
 634         /* get pointers to arch-specific information */
 635         armv4_5_common_t *armv4_5 = target->arch_info;
 636         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 637         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 638
 639         /* put system-speed load byte into the pipeline */
 640         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), 0, NULL, 0);
 641         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 642
 643 }
 644
 645 void arm9tdmi_store_word_regs(target_t *target, u32 mask)
 646 {
 647         /* get pointers to arch-specific information */
 648         armv4_5_common_t *armv4_5 = target->arch_info;
 649         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 650         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 651
 652         /* put system-speed store-multiple into the pipeline */
 653         arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), 0, NULL, 0);
 654         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 655
 656 }
 657
 658 void arm9tdmi_store_hword_reg(target_t *target, int num)
 659 {
 660         /* get pointers to arch-specific information */
 661         armv4_5_common_t *armv4_5 = target->arch_info;
 662         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 663         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 664
 665         /* put system-speed store half-word into the pipeline */
 666         arm9tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), 0, NULL, 0);
 667         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 668
 669 }
 670
 671 void arm9tdmi_store_byte_reg(target_t *target, int num)
 672 {
 673         /* get pointers to arch-specific information */
 674         armv4_5_common_t *armv4_5 = target->arch_info;
 675         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 676         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 677
 678         /* put system-speed store byte into the pipeline */
 679         arm9tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), 0, NULL, 0);
 680         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 681
 682 }
 683
 684 void arm9tdmi_write_pc(target_t *target, u32 pc)
 685 {
 686         /* get pointers to arch-specific information */
 687         armv4_5_common_t *armv4_5 = target->arch_info;
 688         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 689         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 690
 691         /* LDMIA r0-15, [r0] at debug speed
 692          * register values will start to appear on 4th DCLK
 693          */
 694         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0, NULL, 0);
 695
 696         /* fetch NOP, LDM in DECODE stage */
 697         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 698         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 699         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 700         /* nothing fetched, LDM in EXECUTE stage (2nd cycle) (output data) */
 701         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, pc, NULL, 0);
 702         /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
 703         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 704         /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
 705         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 706         /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
 707         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 708
 709 }
 710
 711 void arm9tdmi_branch_resume(target_t *target)
 712 {
 713         /* get pointers to arch-specific information */
 714         armv4_5_common_t *armv4_5 = target->arch_info;
 715         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 716         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 717
 718         arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0);
 719         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 720
 721 }
 722
 723 void arm9tdmi_branch_resume_thumb(target_t *target)
 724 {
 725         DEBUG("");
 726
 727         /* get pointers to arch-specific information */
 728         armv4_5_common_t *armv4_5 = target->arch_info;
 729         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 730         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 731         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 732
 733         /* LDMIA r0-15, [r0] at debug speed
 734         * register values will start to appear on 4th DCLK
 735         */
 736         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x1, 0, 0), 0, NULL, 0);
 737
 738         /* fetch NOP, LDM in DECODE stage */
 739         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 740         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 741         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 742         /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
 743         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) | 1, NULL, 0);
 744         /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
 745         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 746
 747         /* Branch and eXchange */
 748         arm9tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0, NULL, 0);
 749
 750         embeddedice_read_reg(dbg_stat);
 751
 752         /* fetch NOP, BX in DECODE stage */
 753         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 754
 755         embeddedice_read_reg(dbg_stat);
 756
 757         /* fetch NOP, BX in EXECUTE stage (1st cycle) */
 758         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 759
 760         /* target is now in Thumb state */
 761         embeddedice_read_reg(dbg_stat);
 762
 763         /* load r0 value, MOV_IM in Decode*/
 764         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
 765         /* fetch NOP, LDR in Decode, MOV_IM in Execute */
 766         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 767         /* fetch NOP, LDR in Execute */
 768         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 769         /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
 770         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0);
 771         /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
 772         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 773
 774         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 775         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 776
 777         embeddedice_read_reg(dbg_stat);
 778
 779         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f7), 0, NULL, 1);
 780         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 781
 782 }
 783
 784 void arm9tdmi_enable_single_step(target_t *target)
 785 {
 786         /* get pointers to arch-specific information */
 787         armv4_5_common_t *armv4_5 = target->arch_info;
 788         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 789         arm9tdmi_common_t *arm9 = arm7_9->arch_info;
 790
 791         if (arm7_9->has_single_step)
 792         {
 793                 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 1);
 794                 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
 795         }
 796         else
 797         {
 798                 arm7_9_enable_eice_step(target);
 799         }
 800 }
 801
 802 void arm9tdmi_disable_single_step(target_t *target)
 803 {
 804         /* get pointers to arch-specific information */
 805         armv4_5_common_t *armv4_5 = target->arch_info;
 806         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 807         arm9tdmi_common_t *arm9 = arm7_9->arch_info;
 808
 809         if (arm7_9->has_single_step)
 810         {
 811                 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 0);
 812                 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
 813         }
 814         else
 815         {
 816                 arm7_9_disable_eice_step(target);
 817         }
 818 }
 819
 820 void arm9tdmi_build_reg_cache(target_t *target)
 821 {
 822         reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
 823         /* get pointers to arch-specific information */
 824         armv4_5_common_t *armv4_5 = target->arch_info;
 825         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 826         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 827         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 828
 829         embeddedice_reg_t *vec_catch_arch_info;
 830
 831         (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
 832         armv4_5->core_cache = (*cache_p);
 833
 834         /* one extra register (vector catch) */
 835         (*cache_p)->next = embeddedice_build_reg_cache(target, arm7_9);
 836         arm7_9->eice_cache = (*cache_p)->next;
 837
 838 #if 0
 839         (*cache_p)->next->reg_list[EICE_VEC_CATCH].name = "vector catch";
 840         (*cache_p)->next->reg_list[EICE_VEC_CATCH].dirty = 0;
 841         (*cache_p)->next->reg_list[EICE_VEC_CATCH].valid = 0;
 842         (*cache_p)->next->reg_list[EICE_VEC_CATCH].bitfield_desc = NULL;
 843         (*cache_p)->next->reg_list[EICE_VEC_CATCH].num_bitfields = 0;
 844         (*cache_p)->next->reg_list[EICE_VEC_CATCH].size = 8;
 845         (*cache_p)->next->reg_list[EICE_VEC_CATCH].value = calloc(1, 4);
 846         vec_catch_arch_info = (*cache_p)->next->reg_list[EICE_VEC_CATCH].arch_info;
 847         vec_catch_arch_info->addr = 0x2;
 848 #endif
 849 }
 850
 851 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 852 {
 853
 854         arm9tdmi_build_reg_cache(target);
 855
 856         return ERROR_OK;
 857
 858 }
 859
 860 int arm9tdmi_quit()
 861 {
 862
 863         return ERROR_OK;
 864 }
 865
 866 int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, int chain_pos, char *variant)
 867 {
 868         armv4_5_common_t *armv4_5;
 869         arm7_9_common_t *arm7_9;
 870
 871         arm7_9 = &arm9tdmi->arm7_9_common;
 872         armv4_5 = &arm7_9->armv4_5_common;
 873
 874         /* prepare JTAG information for the new target */
 875         arm7_9->jtag_info.chain_pos = chain_pos;
 876         arm7_9->jtag_info.scann_size = 5;
 877
 878         /* register arch-specific functions */
 879         arm7_9->examine_debug_reason = arm9tdmi_examine_debug_reason;
 880         arm7_9->change_to_arm = arm9tdmi_change_to_arm;
 881         arm7_9->read_core_regs = arm9tdmi_read_core_regs;
 882         arm7_9->read_core_regs_target_buffer = arm9tdmi_read_core_regs_target_buffer;
 883         arm7_9->read_xpsr = arm9tdmi_read_xpsr;
 884
 885         arm7_9->write_xpsr = arm9tdmi_write_xpsr;
 886         arm7_9->write_xpsr_im8 = arm9tdmi_write_xpsr_im8;
 887         arm7_9->write_core_regs = arm9tdmi_write_core_regs;
 888
 889         arm7_9->load_word_regs = arm9tdmi_load_word_regs;
 890         arm7_9->load_hword_reg = arm9tdmi_load_hword_reg;
 891         arm7_9->load_byte_reg = arm9tdmi_load_byte_reg;
 892
 893         arm7_9->store_word_regs = arm9tdmi_store_word_regs;
 894         arm7_9->store_hword_reg = arm9tdmi_store_hword_reg;
 895         arm7_9->store_byte_reg = arm9tdmi_store_byte_reg;
 896
 897         arm7_9->write_pc = arm9tdmi_write_pc;
 898         arm7_9->branch_resume = arm9tdmi_branch_resume;
 899         arm7_9->branch_resume_thumb = arm9tdmi_branch_resume_thumb;
 900
 901         arm7_9->enable_single_step = arm9tdmi_enable_single_step;
 902         arm7_9->disable_single_step = arm9tdmi_disable_single_step;
 903
 904         arm7_9->pre_debug_entry = NULL;
 905         arm7_9->post_debug_entry = NULL;
 906
 907         arm7_9->pre_restore_context = NULL;
 908         arm7_9->post_restore_context = NULL;
 909
 910         /* initialize arch-specific breakpoint handling */
 911         buf_set_u32((u8*)(&arm7_9->arm_bkpt), 0, 32, 0xdeeedeee);
 912         buf_set_u32((u8*)(&arm7_9->thumb_bkpt), 0, 16, 0xdeee);
 913
 914         arm7_9->sw_bkpts_use_wp = 1;
 915         arm7_9->sw_bkpts_enabled = 0;
 916         arm7_9->dbgreq_adjust_pc = 3;
 917         arm7_9->arch_info = arm9tdmi;
 918
 919         arm9tdmi->common_magic = ARM9TDMI_COMMON_MAGIC;
 920         arm9tdmi->arch_info = NULL;
 921
 922         if (variant)
 923         {
 924                 arm9tdmi->variant = strdup(variant);
 925         }
 926         else
 927         {
 928                 arm9tdmi->variant = strdup("");
 929         }
 930
 931         arm7_9_init_arch_info(target, arm7_9);
 932
 933         /* override use of DBGRQ, this is safe on ARM9TDMI */
 934         arm7_9->use_dbgrq = 1;
 935
 936         /* all ARM9s have the vector catch register */
 937         arm7_9->has_vector_catch = 1;
 938
 939         return ERROR_OK;
 940 }
 941
 942 /* target arm9tdmi <endianess> <startup_mode> <chain_pos> <variant>*/
 943 int arm9tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
 944 {
 945         int chain_pos;
 946         char *variant = NULL;
 947         arm9tdmi_common_t *arm9tdmi = malloc(sizeof(arm9tdmi_common_t));
 948
 949         if (argc < 4)
 950         {
 951                 ERROR("'target arm9tdmi' requires at least one additional argument");
 952                 exit(-1);
 953         }
 954
 955         chain_pos = strtoul(args[3], NULL, 0);
 956
 957         if (argc >= 5)
 958                 variant = args[4];
 959
 960         arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
 961
 962         return ERROR_OK;
 963 }
 964
 965 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx)
 966 {
 967         int retval;
 968
 969         retval = arm7_9_register_commands(cmd_ctx);
 970
 971         return ERROR_OK;
 972
 973 }
 974