1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * Copyright (C) 2009-2010 by David Brownell *
13 * Copyright (C) 2013 by Andreas Fritiofson *
14 * andreas.fritiofson@gmail.com *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published by *
18 * the Free Software Foundation; either version 2 of the License, or *
19 * (at your option) any later version. *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
26 * You should have received a copy of the GNU General Public License *
27 * along with this program; if not, write to the *
28 * Free Software Foundation, Inc., *
29 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
30 ***************************************************************************/
34 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
35 * debugging architecture. Compared with previous versions, this includes
36 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
37 * transport, and focusses on memory mapped resources as defined by the
38 * CoreSight architecture.
40 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
41 * basic components: a Debug Port (DP) transporting messages to and from a
42 * debugger, and an Access Port (AP) accessing resources. Three types of DP
43 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
44 * One uses only SWD for communication, and is called SW-DP. The third can
45 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
46 * is used to access memory mapped resources and is called a MEM-AP. Also a
47 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
49 * This programming interface allows DAP pipelined operations through a
50 * transaction queue. This primarily affects AP operations (such as using
51 * a MEM-AP to access memory or registers). If the current transaction has
52 * not finished by the time the next one must begin, and the ORUNDETECT bit
53 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
54 * further AP operations will fail. There are two basic methods to avoid
55 * such overrun errors. One involves polling for status instead of using
56 * transaction piplining. The other involves adding delays to ensure the
57 * AP has enough time to complete one operation before starting the next
58 * one. (For JTAG these delays are controlled by memaccess_tck.)
62 * Relevant specifications from ARM include:
64 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
65 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
67 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
68 * Cortex-M3(tm) TRM, ARM DDI 0337G
75 #include "jtag/interface.h"
77 #include "arm_adi_v5.h"
78 #include <helper/time_support.h>
80 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
83 uint32_t tar_block_size(uint32_t address)
84 Return the largest block starting at address that does not cross a tar block size alignment boundary
86 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
88 return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
91 /***************************************************************************
93 * DP and MEM-AP register access through APACC and DPACC *
95 ***************************************************************************/
98 * Select one of the APs connected to the specified DAP. The
99 * selection is implicitly used with future AP transactions.
100 * This is a NOP if the specified AP is already selected.
103 * @param apsel Number of the AP to (implicitly) use with further
104 * transactions. This normally identifies a MEM-AP.
106 void dap_ap_select(struct adiv5_dap *dap, uint8_t ap)
108 uint32_t new_ap = (ap << 24) & 0xFF000000;
110 if (new_ap != dap->ap_current) {
111 dap->ap_current = new_ap;
112 /* Switching AP invalidates cached values.
113 * Values MUST BE UPDATED BEFORE AP ACCESS.
115 dap->ap_bank_value = -1;
116 dap->ap_csw_value = -1;
117 dap->ap_tar_value = -1;
121 static int dap_setup_accessport_csw(struct adiv5_dap *dap, uint32_t csw)
123 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT |
124 dap->apcsw[dap->ap_current >> 24];
126 if (csw != dap->ap_csw_value) {
127 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
128 int retval = dap_queue_ap_write(dap, AP_REG_CSW, csw);
129 if (retval != ERROR_OK)
131 dap->ap_csw_value = csw;
136 static int dap_setup_accessport_tar(struct adiv5_dap *dap, uint32_t tar)
138 if (tar != dap->ap_tar_value || dap->ap_csw_value & CSW_ADDRINC_MASK) {
139 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
140 int retval = dap_queue_ap_write(dap, AP_REG_TAR, tar);
141 if (retval != ERROR_OK)
143 dap->ap_tar_value = tar;
149 * Queue transactions setting up transfer parameters for the
150 * currently selected MEM-AP.
152 * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
153 * initiate data reads or writes using memory or peripheral addresses.
154 * If the CSW is configured for it, the TAR may be automatically
155 * incremented after each transfer.
157 * @todo Rename to reflect it being specifically a MEM-AP function.
159 * @param dap The DAP connected to the MEM-AP.
160 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
161 * matches the cached value, the register is not changed.
162 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
163 * matches the cached address, the register is not changed.
165 * @return ERROR_OK if the transaction was properly queued, else a fault code.
167 int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
170 retval = dap_setup_accessport_csw(dap, csw);
171 if (retval != ERROR_OK)
173 retval = dap_setup_accessport_tar(dap, tar);
174 if (retval != ERROR_OK)
180 * Asynchronous (queued) read of a word from memory or a system register.
182 * @param dap The DAP connected to the MEM-AP performing the read.
183 * @param address Address of the 32-bit word to read; it must be
184 * readable by the currently selected MEM-AP.
185 * @param value points to where the word will be stored when the
186 * transaction queue is flushed (assuming no errors).
188 * @return ERROR_OK for success. Otherwise a fault code.
190 int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
195 /* Use banked addressing (REG_BDx) to avoid some link traffic
196 * (updating TAR) when reading several consecutive addresses.
198 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
199 address & 0xFFFFFFF0);
200 if (retval != ERROR_OK)
203 return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value);
207 * Synchronous read of a word from memory or a system register.
208 * As a side effect, this flushes any queued transactions.
210 * @param dap The DAP connected to the MEM-AP performing the read.
211 * @param address Address of the 32-bit word to read; it must be
212 * readable by the currently selected MEM-AP.
213 * @param value points to where the result will be stored.
215 * @return ERROR_OK for success; *value holds the result.
216 * Otherwise a fault code.
218 int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
223 retval = mem_ap_read_u32(dap, address, value);
224 if (retval != ERROR_OK)
231 * Asynchronous (queued) write of a word to memory or a system register.
233 * @param dap The DAP connected to the MEM-AP.
234 * @param address Address to be written; it must be writable by
235 * the currently selected MEM-AP.
236 * @param value Word that will be written to the address when transaction
237 * queue is flushed (assuming no errors).
239 * @return ERROR_OK for success. Otherwise a fault code.
241 int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
246 /* Use banked addressing (REG_BDx) to avoid some link traffic
247 * (updating TAR) when writing several consecutive addresses.
249 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
250 address & 0xFFFFFFF0);
251 if (retval != ERROR_OK)
254 return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC),
259 * Synchronous write of a word to memory or a system register.
260 * As a side effect, this flushes any queued transactions.
262 * @param dap The DAP connected to the MEM-AP.
263 * @param address Address to be written; it must be writable by
264 * the currently selected MEM-AP.
265 * @param value Word that will be written.
267 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
269 int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
272 int retval = mem_ap_write_u32(dap, address, value);
274 if (retval != ERROR_OK)
281 * Synchronous write of a block of memory, using a specific access size.
283 * @param dap The DAP connected to the MEM-AP.
284 * @param buffer The data buffer to write. No particular alignment is assumed.
285 * @param size Which access size to use, in bytes. 1, 2 or 4.
286 * @param count The number of writes to do (in size units, not bytes).
287 * @param address Address to be written; it must be writable by the currently selected MEM-AP.
288 * @param addrinc Whether the target address should be increased for each write or not. This
289 * should normally be true, except when writing to e.g. a FIFO.
290 * @return ERROR_OK on success, otherwise an error code.
292 int mem_ap_write(struct adiv5_dap *dap, const uint8_t *buffer, uint32_t size, uint32_t count,
293 uint32_t address, bool addrinc)
295 size_t nbytes = size * count;
296 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
301 csw_size = CSW_32BIT;
303 csw_size = CSW_16BIT;
307 return ERROR_TARGET_UNALIGNED_ACCESS;
309 retval = dap_setup_accessport_tar(dap, address);
310 if (retval != ERROR_OK)
314 uint32_t this_size = size;
316 /* Select packed transfer if possible */
317 if (addrinc && dap->packed_transfers && nbytes >= 4
318 && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
320 retval = dap_setup_accessport_csw(dap, csw_size | CSW_ADDRINC_PACKED);
322 retval = dap_setup_accessport_csw(dap, csw_size | csw_addrincr);
325 if (retval != ERROR_OK)
328 /* How many source bytes each transfer will consume, and their location in the DRW,
329 * depends on the type of transfer and alignment. See ARM document IHI0031C. */
330 uint32_t outvalue = 0;
333 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
334 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
336 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
338 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
343 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
344 if (retval != ERROR_OK)
347 /* Rewrite TAR if it wrapped */
348 if (addrinc && address % dap->tar_autoincr_block < size && nbytes > 0) {
349 retval = dap_setup_accessport_tar(dap, address);
350 if (retval != ERROR_OK)
355 /* REVISIT: Might want to have a queued version of this function that does not run. */
356 if (retval == ERROR_OK)
357 retval = dap_run(dap);
359 if (retval != ERROR_OK) {
361 if (dap_queue_ap_read(dap, AP_REG_TAR, &tar) == ERROR_OK
362 && dap_run(dap) == ERROR_OK)
363 LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
365 LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
371 /* Compatibility wrappers around mem_ap_write(). Note that the count is in bytes for these. */
372 int mem_ap_write_buf_u32(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address, bool addr_incr)
374 return mem_ap_write(dap, buffer, 4, count / 4, address, true);
377 int mem_ap_write_buf_u16(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
379 return mem_ap_write(dap, buffer, 2, count / 2, address, true);
382 int mem_ap_write_buf_u8(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
384 return mem_ap_write(dap, buffer, 1, count, address, true);
388 * Synchronous read of a block of memory, using a specific access size.
390 * @param dap The DAP connected to the MEM-AP.
391 * @param buffer The data buffer to receive the data. No particular alignment is assumed.
392 * @param size Which access size to use, in bytes. 1, 2 or 4.
393 * @param count The number of reads to do (in size units, not bytes).
394 * @param address Address to be read; it must be readable by the currently selected MEM-AP.
395 * @param addrinc Whether the target address should be increased after each read or not. This
396 * should normally be true, except when reading from e.g. a FIFO.
397 * @return ERROR_OK on success, otherwise an error code.
399 int mem_ap_read(struct adiv5_dap *dap, uint8_t *buffer, uint32_t size, uint32_t count,
400 uint32_t adr, bool addrinc)
402 size_t nbytes = size * count;
403 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
405 uint32_t address = adr;
409 csw_size = CSW_32BIT;
411 csw_size = CSW_16BIT;
415 return ERROR_TARGET_UNALIGNED_ACCESS;
417 /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
418 * over-allocation if packed transfers are going to be used, but determining the real need at
419 * this point would be messy. */
420 uint32_t *read_buf = malloc(count * sizeof(uint32_t));
421 uint32_t *read_ptr = read_buf;
422 if (read_buf == NULL) {
423 LOG_ERROR("Failed to allocate read buffer");
427 retval = dap_setup_accessport_tar(dap, address);
428 if (retval != ERROR_OK)
431 /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
432 * useful bytes it contains, and their location in the word, depends on the type of transfer
435 uint32_t this_size = size;
437 /* Select packed transfer if possible */
438 if (addrinc && dap->packed_transfers && nbytes >= 4
439 && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
441 retval = dap_setup_accessport_csw(dap, csw_size | CSW_ADDRINC_PACKED);
443 retval = dap_setup_accessport_csw(dap, csw_size | csw_addrincr);
445 if (retval != ERROR_OK)
448 retval = dap_queue_ap_read(dap, AP_REG_DRW, read_ptr++);
449 if (retval != ERROR_OK)
453 address += this_size;
455 /* Rewrite TAR if it wrapped */
456 if (addrinc && address % dap->tar_autoincr_block < size && nbytes > 0) {
457 retval = dap_setup_accessport_tar(dap, address);
458 if (retval != ERROR_OK)
463 if (retval == ERROR_OK)
464 retval = dap_run(dap);
468 nbytes = size * count;
471 /* If something failed, read TAR to find out how much data was successfully read, so we can
472 * at least give the caller what we have. */
473 if (retval != ERROR_OK) {
475 if (dap_queue_ap_read(dap, AP_REG_TAR, &tar) == ERROR_OK
476 && dap_run(dap) == ERROR_OK) {
477 LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
478 if (nbytes > tar - address)
479 nbytes = tar - address;
481 LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
486 /* Replay loop to populate caller's buffer from the correct word and byte lane */
488 uint32_t this_size = size;
490 if (addrinc && dap->packed_transfers && nbytes >= 4
491 && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
497 *buffer++ = *read_ptr >> 8 * (address++ & 3);
498 *buffer++ = *read_ptr >> 8 * (address++ & 3);
500 *buffer++ = *read_ptr >> 8 * (address++ & 3);
502 *buffer++ = *read_ptr >> 8 * (address++ & 3);
513 /* Compatibility wrappers around mem_ap_read(). Note that the count is in bytes for these (despite
514 * what their doxygen documentation said). */
515 int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer,
516 int count, uint32_t address, bool addr_incr)
518 return mem_ap_read(dap, buffer, 4, count / 4, address, addr_incr);
521 int mem_ap_read_buf_u16(struct adiv5_dap *dap, uint8_t *buffer,
522 int count, uint32_t address)
524 return mem_ap_read(dap, buffer, 2, count / 2, address, true);
527 int mem_ap_read_buf_u8(struct adiv5_dap *dap, uint8_t *buffer,
528 int count, uint32_t address)
530 return mem_ap_read(dap, buffer, 1, count, address, true);
533 /*--------------------------------------------------------------------*/
534 /* Wrapping function with selection of AP */
535 /*--------------------------------------------------------------------*/
536 int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
537 uint32_t address, uint32_t *value)
539 dap_ap_select(swjdp, ap);
540 return mem_ap_read_u32(swjdp, address, value);
543 int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap,
544 uint32_t address, uint32_t value)
546 dap_ap_select(swjdp, ap);
547 return mem_ap_write_u32(swjdp, address, value);
550 int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
551 uint32_t address, uint32_t *value)
553 dap_ap_select(swjdp, ap);
554 return mem_ap_read_atomic_u32(swjdp, address, value);
557 int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
558 uint32_t address, uint32_t value)
560 dap_ap_select(swjdp, ap);
561 return mem_ap_write_atomic_u32(swjdp, address, value);
564 int mem_ap_sel_read_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
565 uint8_t *buffer, int count, uint32_t address)
567 dap_ap_select(swjdp, ap);
568 return mem_ap_read_buf_u8(swjdp, buffer, count, address);
571 int mem_ap_sel_read_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
572 uint8_t *buffer, int count, uint32_t address)
574 dap_ap_select(swjdp, ap);
575 return mem_ap_read_buf_u16(swjdp, buffer, count, address);
578 int mem_ap_sel_read_buf_u32_noincr(struct adiv5_dap *swjdp, uint8_t ap,
579 uint8_t *buffer, int count, uint32_t address)
581 dap_ap_select(swjdp, ap);
582 return mem_ap_read_buf_u32(swjdp, buffer, count, address, false);
585 int mem_ap_sel_read_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
586 uint8_t *buffer, int count, uint32_t address)
588 dap_ap_select(swjdp, ap);
589 return mem_ap_read_buf_u32(swjdp, buffer, count, address, true);
592 int mem_ap_sel_write_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
593 const uint8_t *buffer, int count, uint32_t address)
595 dap_ap_select(swjdp, ap);
596 return mem_ap_write_buf_u8(swjdp, buffer, count, address);
599 int mem_ap_sel_write_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
600 const uint8_t *buffer, int count, uint32_t address)
602 dap_ap_select(swjdp, ap);
603 return mem_ap_write_buf_u16(swjdp, buffer, count, address);
606 int mem_ap_sel_write_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
607 const uint8_t *buffer, int count, uint32_t address)
609 dap_ap_select(swjdp, ap);
610 return mem_ap_write_buf_u32(swjdp, buffer, count, address, true);
613 int mem_ap_sel_write_buf_u32_noincr(struct adiv5_dap *swjdp, uint8_t ap,
614 const uint8_t *buffer, int count, uint32_t address)
616 dap_ap_select(swjdp, ap);
617 return mem_ap_write_buf_u32(swjdp, buffer, count, address, false);
620 #define MDM_REG_STAT 0x00
621 #define MDM_REG_CTRL 0x04
622 #define MDM_REG_ID 0xfc
624 #define MDM_STAT_FMEACK (1<<0)
625 #define MDM_STAT_FREADY (1<<1)
626 #define MDM_STAT_SYSSEC (1<<2)
627 #define MDM_STAT_SYSRES (1<<3)
628 #define MDM_STAT_FMEEN (1<<5)
629 #define MDM_STAT_BACKDOOREN (1<<6)
630 #define MDM_STAT_LPEN (1<<7)
631 #define MDM_STAT_VLPEN (1<<8)
632 #define MDM_STAT_LLSMODEXIT (1<<9)
633 #define MDM_STAT_VLLSXMODEXIT (1<<10)
634 #define MDM_STAT_CORE_HALTED (1<<16)
635 #define MDM_STAT_CORE_SLEEPDEEP (1<<17)
636 #define MDM_STAT_CORESLEEPING (1<<18)
638 #define MEM_CTRL_FMEIP (1<<0)
639 #define MEM_CTRL_DBG_DIS (1<<1)
640 #define MEM_CTRL_DBG_REQ (1<<2)
641 #define MEM_CTRL_SYS_RES_REQ (1<<3)
642 #define MEM_CTRL_CORE_HOLD_RES (1<<4)
643 #define MEM_CTRL_VLLSX_DBG_REQ (1<<5)
644 #define MEM_CTRL_VLLSX_DBG_ACK (1<<6)
645 #define MEM_CTRL_VLLSX_STAT_ACK (1<<7)
650 int dap_syssec_kinetis_mdmap(struct adiv5_dap *dap)
654 enum reset_types jtag_reset_config = jtag_get_reset_config();
656 dap_ap_select(dap, 1);
658 /* first check mdm-ap id register */
659 retval = dap_queue_ap_read(dap, MDM_REG_ID, &val);
660 if (retval != ERROR_OK)
664 if (val != 0x001C0000) {
665 LOG_DEBUG("id doesn't match %08" PRIX32 " != 0x001C0000", val);
666 dap_ap_select(dap, 0);
670 /* read and parse status register
671 * it's important that the device is out of
675 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
676 if (retval != ERROR_OK)
680 LOG_DEBUG("MDM_REG_STAT %08" PRIX32, val);
681 } while (!(val & MDM_STAT_FREADY));
683 if ((val & MDM_STAT_SYSSEC)) {
684 LOG_DEBUG("MDMAP: system is secured, masserase needed");
686 if (!(val & MDM_STAT_FMEEN))
687 LOG_DEBUG("MDMAP: masserase is disabled");
689 /* we need to assert reset */
690 if (jtag_reset_config & RESET_HAS_SRST) {
691 /* default to asserting srst */
692 adapter_assert_reset();
694 LOG_DEBUG("SRST not configured");
695 dap_ap_select(dap, 0);
700 retval = dap_queue_ap_write(dap, MDM_REG_CTRL, MEM_CTRL_FMEIP);
701 if (retval != ERROR_OK)
704 /* read status register and wait for ready */
705 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
706 if (retval != ERROR_OK)
709 LOG_DEBUG("MDM_REG_STAT %08" PRIX32, val);
716 retval = dap_queue_ap_write(dap, MDM_REG_CTRL, 0);
717 if (retval != ERROR_OK)
720 /* read status register */
721 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
722 if (retval != ERROR_OK)
725 LOG_DEBUG("MDM_REG_STAT %08" PRIX32, val);
726 /* read control register and wait for ready */
727 retval = dap_queue_ap_read(dap, MDM_REG_CTRL, &val);
728 if (retval != ERROR_OK)
731 LOG_DEBUG("MDM_REG_CTRL %08" PRIX32, val);
739 dap_ap_select(dap, 0);
745 struct dap_syssec_filter {
749 int (*dap_init)(struct adiv5_dap *dap);
753 static struct dap_syssec_filter dap_syssec_filter_data[] = {
754 { 0x4BA00477, dap_syssec_kinetis_mdmap }
760 int dap_syssec(struct adiv5_dap *dap)
763 struct jtag_tap *tap;
765 for (i = 0; i < sizeof(dap_syssec_filter_data); i++) {
766 tap = dap->jtag_info->tap;
768 while (tap != NULL) {
769 if (tap->hasidcode && (dap_syssec_filter_data[i].idcode == tap->idcode)) {
770 LOG_DEBUG("DAP: mdmap_init for idcode: %08" PRIx32, tap->idcode);
771 dap_syssec_filter_data[i].dap_init(dap);
780 /*--------------------------------------------------------------------------*/
783 /* FIXME don't import ... just initialize as
784 * part of DAP transport setup
786 extern const struct dap_ops jtag_dp_ops;
788 /*--------------------------------------------------------------------------*/
791 * Initialize a DAP. This sets up the power domains, prepares the DP
792 * for further use, and arranges to use AP #0 for all AP operations
793 * until dap_ap-select() changes that policy.
795 * @param dap The DAP being initialized.
797 * @todo Rename this. We also need an initialization scheme which account
798 * for SWD transports not just JTAG; that will need to address differences
799 * in layering. (JTAG is useful without any debug target; but not SWD.)
800 * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
802 int ahbap_debugport_init(struct adiv5_dap *dap)
810 /* JTAG-DP or SWJ-DP, in JTAG mode
811 * ... for SWD mode this is patched as part
815 dap->ops = &jtag_dp_ops;
817 /* Default MEM-AP setup.
819 * REVISIT AP #0 may be an inappropriate default for this.
820 * Should we probe, or take a hint from the caller?
821 * Presumably we can ignore the possibility of multiple APs.
823 dap->ap_current = !0;
824 dap_ap_select(dap, 0);
826 /* DP initialization */
828 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
829 if (retval != ERROR_OK)
832 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
833 if (retval != ERROR_OK)
836 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
837 if (retval != ERROR_OK)
840 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
841 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
842 if (retval != ERROR_OK)
845 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
846 if (retval != ERROR_OK)
848 retval = dap_run(dap);
849 if (retval != ERROR_OK)
852 /* Check that we have debug power domains activated */
853 while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10)) {
854 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
855 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
856 if (retval != ERROR_OK)
858 retval = dap_run(dap);
859 if (retval != ERROR_OK)
864 while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10)) {
865 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
866 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
867 if (retval != ERROR_OK)
869 retval = dap_run(dap);
870 if (retval != ERROR_OK)
875 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
876 if (retval != ERROR_OK)
878 /* With debug power on we can activate OVERRUN checking */
879 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
880 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
881 if (retval != ERROR_OK)
883 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
884 if (retval != ERROR_OK)
889 /* check that we support packed transfers */
892 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
893 if (retval != ERROR_OK)
896 retval = dap_queue_ap_read(dap, AP_REG_CSW, &csw);
897 if (retval != ERROR_OK)
900 retval = dap_run(dap);
901 if (retval != ERROR_OK)
904 if (csw & CSW_ADDRINC_PACKED)
905 dap->packed_transfers = true;
907 dap->packed_transfers = false;
909 LOG_DEBUG("MEM_AP Packed Transfers: %s",
910 dap->packed_transfers ? "enabled" : "disabled");
915 /* CID interpretation -- see ARM IHI 0029B section 3
916 * and ARM IHI 0031A table 13-3.
918 static const char *class_description[16] = {
919 "Reserved", "ROM table", "Reserved", "Reserved",
920 "Reserved", "Reserved", "Reserved", "Reserved",
921 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
922 "Reserved", "OptimoDE DESS",
923 "Generic IP component", "PrimeCell or System component"
926 static bool is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
928 return cid3 == 0xb1 && cid2 == 0x05
929 && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
933 * This function checks the ID for each access port to find the requested Access Port type
935 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, uint8_t *ap_num_out)
939 /* Maximum AP number is 255 since the SELECT register is 8 bits */
940 for (ap = 0; ap <= 255; ap++) {
942 /* read the IDR register of the Access Port */
944 dap_ap_select(dap, ap);
946 int retval = dap_queue_ap_read(dap, AP_REG_IDR, &id_val);
947 if (retval != ERROR_OK)
950 retval = dap_run(dap);
954 * 27-24 : JEDEC bank (0x4 for ARM)
955 * 23-17 : JEDEC code (0x3B for ARM)
958 * 7-0 : AP Identity (1=AHB-AP 2=APB-AP 0x10=JTAG-AP)
961 /* Reading register for a non-existant AP should not cause an error,
962 * but just to be sure, try to continue searching if an error does happen.
964 if ((retval == ERROR_OK) && /* Register read success */
965 ((id_val & 0x0FFF0000) == 0x04770000) && /* Jedec codes match */
966 ((id_val & 0xFF) == type_to_find)) { /* type matches*/
968 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
969 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
970 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
971 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
979 LOG_DEBUG("No %s found",
980 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
981 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
982 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
986 int dap_get_debugbase(struct adiv5_dap *dap, int ap,
987 uint32_t *out_dbgbase, uint32_t *out_apid)
991 uint32_t dbgbase, apid;
993 /* AP address is in bits 31:24 of DP_SELECT */
995 return ERROR_COMMAND_SYNTAX_ERROR;
997 ap_old = dap->ap_current;
998 dap_ap_select(dap, ap);
1000 retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase);
1001 if (retval != ERROR_OK)
1003 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1004 if (retval != ERROR_OK)
1006 retval = dap_run(dap);
1007 if (retval != ERROR_OK)
1010 /* Excavate the device ID code */
1011 struct jtag_tap *tap = dap->jtag_info->tap;
1012 while (tap != NULL) {
1015 tap = tap->next_tap;
1017 if (tap == NULL || !tap->hasidcode)
1020 dap_ap_select(dap, ap_old);
1022 /* The asignment happens only here to prevent modification of these
1023 * values before they are certain. */
1024 *out_dbgbase = dbgbase;
1030 int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
1031 uint32_t dbgbase, uint8_t type, uint32_t *addr)
1034 uint32_t romentry, entry_offset = 0, component_base, devtype;
1035 int retval = ERROR_FAIL;
1038 return ERROR_COMMAND_SYNTAX_ERROR;
1040 ap_old = dap->ap_current;
1041 dap_ap_select(dap, ap);
1044 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) |
1045 entry_offset, &romentry);
1046 if (retval != ERROR_OK)
1049 component_base = (dbgbase & 0xFFFFF000)
1050 + (romentry & 0xFFFFF000);
1052 if (romentry & 0x1) {
1053 retval = mem_ap_read_atomic_u32(dap,
1054 (component_base & 0xfffff000) | 0xfcc,
1056 if (retval != ERROR_OK)
1058 if ((devtype & 0xff) == type) {
1059 *addr = component_base;
1065 } while (romentry > 0);
1067 dap_ap_select(dap, ap_old);
1072 static int dap_info_command(struct command_context *cmd_ctx,
1073 struct adiv5_dap *dap, int ap)
1076 uint32_t dbgbase = 0, apid = 0; /* Silence gcc by initializing */
1077 int romtable_present = 0;
1081 retval = dap_get_debugbase(dap, ap, &dbgbase, &apid);
1082 if (retval != ERROR_OK)
1085 ap_old = dap->ap_current;
1086 dap_ap_select(dap, ap);
1088 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1089 mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1090 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1092 switch (apid&0x0F) {
1094 command_print(cmd_ctx, "\tType is JTAG-AP");
1097 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1100 command_print(cmd_ctx, "\tType is MEM-AP APB");
1103 command_print(cmd_ctx, "\tUnknown AP type");
1107 /* NOTE: a MEM-AP may have a single CoreSight component that's
1108 * not a ROM table ... or have no such components at all.
1111 command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32, dbgbase);
1113 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap);
1115 romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1116 if (romtable_present) {
1117 uint32_t cid0, cid1, cid2, cid3, memtype, romentry;
1118 uint16_t entry_offset;
1120 /* bit 16 of apid indicates a memory access port */
1122 command_print(cmd_ctx, "\tValid ROM table present");
1124 command_print(cmd_ctx, "\tROM table in legacy format");
1126 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1127 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1128 if (retval != ERROR_OK)
1130 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1131 if (retval != ERROR_OK)
1133 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1134 if (retval != ERROR_OK)
1136 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1137 if (retval != ERROR_OK)
1139 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1140 if (retval != ERROR_OK)
1142 retval = dap_run(dap);
1143 if (retval != ERROR_OK)
1146 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1147 command_print(cmd_ctx, "\tCID3 0x%2.2x"
1151 (unsigned) cid3, (unsigned)cid2,
1152 (unsigned) cid1, (unsigned) cid0);
1154 command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1156 command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1157 "Dedicated debug bus.");
1159 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1162 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1163 if (retval != ERROR_OK)
1165 command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "", entry_offset, romentry);
1166 if (romentry & 0x01) {
1167 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1168 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1169 uint32_t component_base;
1173 component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000);
1175 /* IDs are in last 4K section */
1176 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE0, &c_pid0);
1177 if (retval != ERROR_OK)
1180 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE4, &c_pid1);
1181 if (retval != ERROR_OK)
1184 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE8, &c_pid2);
1185 if (retval != ERROR_OK)
1188 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFEC, &c_pid3);
1189 if (retval != ERROR_OK)
1192 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFD0, &c_pid4);
1193 if (retval != ERROR_OK)
1197 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF0, &c_cid0);
1198 if (retval != ERROR_OK)
1201 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF4, &c_cid1);
1202 if (retval != ERROR_OK)
1205 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF8, &c_cid2);
1206 if (retval != ERROR_OK)
1209 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFFC, &c_cid3);
1210 if (retval != ERROR_OK)
1214 command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 ","
1215 "start address 0x%" PRIx32, component_base,
1216 /* component may take multiple 4K pages */
1217 component_base - 0x1000*(c_pid4 >> 4));
1218 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1219 (int) (c_cid1 >> 4) & 0xf,
1220 /* See ARM IHI 0029B Table 3-3 */
1221 class_description[(c_cid1 >> 4) & 0xf]);
1223 /* CoreSight component? */
1224 if (((c_cid1 >> 4) & 0x0f) == 9) {
1227 char *major = "Reserved", *subtype = "Reserved";
1229 retval = mem_ap_read_atomic_u32(dap,
1230 (component_base & 0xfffff000) | 0xfcc,
1232 if (retval != ERROR_OK)
1234 minor = (devtype >> 4) & 0x0f;
1235 switch (devtype & 0x0f) {
1237 major = "Miscellaneous";
1243 subtype = "Validation component";
1248 major = "Trace Sink";
1262 major = "Trace Link";
1268 subtype = "Funnel, router";
1274 subtype = "FIFO, buffer";
1279 major = "Trace Source";
1285 subtype = "Processor";
1291 subtype = "Engine/Coprocessor";
1299 major = "Debug Control";
1305 subtype = "Trigger Matrix";
1308 subtype = "Debug Auth";
1313 major = "Debug Logic";
1319 subtype = "Processor";
1325 subtype = "Engine/Coprocessor";
1330 command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1331 (unsigned) (devtype & 0xff),
1333 /* REVISIT also show 0xfc8 DevId */
1336 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1337 command_print(cmd_ctx,
1346 command_print(cmd_ctx,
1347 "\t\tPeripheral ID[4..0] = hex "
1348 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1349 (int) c_pid4, (int) c_pid3, (int) c_pid2,
1350 (int) c_pid1, (int) c_pid0);
1352 /* Part number interpretations are from Cortex
1353 * core specs, the CoreSight components TRM
1354 * (ARM DDI 0314H), CoreSight System Design
1355 * Guide (ARM DGI 0012D) and ETM specs; also
1356 * from chip observation (e.g. TI SDTI).
1358 part_num = (c_pid0 & 0xff);
1359 part_num |= (c_pid1 & 0x0f) << 8;
1362 type = "Cortex-M3 NVIC";
1363 full = "(Interrupt Controller)";
1366 type = "Cortex-M3 ITM";
1367 full = "(Instrumentation Trace Module)";
1370 type = "Cortex-M3 DWT";
1371 full = "(Data Watchpoint and Trace)";
1374 type = "Cortex-M3 FBP";
1375 full = "(Flash Patch and Breakpoint)";
1378 type = "Cortex-M4 SCS";
1379 full = "(System Control Space)";
1382 type = "CoreSight ETM11";
1383 full = "(Embedded Trace)";
1385 /* case 0x113: what? */
1386 case 0x120: /* from OMAP3 memmap */
1388 full = "(System Debug Trace Interface)";
1390 case 0x343: /* from OMAP3 memmap */
1395 type = "Coresight CTI";
1396 full = "(Cross Trigger)";
1399 type = "Coresight ETB";
1400 full = "(Trace Buffer)";
1403 type = "Coresight CSTF";
1404 full = "(Trace Funnel)";
1407 type = "CoreSight ETM9";
1408 full = "(Embedded Trace)";
1411 type = "Coresight TPIU";
1412 full = "(Trace Port Interface Unit)";
1415 type = "Cortex-A8 ETM";
1416 full = "(Embedded Trace)";
1419 type = "Cortex-A8 CTI";
1420 full = "(Cross Trigger)";
1423 type = "Cortex-M3 TPIU";
1424 full = "(Trace Port Interface Unit)";
1427 type = "Cortex-M3 ETM";
1428 full = "(Embedded Trace)";
1431 type = "Cortex-M4 ETM";
1432 full = "(Embedded Trace)";
1435 type = "Cortex-R4 ETM";
1436 full = "(Embedded Trace)";
1439 type = "Cortex-M4 TPUI";
1440 full = "(Trace Port Interface Unit)";
1443 type = "Cortex-A8 Debug";
1444 full = "(Debug Unit)";
1447 type = "-*- unrecognized -*-";
1451 command_print(cmd_ctx, "\t\tPart is %s %s",
1455 command_print(cmd_ctx, "\t\tComponent not present");
1457 command_print(cmd_ctx, "\t\tEnd of ROM table");
1460 } while (romentry > 0);
1462 command_print(cmd_ctx, "\tNo ROM table present");
1463 dap_ap_select(dap, ap_old);
1468 COMMAND_HANDLER(handle_dap_info_command)
1470 struct target *target = get_current_target(CMD_CTX);
1471 struct arm *arm = target_to_arm(target);
1472 struct adiv5_dap *dap = arm->dap;
1480 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1483 return ERROR_COMMAND_SYNTAX_ERROR;
1486 return dap_info_command(CMD_CTX, dap, apsel);
1489 COMMAND_HANDLER(dap_baseaddr_command)
1491 struct target *target = get_current_target(CMD_CTX);
1492 struct arm *arm = target_to_arm(target);
1493 struct adiv5_dap *dap = arm->dap;
1495 uint32_t apsel, baseaddr;
1503 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1504 /* AP address is in bits 31:24 of DP_SELECT */
1506 return ERROR_COMMAND_SYNTAX_ERROR;
1509 return ERROR_COMMAND_SYNTAX_ERROR;
1512 dap_ap_select(dap, apsel);
1514 /* NOTE: assumes we're talking to a MEM-AP, which
1515 * has a base address. There are other kinds of AP,
1516 * though they're not common for now. This should
1517 * use the ID register to verify it's a MEM-AP.
1519 retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
1520 if (retval != ERROR_OK)
1522 retval = dap_run(dap);
1523 if (retval != ERROR_OK)
1526 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1531 COMMAND_HANDLER(dap_memaccess_command)
1533 struct target *target = get_current_target(CMD_CTX);
1534 struct arm *arm = target_to_arm(target);
1535 struct adiv5_dap *dap = arm->dap;
1537 uint32_t memaccess_tck;
1541 memaccess_tck = dap->memaccess_tck;
1544 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1547 return ERROR_COMMAND_SYNTAX_ERROR;
1549 dap->memaccess_tck = memaccess_tck;
1551 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1552 dap->memaccess_tck);
1557 COMMAND_HANDLER(dap_apsel_command)
1559 struct target *target = get_current_target(CMD_CTX);
1560 struct arm *arm = target_to_arm(target);
1561 struct adiv5_dap *dap = arm->dap;
1563 uint32_t apsel, apid;
1571 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1572 /* AP address is in bits 31:24 of DP_SELECT */
1574 return ERROR_COMMAND_SYNTAX_ERROR;
1577 return ERROR_COMMAND_SYNTAX_ERROR;
1581 dap_ap_select(dap, apsel);
1583 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1584 if (retval != ERROR_OK)
1586 retval = dap_run(dap);
1587 if (retval != ERROR_OK)
1590 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1596 COMMAND_HANDLER(dap_apcsw_command)
1598 struct target *target = get_current_target(CMD_CTX);
1599 struct arm *arm = target_to_arm(target);
1600 struct adiv5_dap *dap = arm->dap;
1602 uint32_t apcsw = dap->apcsw[dap->apsel], sprot = 0;
1606 command_print(CMD_CTX, "apsel %" PRIi32 " selected, csw 0x%8.8" PRIx32,
1607 (dap->apsel), apcsw);
1610 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], sprot);
1611 /* AP address is in bits 31:24 of DP_SELECT */
1613 return ERROR_COMMAND_SYNTAX_ERROR;
1617 apcsw &= ~CSW_SPROT;
1620 return ERROR_COMMAND_SYNTAX_ERROR;
1622 dap->apcsw[dap->apsel] = apcsw;
1629 COMMAND_HANDLER(dap_apid_command)
1631 struct target *target = get_current_target(CMD_CTX);
1632 struct arm *arm = target_to_arm(target);
1633 struct adiv5_dap *dap = arm->dap;
1635 uint32_t apsel, apid;
1643 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1644 /* AP address is in bits 31:24 of DP_SELECT */
1646 return ERROR_COMMAND_SYNTAX_ERROR;
1649 return ERROR_COMMAND_SYNTAX_ERROR;
1652 dap_ap_select(dap, apsel);
1654 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1655 if (retval != ERROR_OK)
1657 retval = dap_run(dap);
1658 if (retval != ERROR_OK)
1661 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1666 static const struct command_registration dap_commands[] = {
1669 .handler = handle_dap_info_command,
1670 .mode = COMMAND_EXEC,
1671 .help = "display ROM table for MEM-AP "
1672 "(default currently selected AP)",
1673 .usage = "[ap_num]",
1677 .handler = dap_apsel_command,
1678 .mode = COMMAND_EXEC,
1679 .help = "Set the currently selected AP (default 0) "
1680 "and display the result",
1681 .usage = "[ap_num]",
1685 .handler = dap_apcsw_command,
1686 .mode = COMMAND_EXEC,
1687 .help = "Set csw access bit ",
1693 .handler = dap_apid_command,
1694 .mode = COMMAND_EXEC,
1695 .help = "return ID register from AP "
1696 "(default currently selected AP)",
1697 .usage = "[ap_num]",
1701 .handler = dap_baseaddr_command,
1702 .mode = COMMAND_EXEC,
1703 .help = "return debug base address from MEM-AP "
1704 "(default currently selected AP)",
1705 .usage = "[ap_num]",
1708 .name = "memaccess",
1709 .handler = dap_memaccess_command,
1710 .mode = COMMAND_EXEC,
1711 .help = "set/get number of extra tck for MEM-AP memory "
1712 "bus access [0-255]",
1713 .usage = "[cycles]",
1715 COMMAND_REGISTRATION_DONE
1718 const struct command_registration dap_command_handlers[] = {
1721 .mode = COMMAND_EXEC,
1722 .help = "DAP command group",
1724 .chain = dap_commands,
1726 COMMAND_REGISTRATION_DONE