1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * Copyright (C) 2009-2010 by David Brownell *
13 * This program is free software; you can redistribute it and/or modify *
14 * it under the terms of the GNU General Public License as published by *
15 * the Free Software Foundation; either version 2 of the License, or *
16 * (at your option) any later version. *
18 * This program is distributed in the hope that it will be useful, *
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
21 * GNU General Public License for more details. *
23 * You should have received a copy of the GNU General Public License *
24 * along with this program; if not, write to the *
25 * Free Software Foundation, Inc., *
26 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
27 ***************************************************************************/
31 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
32 * debugging architecture. Compared with previous versions, this includes
33 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
34 * transport, and focusses on memory mapped resources as defined by the
35 * CoreSight architecture.
37 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
38 * basic components: a Debug Port (DP) transporting messages to and from a
39 * debugger, and an Access Port (AP) accessing resources. Three types of DP
40 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
41 * One uses only SWD for communication, and is called SW-DP. The third can
42 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
43 * is used to access memory mapped resources and is called a MEM-AP. Also a
44 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
46 * This programming interface allows DAP pipelined operations through a
47 * transaction queue. This primarily affects AP operations (such as using
48 * a MEM-AP to access memory or registers). If the current transaction has
49 * not finished by the time the next one must begin, and the ORUNDETECT bit
50 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
51 * further AP operations will fail. There are two basic methods to avoid
52 * such overrun errors. One involves polling for status instead of using
53 * transaction piplining. The other involves adding delays to ensure the
54 * AP has enough time to complete one operation before starting the next
55 * one. (For JTAG these delays are controlled by memaccess_tck.)
59 * Relevant specifications from ARM include:
61 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
62 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
64 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
65 * Cortex-M3(tm) TRM, ARM DDI 0337G
72 #include "jtag/interface.h"
74 #include "arm_adi_v5.h"
75 #include <helper/time_support.h>
77 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
80 uint32_t tar_block_size(uint32_t address)
81 Return the largest block starting at address that does not cross a tar block size alignment boundary
83 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
85 return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
88 /***************************************************************************
90 * DP and MEM-AP register access through APACC and DPACC *
92 ***************************************************************************/
95 * Select one of the APs connected to the specified DAP. The
96 * selection is implicitly used with future AP transactions.
97 * This is a NOP if the specified AP is already selected.
100 * @param apsel Number of the AP to (implicitly) use with further
101 * transactions. This normally identifies a MEM-AP.
103 void dap_ap_select(struct adiv5_dap *dap, uint8_t ap)
105 uint32_t new_ap = (ap << 24) & 0xFF000000;
107 if (new_ap != dap->ap_current) {
108 dap->ap_current = new_ap;
109 /* Switching AP invalidates cached values.
110 * Values MUST BE UPDATED BEFORE AP ACCESS.
112 dap->ap_bank_value = -1;
113 dap->ap_csw_value = -1;
114 dap->ap_tar_value = -1;
119 * Queue transactions setting up transfer parameters for the
120 * currently selected MEM-AP.
122 * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
123 * initiate data reads or writes using memory or peripheral addresses.
124 * If the CSW is configured for it, the TAR may be automatically
125 * incremented after each transfer.
127 * @todo Rename to reflect it being specifically a MEM-AP function.
129 * @param dap The DAP connected to the MEM-AP.
130 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
131 * matches the cached value, the register is not changed.
132 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
133 * matches the cached address, the register is not changed.
135 * @return ERROR_OK if the transaction was properly queued, else a fault code.
137 int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
140 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT |
141 dap->apcsw[dap->ap_current >> 24];
143 if (csw != dap->ap_csw_value) {
144 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
145 retval = dap_queue_ap_write(dap, AP_REG_CSW, csw);
146 if (retval != ERROR_OK)
148 dap->ap_csw_value = csw;
150 if (tar != dap->ap_tar_value) {
151 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
152 retval = dap_queue_ap_write(dap, AP_REG_TAR, tar);
153 if (retval != ERROR_OK)
155 dap->ap_tar_value = tar;
157 /* Disable TAR cache when autoincrementing */
158 if (csw & CSW_ADDRINC_MASK)
159 dap->ap_tar_value = -1;
164 * Asynchronous (queued) read of a word from memory or a system register.
166 * @param dap The DAP connected to the MEM-AP performing the read.
167 * @param address Address of the 32-bit word to read; it must be
168 * readable by the currently selected MEM-AP.
169 * @param value points to where the word will be stored when the
170 * transaction queue is flushed (assuming no errors).
172 * @return ERROR_OK for success. Otherwise a fault code.
174 int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
179 /* Use banked addressing (REG_BDx) to avoid some link traffic
180 * (updating TAR) when reading several consecutive addresses.
182 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
183 address & 0xFFFFFFF0);
184 if (retval != ERROR_OK)
187 return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value);
191 * Synchronous read of a word from memory or a system register.
192 * As a side effect, this flushes any queued transactions.
194 * @param dap The DAP connected to the MEM-AP performing the read.
195 * @param address Address of the 32-bit word to read; it must be
196 * readable by the currently selected MEM-AP.
197 * @param value points to where the result will be stored.
199 * @return ERROR_OK for success; *value holds the result.
200 * Otherwise a fault code.
202 int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
207 retval = mem_ap_read_u32(dap, address, value);
208 if (retval != ERROR_OK)
215 * Asynchronous (queued) write of a word to memory or a system register.
217 * @param dap The DAP connected to the MEM-AP.
218 * @param address Address to be written; it must be writable by
219 * the currently selected MEM-AP.
220 * @param value Word that will be written to the address when transaction
221 * queue is flushed (assuming no errors).
223 * @return ERROR_OK for success. Otherwise a fault code.
225 int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
230 /* Use banked addressing (REG_BDx) to avoid some link traffic
231 * (updating TAR) when writing several consecutive addresses.
233 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
234 address & 0xFFFFFFF0);
235 if (retval != ERROR_OK)
238 return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC),
243 * Synchronous write of a word to memory or a system register.
244 * As a side effect, this flushes any queued transactions.
246 * @param dap The DAP connected to the MEM-AP.
247 * @param address Address to be written; it must be writable by
248 * the currently selected MEM-AP.
249 * @param value Word that will be written.
251 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
253 int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
256 int retval = mem_ap_write_u32(dap, address, value);
258 if (retval != ERROR_OK)
264 int mem_ap_write_buf_u32(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address, bool addr_incr)
266 int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
267 uint32_t adr = address;
268 uint32_t incr_flag = addr_incr ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
273 /* Adjust to write blocks within boundaries aligned to the TAR auto-increment size */
274 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
275 if (wcount < blocksize)
278 /* handle unaligned data at 4k boundary */
282 retval = dap_setup_accessport(dap, CSW_32BIT | incr_flag, address);
283 if (retval != ERROR_OK)
286 for (writecount = 0; writecount < blocksize; writecount++) {
287 uint32_t outvalue = 0;
288 outvalue |= (uint32_t)*buffer++ << 8 * (adr++ & 3);
289 outvalue |= (uint32_t)*buffer++ << 8 * (adr++ & 3);
290 outvalue |= (uint32_t)*buffer++ << 8 * (adr++ & 3);
291 outvalue |= (uint32_t)*buffer++ << 8 * (adr++ & 3);
293 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
294 if (retval != ERROR_OK)
298 retval = dap_run(dap);
299 if (retval == ERROR_OK) {
302 address += 4 * blocksize;
306 if (errorcount > 1) {
307 LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
315 static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap,
316 const uint8_t *buffer, int count, uint32_t address)
318 int retval = ERROR_OK;
319 int wcount, blocksize, writecount;
326 /* Adjust to write blocks within boundaries aligned to the TAR auto-increment size */
327 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
329 if (wcount < blocksize)
332 /* handle unaligned data at 4k boundary */
336 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
337 if (retval != ERROR_OK)
339 writecount = blocksize;
342 nbytes = MIN((writecount << 1), 4);
345 retval = mem_ap_write_buf_u16(dap, buffer,
347 if (retval != ERROR_OK) {
348 LOG_WARNING("Block write error address "
349 "0x%" PRIx32 ", count 0x%x",
359 uint32_t outvalue = 0;
360 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
361 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
362 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
363 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
365 retval = dap_queue_ap_write(dap,
366 AP_REG_DRW, outvalue);
367 if (retval != ERROR_OK)
370 retval = dap_run(dap);
371 if (retval != ERROR_OK) {
372 LOG_WARNING("Block write error address "
373 "0x%" PRIx32 ", count 0x%x",
379 writecount -= nbytes >> 1;
381 } while (writecount);
388 int mem_ap_write_buf_u16(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
390 int retval = ERROR_OK;
392 if (dap->packed_transfers && count >= 4)
393 return mem_ap_write_buf_packed_u16(dap, buffer, count, address);
396 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
397 if (retval != ERROR_OK)
400 uint32_t outvalue = 0;
401 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
402 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
404 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
405 if (retval != ERROR_OK)
408 retval = dap_run(dap);
409 if (retval != ERROR_OK)
418 static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap,
419 const uint8_t *buffer, int count, uint32_t address)
421 int retval = ERROR_OK;
422 int wcount, blocksize, writecount;
429 /* Adjust to write blocks within boundaries aligned to the TAR auto-increment size */
430 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
432 if (wcount < blocksize)
435 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
436 if (retval != ERROR_OK)
438 writecount = blocksize;
441 nbytes = MIN(writecount, 4);
444 retval = mem_ap_write_buf_u8(dap, buffer, nbytes, address);
445 if (retval != ERROR_OK) {
446 LOG_WARNING("Block write error address "
447 "0x%" PRIx32 ", count 0x%x",
457 uint32_t outvalue = 0;
458 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
459 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
460 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
461 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
463 retval = dap_queue_ap_write(dap,
464 AP_REG_DRW, outvalue);
465 if (retval != ERROR_OK)
468 retval = dap_run(dap);
469 if (retval != ERROR_OK) {
470 LOG_WARNING("Block write error address "
471 "0x%" PRIx32 ", count 0x%x",
477 writecount -= nbytes;
479 } while (writecount);
486 int mem_ap_write_buf_u8(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
488 int retval = ERROR_OK;
490 if (dap->packed_transfers && count >= 4)
491 return mem_ap_write_buf_packed_u8(dap, buffer, count, address);
494 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
495 if (retval != ERROR_OK)
497 uint32_t outvalue = (uint32_t)*buffer++ << 8 * (address++ & 0x3);
498 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
499 if (retval != ERROR_OK)
502 retval = dap_run(dap);
503 if (retval != ERROR_OK)
513 * Synchronously read a block of 32-bit words into a buffer
514 * @param dap The DAP connected to the MEM-AP.
515 * @param buffer where the words will be stored (in host byte order).
516 * @param count How many words to read.
517 * @param address Memory address from which to read words; all the
518 * @param addr_incr if true, increment the source address for each u32
519 * words must be readable by the currently selected MEM-AP.
521 int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer,
522 int count, uint32_t address, bool addr_incr)
524 int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
525 uint32_t adr = address;
526 uint8_t *pBuffer = buffer;
527 uint32_t incr_flag = CSW_ADDRINC_OFF;
533 /* Adjust to read blocks within boundaries aligned to the
534 * TAR autoincrement size (at least 2^10). Autoincrement
535 * mode avoids an extra per-word roundtrip to update TAR.
537 blocksize = max_tar_block_size(dap->tar_autoincr_block,
539 if (wcount < blocksize)
542 /* handle unaligned data at 4k boundary */
547 incr_flag = CSW_ADDRINC_SINGLE;
549 retval = dap_setup_accessport(dap, CSW_32BIT | incr_flag,
551 if (retval != ERROR_OK)
554 retval = dap_queue_ap_read_block(dap, AP_REG_DRW, blocksize, buffer);
556 retval = dap_run(dap);
557 if (retval != ERROR_OK) {
559 if (errorcount <= 1) {
563 LOG_WARNING("Block read error address 0x%" PRIx32, address);
566 wcount = wcount - blocksize;
568 address += 4 * blocksize;
569 buffer += 4 * blocksize;
572 /* if we have an unaligned access - reorder data */
574 for (readcount = 0; readcount < count; readcount++) {
577 memcpy(&data, pBuffer, sizeof(uint32_t));
579 for (i = 0; i < 4; i++) {
580 *((uint8_t *)pBuffer) =
581 (data >> 8 * (adr & 0x3));
591 static int mem_ap_read_buf_packed_u16(struct adiv5_dap *dap,
592 uint8_t *buffer, int count, uint32_t address)
595 int retval = ERROR_OK;
596 int wcount, blocksize, readcount, i;
603 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
604 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
605 if (wcount < blocksize)
608 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
609 if (retval != ERROR_OK)
612 /* handle unaligned data at 4k boundary */
615 readcount = blocksize;
618 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
619 if (retval != ERROR_OK)
621 retval = dap_run(dap);
622 if (retval != ERROR_OK) {
623 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
627 nbytes = MIN((readcount << 1), 4);
629 for (i = 0; i < nbytes; i++) {
630 *((uint8_t *)buffer) = (invalue >> 8 * (address & 0x3));
635 readcount -= (nbytes >> 1);
644 * Synchronously read a block of 16-bit halfwords into a buffer
645 * @param dap The DAP connected to the MEM-AP.
646 * @param buffer where the halfwords will be stored (in host byte order).
647 * @param count How many halfwords to read.
648 * @param address Memory address from which to read words; all the
649 * words must be readable by the currently selected MEM-AP.
651 int mem_ap_read_buf_u16(struct adiv5_dap *dap, uint8_t *buffer,
652 int count, uint32_t address)
655 int retval = ERROR_OK;
657 if (dap->packed_transfers && count >= 4)
658 return mem_ap_read_buf_packed_u16(dap, buffer, count, address);
661 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
662 if (retval != ERROR_OK)
664 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
665 if (retval != ERROR_OK)
668 retval = dap_run(dap);
669 if (retval != ERROR_OK)
673 for (i = 0; i < 2; i++) {
674 *((uint8_t *)buffer) = (invalue >> 8 * (address & 0x3));
679 uint16_t svalue = (invalue >> 8 * (address & 0x3));
680 memcpy(buffer, &svalue, sizeof(uint16_t));
690 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
691 * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
693 * The solution is to arrange for a large out/in scan in this loop and
694 * and convert data afterwards.
696 static int mem_ap_read_buf_packed_u8(struct adiv5_dap *dap,
697 uint8_t *buffer, int count, uint32_t address)
700 int retval = ERROR_OK;
701 int wcount, blocksize, readcount, i;
708 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
709 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
711 if (wcount < blocksize)
714 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
715 if (retval != ERROR_OK)
717 readcount = blocksize;
720 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
721 if (retval != ERROR_OK)
723 retval = dap_run(dap);
724 if (retval != ERROR_OK) {
725 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
729 nbytes = MIN(readcount, 4);
731 for (i = 0; i < nbytes; i++) {
732 *((uint8_t *)buffer) = (invalue >> 8 * (address & 0x3));
746 * Synchronously read a block of bytes into a buffer
747 * @param dap The DAP connected to the MEM-AP.
748 * @param buffer where the bytes will be stored.
749 * @param count How many bytes to read.
750 * @param address Memory address from which to read data; all the
751 * data must be readable by the currently selected MEM-AP.
753 int mem_ap_read_buf_u8(struct adiv5_dap *dap, uint8_t *buffer,
754 int count, uint32_t address)
757 int retval = ERROR_OK;
759 if (dap->packed_transfers && count >= 4)
760 return mem_ap_read_buf_packed_u8(dap, buffer, count, address);
763 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
764 if (retval != ERROR_OK)
766 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
767 if (retval != ERROR_OK)
769 retval = dap_run(dap);
770 if (retval != ERROR_OK)
773 *((uint8_t *)buffer) = (invalue >> 8 * (address & 0x3));
782 /*--------------------------------------------------------------------*/
783 /* Wrapping function with selection of AP */
784 /*--------------------------------------------------------------------*/
785 int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
786 uint32_t address, uint32_t *value)
788 dap_ap_select(swjdp, ap);
789 return mem_ap_read_u32(swjdp, address, value);
792 int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap,
793 uint32_t address, uint32_t value)
795 dap_ap_select(swjdp, ap);
796 return mem_ap_write_u32(swjdp, address, value);
799 int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
800 uint32_t address, uint32_t *value)
802 dap_ap_select(swjdp, ap);
803 return mem_ap_read_atomic_u32(swjdp, address, value);
806 int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
807 uint32_t address, uint32_t value)
809 dap_ap_select(swjdp, ap);
810 return mem_ap_write_atomic_u32(swjdp, address, value);
813 int mem_ap_sel_read_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
814 uint8_t *buffer, int count, uint32_t address)
816 dap_ap_select(swjdp, ap);
817 return mem_ap_read_buf_u8(swjdp, buffer, count, address);
820 int mem_ap_sel_read_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
821 uint8_t *buffer, int count, uint32_t address)
823 dap_ap_select(swjdp, ap);
824 return mem_ap_read_buf_u16(swjdp, buffer, count, address);
827 int mem_ap_sel_read_buf_u32_noincr(struct adiv5_dap *swjdp, uint8_t ap,
828 uint8_t *buffer, int count, uint32_t address)
830 dap_ap_select(swjdp, ap);
831 return mem_ap_read_buf_u32(swjdp, buffer, count, address, false);
834 int mem_ap_sel_read_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
835 uint8_t *buffer, int count, uint32_t address)
837 dap_ap_select(swjdp, ap);
838 return mem_ap_read_buf_u32(swjdp, buffer, count, address, true);
841 int mem_ap_sel_write_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
842 const uint8_t *buffer, int count, uint32_t address)
844 dap_ap_select(swjdp, ap);
845 return mem_ap_write_buf_u8(swjdp, buffer, count, address);
848 int mem_ap_sel_write_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
849 const uint8_t *buffer, int count, uint32_t address)
851 dap_ap_select(swjdp, ap);
852 return mem_ap_write_buf_u16(swjdp, buffer, count, address);
855 int mem_ap_sel_write_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
856 const uint8_t *buffer, int count, uint32_t address)
858 dap_ap_select(swjdp, ap);
859 return mem_ap_write_buf_u32(swjdp, buffer, count, address, true);
862 int mem_ap_sel_write_buf_u32_noincr(struct adiv5_dap *swjdp, uint8_t ap,
863 const uint8_t *buffer, int count, uint32_t address)
865 dap_ap_select(swjdp, ap);
866 return mem_ap_write_buf_u32(swjdp, buffer, count, address, false);
869 #define MDM_REG_STAT 0x00
870 #define MDM_REG_CTRL 0x04
871 #define MDM_REG_ID 0xfc
873 #define MDM_STAT_FMEACK (1<<0)
874 #define MDM_STAT_FREADY (1<<1)
875 #define MDM_STAT_SYSSEC (1<<2)
876 #define MDM_STAT_SYSRES (1<<3)
877 #define MDM_STAT_FMEEN (1<<5)
878 #define MDM_STAT_BACKDOOREN (1<<6)
879 #define MDM_STAT_LPEN (1<<7)
880 #define MDM_STAT_VLPEN (1<<8)
881 #define MDM_STAT_LLSMODEXIT (1<<9)
882 #define MDM_STAT_VLLSXMODEXIT (1<<10)
883 #define MDM_STAT_CORE_HALTED (1<<16)
884 #define MDM_STAT_CORE_SLEEPDEEP (1<<17)
885 #define MDM_STAT_CORESLEEPING (1<<18)
887 #define MEM_CTRL_FMEIP (1<<0)
888 #define MEM_CTRL_DBG_DIS (1<<1)
889 #define MEM_CTRL_DBG_REQ (1<<2)
890 #define MEM_CTRL_SYS_RES_REQ (1<<3)
891 #define MEM_CTRL_CORE_HOLD_RES (1<<4)
892 #define MEM_CTRL_VLLSX_DBG_REQ (1<<5)
893 #define MEM_CTRL_VLLSX_DBG_ACK (1<<6)
894 #define MEM_CTRL_VLLSX_STAT_ACK (1<<7)
899 int dap_syssec_kinetis_mdmap(struct adiv5_dap *dap)
903 enum reset_types jtag_reset_config = jtag_get_reset_config();
905 dap_ap_select(dap, 1);
907 /* first check mdm-ap id register */
908 retval = dap_queue_ap_read(dap, MDM_REG_ID, &val);
909 if (retval != ERROR_OK)
913 if (val != 0x001C0000) {
914 LOG_DEBUG("id doesn't match %08X != 0x001C0000", val);
915 dap_ap_select(dap, 0);
919 /* read and parse status register
920 * it's important that the device is out of
923 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
924 if (retval != ERROR_OK)
928 LOG_DEBUG("MDM_REG_STAT %08X", val);
930 if ((val & (MDM_STAT_SYSSEC|MDM_STAT_FREADY)) != (MDM_STAT_FREADY)) {
931 LOG_DEBUG("MDMAP: system is secured, masserase needed");
933 if (!(val & MDM_STAT_FMEEN))
934 LOG_DEBUG("MDMAP: masserase is disabled");
936 /* we need to assert reset */
937 if (jtag_reset_config & RESET_HAS_SRST) {
938 /* default to asserting srst */
939 adapter_assert_reset();
941 LOG_DEBUG("SRST not configured");
942 dap_ap_select(dap, 0);
947 retval = dap_queue_ap_write(dap, MDM_REG_CTRL, MEM_CTRL_FMEIP);
948 if (retval != ERROR_OK)
951 /* read status register and wait for ready */
952 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
953 if (retval != ERROR_OK)
956 LOG_DEBUG("MDM_REG_STAT %08X", val);
963 retval = dap_queue_ap_write(dap, MDM_REG_CTRL, 0);
964 if (retval != ERROR_OK)
967 /* read status register */
968 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
969 if (retval != ERROR_OK)
972 LOG_DEBUG("MDM_REG_STAT %08X", val);
973 /* read control register and wait for ready */
974 retval = dap_queue_ap_read(dap, MDM_REG_CTRL, &val);
975 if (retval != ERROR_OK)
978 LOG_DEBUG("MDM_REG_CTRL %08X", val);
986 dap_ap_select(dap, 0);
992 struct dap_syssec_filter {
996 int (*dap_init)(struct adiv5_dap *dap);
1000 static struct dap_syssec_filter dap_syssec_filter_data[] = {
1001 { 0x4BA00477, dap_syssec_kinetis_mdmap }
1007 int dap_syssec(struct adiv5_dap *dap)
1010 struct jtag_tap *tap;
1012 for (i = 0; i < sizeof(dap_syssec_filter_data); i++) {
1013 tap = dap->jtag_info->tap;
1015 while (tap != NULL) {
1016 if (tap->hasidcode && (dap_syssec_filter_data[i].idcode == tap->idcode)) {
1017 LOG_DEBUG("DAP: mdmap_init for idcode: %08x", tap->idcode);
1018 dap_syssec_filter_data[i].dap_init(dap);
1020 tap = tap->next_tap;
1027 /*--------------------------------------------------------------------------*/
1030 /* FIXME don't import ... just initialize as
1031 * part of DAP transport setup
1033 extern const struct dap_ops jtag_dp_ops;
1035 /*--------------------------------------------------------------------------*/
1038 * Initialize a DAP. This sets up the power domains, prepares the DP
1039 * for further use, and arranges to use AP #0 for all AP operations
1040 * until dap_ap-select() changes that policy.
1042 * @param dap The DAP being initialized.
1044 * @todo Rename this. We also need an initialization scheme which account
1045 * for SWD transports not just JTAG; that will need to address differences
1046 * in layering. (JTAG is useful without any debug target; but not SWD.)
1047 * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
1049 int ahbap_debugport_init(struct adiv5_dap *dap)
1057 /* JTAG-DP or SWJ-DP, in JTAG mode
1058 * ... for SWD mode this is patched as part
1059 * of link switchover
1062 dap->ops = &jtag_dp_ops;
1064 /* Default MEM-AP setup.
1066 * REVISIT AP #0 may be an inappropriate default for this.
1067 * Should we probe, or take a hint from the caller?
1068 * Presumably we can ignore the possibility of multiple APs.
1070 dap->ap_current = !0;
1071 dap_ap_select(dap, 0);
1073 /* DP initialization */
1075 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1076 if (retval != ERROR_OK)
1079 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
1080 if (retval != ERROR_OK)
1083 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1084 if (retval != ERROR_OK)
1087 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
1088 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
1089 if (retval != ERROR_OK)
1092 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
1093 if (retval != ERROR_OK)
1095 retval = dap_run(dap);
1096 if (retval != ERROR_OK)
1099 /* Check that we have debug power domains activated */
1100 while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10)) {
1101 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
1102 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
1103 if (retval != ERROR_OK)
1105 retval = dap_run(dap);
1106 if (retval != ERROR_OK)
1111 while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10)) {
1112 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
1113 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
1114 if (retval != ERROR_OK)
1116 retval = dap_run(dap);
1117 if (retval != ERROR_OK)
1122 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1123 if (retval != ERROR_OK)
1125 /* With debug power on we can activate OVERRUN checking */
1126 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
1127 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
1128 if (retval != ERROR_OK)
1130 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1131 if (retval != ERROR_OK)
1136 /* check that we support packed transfers */
1139 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
1140 if (retval != ERROR_OK)
1143 retval = dap_queue_ap_read(dap, AP_REG_CSW, &csw);
1144 if (retval != ERROR_OK)
1147 retval = dap_run(dap);
1148 if (retval != ERROR_OK)
1151 if (csw & CSW_ADDRINC_PACKED)
1152 dap->packed_transfers = true;
1154 dap->packed_transfers = false;
1156 LOG_DEBUG("MEM_AP Packed Transfers: %s",
1157 dap->packed_transfers ? "enabled" : "disabled");
1162 /* CID interpretation -- see ARM IHI 0029B section 3
1163 * and ARM IHI 0031A table 13-3.
1165 static const char *class_description[16] = {
1166 "Reserved", "ROM table", "Reserved", "Reserved",
1167 "Reserved", "Reserved", "Reserved", "Reserved",
1168 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1169 "Reserved", "OptimoDE DESS",
1170 "Generic IP component", "PrimeCell or System component"
1173 static bool is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
1175 return cid3 == 0xb1 && cid2 == 0x05
1176 && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1180 * This function checks the ID for each access port to find the requested Access Port type
1182 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, uint8_t *ap_num_out)
1186 /* Maximum AP number is 255 since the SELECT register is 8 bits */
1187 for (ap = 0; ap <= 255; ap++) {
1189 /* read the IDR register of the Access Port */
1190 uint32_t id_val = 0;
1191 dap_ap_select(dap, ap);
1193 int retval = dap_queue_ap_read(dap, AP_REG_IDR, &id_val);
1194 if (retval != ERROR_OK)
1197 retval = dap_run(dap);
1201 * 27-24 : JEDEC bank (0x4 for ARM)
1202 * 23-17 : JEDEC code (0x3B for ARM)
1205 * 7-0 : AP Identity (1=AHB-AP 2=APB-AP 0x10=JTAG-AP)
1208 /* Reading register for a non-existant AP should not cause an error,
1209 * but just to be sure, try to continue searching if an error does happen.
1211 if ((retval == ERROR_OK) && /* Register read success */
1212 ((id_val & 0x0FFF0000) == 0x04770000) && /* Jedec codes match */
1213 ((id_val & 0xFF) == type_to_find)) { /* type matches*/
1215 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08X)",
1216 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
1217 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
1218 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
1226 LOG_DEBUG("No %s found",
1227 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
1228 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
1229 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
1233 int dap_get_debugbase(struct adiv5_dap *dap, int ap,
1234 uint32_t *out_dbgbase, uint32_t *out_apid)
1238 uint32_t dbgbase, apid;
1240 /* AP address is in bits 31:24 of DP_SELECT */
1242 return ERROR_COMMAND_SYNTAX_ERROR;
1244 ap_old = dap->ap_current;
1245 dap_ap_select(dap, ap);
1247 retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase);
1248 if (retval != ERROR_OK)
1250 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1251 if (retval != ERROR_OK)
1253 retval = dap_run(dap);
1254 if (retval != ERROR_OK)
1257 /* Excavate the device ID code */
1258 struct jtag_tap *tap = dap->jtag_info->tap;
1259 while (tap != NULL) {
1262 tap = tap->next_tap;
1264 if (tap == NULL || !tap->hasidcode)
1267 dap_ap_select(dap, ap_old);
1269 /* The asignment happens only here to prevent modification of these
1270 * values before they are certain. */
1271 *out_dbgbase = dbgbase;
1277 int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
1278 uint32_t dbgbase, uint8_t type, uint32_t *addr)
1281 uint32_t romentry, entry_offset = 0, component_base, devtype;
1282 int retval = ERROR_FAIL;
1285 return ERROR_COMMAND_SYNTAX_ERROR;
1287 ap_old = dap->ap_current;
1288 dap_ap_select(dap, ap);
1291 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) |
1292 entry_offset, &romentry);
1293 if (retval != ERROR_OK)
1296 component_base = (dbgbase & 0xFFFFF000)
1297 + (romentry & 0xFFFFF000);
1299 if (romentry & 0x1) {
1300 retval = mem_ap_read_atomic_u32(dap,
1301 (component_base & 0xfffff000) | 0xfcc,
1303 if (retval != ERROR_OK)
1305 if ((devtype & 0xff) == type) {
1306 *addr = component_base;
1312 } while (romentry > 0);
1314 dap_ap_select(dap, ap_old);
1319 static int dap_info_command(struct command_context *cmd_ctx,
1320 struct adiv5_dap *dap, int ap)
1323 uint32_t dbgbase = 0, apid = 0; /* Silence gcc by initializing */
1324 int romtable_present = 0;
1328 retval = dap_get_debugbase(dap, ap, &dbgbase, &apid);
1329 if (retval != ERROR_OK)
1332 ap_old = dap->ap_current;
1333 dap_ap_select(dap, ap);
1335 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1336 mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1337 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1339 switch (apid&0x0F) {
1341 command_print(cmd_ctx, "\tType is JTAG-AP");
1344 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1347 command_print(cmd_ctx, "\tType is MEM-AP APB");
1350 command_print(cmd_ctx, "\tUnknown AP type");
1354 /* NOTE: a MEM-AP may have a single CoreSight component that's
1355 * not a ROM table ... or have no such components at all.
1358 command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32, dbgbase);
1360 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap);
1362 romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1363 if (romtable_present) {
1364 uint32_t cid0, cid1, cid2, cid3, memtype, romentry;
1365 uint16_t entry_offset;
1367 /* bit 16 of apid indicates a memory access port */
1369 command_print(cmd_ctx, "\tValid ROM table present");
1371 command_print(cmd_ctx, "\tROM table in legacy format");
1373 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1374 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1375 if (retval != ERROR_OK)
1377 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1378 if (retval != ERROR_OK)
1380 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1381 if (retval != ERROR_OK)
1383 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1384 if (retval != ERROR_OK)
1386 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1387 if (retval != ERROR_OK)
1389 retval = dap_run(dap);
1390 if (retval != ERROR_OK)
1393 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1394 command_print(cmd_ctx, "\tCID3 0x%2.2x"
1398 (unsigned) cid3, (unsigned)cid2,
1399 (unsigned) cid1, (unsigned) cid0);
1401 command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1403 command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1404 "Dedicated debug bus.");
1406 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1409 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1410 if (retval != ERROR_OK)
1412 command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "", entry_offset, romentry);
1413 if (romentry & 0x01) {
1414 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1415 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1416 uint32_t component_base;
1420 component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000);
1422 /* IDs are in last 4K section */
1423 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE0, &c_pid0);
1424 if (retval != ERROR_OK)
1427 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE4, &c_pid1);
1428 if (retval != ERROR_OK)
1431 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE8, &c_pid2);
1432 if (retval != ERROR_OK)
1435 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFEC, &c_pid3);
1436 if (retval != ERROR_OK)
1439 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFD0, &c_pid4);
1440 if (retval != ERROR_OK)
1444 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF0, &c_cid0);
1445 if (retval != ERROR_OK)
1448 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF4, &c_cid1);
1449 if (retval != ERROR_OK)
1452 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF8, &c_cid2);
1453 if (retval != ERROR_OK)
1456 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFFC, &c_cid3);
1457 if (retval != ERROR_OK)
1461 command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 ","
1462 "start address 0x%" PRIx32, component_base,
1463 /* component may take multiple 4K pages */
1464 component_base - 0x1000*(c_pid4 >> 4));
1465 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1466 (int) (c_cid1 >> 4) & 0xf,
1467 /* See ARM IHI 0029B Table 3-3 */
1468 class_description[(c_cid1 >> 4) & 0xf]);
1470 /* CoreSight component? */
1471 if (((c_cid1 >> 4) & 0x0f) == 9) {
1474 char *major = "Reserved", *subtype = "Reserved";
1476 retval = mem_ap_read_atomic_u32(dap,
1477 (component_base & 0xfffff000) | 0xfcc,
1479 if (retval != ERROR_OK)
1481 minor = (devtype >> 4) & 0x0f;
1482 switch (devtype & 0x0f) {
1484 major = "Miscellaneous";
1490 subtype = "Validation component";
1495 major = "Trace Sink";
1509 major = "Trace Link";
1515 subtype = "Funnel, router";
1521 subtype = "FIFO, buffer";
1526 major = "Trace Source";
1532 subtype = "Processor";
1538 subtype = "Engine/Coprocessor";
1546 major = "Debug Control";
1552 subtype = "Trigger Matrix";
1555 subtype = "Debug Auth";
1560 major = "Debug Logic";
1566 subtype = "Processor";
1572 subtype = "Engine/Coprocessor";
1577 command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1578 (unsigned) (devtype & 0xff),
1580 /* REVISIT also show 0xfc8 DevId */
1583 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1584 command_print(cmd_ctx,
1593 command_print(cmd_ctx,
1594 "\t\tPeripheral ID[4..0] = hex "
1595 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1596 (int) c_pid4, (int) c_pid3, (int) c_pid2,
1597 (int) c_pid1, (int) c_pid0);
1599 /* Part number interpretations are from Cortex
1600 * core specs, the CoreSight components TRM
1601 * (ARM DDI 0314H), CoreSight System Design
1602 * Guide (ARM DGI 0012D) and ETM specs; also
1603 * from chip observation (e.g. TI SDTI).
1605 part_num = (c_pid0 & 0xff);
1606 part_num |= (c_pid1 & 0x0f) << 8;
1609 type = "Cortex-M3 NVIC";
1610 full = "(Interrupt Controller)";
1613 type = "Cortex-M3 ITM";
1614 full = "(Instrumentation Trace Module)";
1617 type = "Cortex-M3 DWT";
1618 full = "(Data Watchpoint and Trace)";
1621 type = "Cortex-M3 FBP";
1622 full = "(Flash Patch and Breakpoint)";
1625 type = "Cortex-M4 SCS";
1626 full = "(System Control Space)";
1629 type = "CoreSight ETM11";
1630 full = "(Embedded Trace)";
1632 /* case 0x113: what? */
1633 case 0x120: /* from OMAP3 memmap */
1635 full = "(System Debug Trace Interface)";
1637 case 0x343: /* from OMAP3 memmap */
1642 type = "Coresight CTI";
1643 full = "(Cross Trigger)";
1646 type = "Coresight ETB";
1647 full = "(Trace Buffer)";
1650 type = "Coresight CSTF";
1651 full = "(Trace Funnel)";
1654 type = "CoreSight ETM9";
1655 full = "(Embedded Trace)";
1658 type = "Coresight TPIU";
1659 full = "(Trace Port Interface Unit)";
1662 type = "Cortex-A8 ETM";
1663 full = "(Embedded Trace)";
1666 type = "Cortex-A8 CTI";
1667 full = "(Cross Trigger)";
1670 type = "Cortex-M3 TPIU";
1671 full = "(Trace Port Interface Unit)";
1674 type = "Cortex-M3 ETM";
1675 full = "(Embedded Trace)";
1678 type = "Cortex-M4 ETM";
1679 full = "(Embedded Trace)";
1682 type = "Cortex-R4 ETM";
1683 full = "(Embedded Trace)";
1686 type = "Cortex-M4 TPUI";
1687 full = "(Trace Port Interface Unit)";
1690 type = "Cortex-A8 Debug";
1691 full = "(Debug Unit)";
1694 type = "-*- unrecognized -*-";
1698 command_print(cmd_ctx, "\t\tPart is %s %s",
1702 command_print(cmd_ctx, "\t\tComponent not present");
1704 command_print(cmd_ctx, "\t\tEnd of ROM table");
1707 } while (romentry > 0);
1709 command_print(cmd_ctx, "\tNo ROM table present");
1710 dap_ap_select(dap, ap_old);
1715 COMMAND_HANDLER(handle_dap_info_command)
1717 struct target *target = get_current_target(CMD_CTX);
1718 struct arm *arm = target_to_arm(target);
1719 struct adiv5_dap *dap = arm->dap;
1727 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1730 return ERROR_COMMAND_SYNTAX_ERROR;
1733 return dap_info_command(CMD_CTX, dap, apsel);
1736 COMMAND_HANDLER(dap_baseaddr_command)
1738 struct target *target = get_current_target(CMD_CTX);
1739 struct arm *arm = target_to_arm(target);
1740 struct adiv5_dap *dap = arm->dap;
1742 uint32_t apsel, baseaddr;
1750 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1751 /* AP address is in bits 31:24 of DP_SELECT */
1753 return ERROR_COMMAND_SYNTAX_ERROR;
1756 return ERROR_COMMAND_SYNTAX_ERROR;
1759 dap_ap_select(dap, apsel);
1761 /* NOTE: assumes we're talking to a MEM-AP, which
1762 * has a base address. There are other kinds of AP,
1763 * though they're not common for now. This should
1764 * use the ID register to verify it's a MEM-AP.
1766 retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
1767 if (retval != ERROR_OK)
1769 retval = dap_run(dap);
1770 if (retval != ERROR_OK)
1773 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1778 COMMAND_HANDLER(dap_memaccess_command)
1780 struct target *target = get_current_target(CMD_CTX);
1781 struct arm *arm = target_to_arm(target);
1782 struct adiv5_dap *dap = arm->dap;
1784 uint32_t memaccess_tck;
1788 memaccess_tck = dap->memaccess_tck;
1791 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1794 return ERROR_COMMAND_SYNTAX_ERROR;
1796 dap->memaccess_tck = memaccess_tck;
1798 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1799 dap->memaccess_tck);
1804 COMMAND_HANDLER(dap_apsel_command)
1806 struct target *target = get_current_target(CMD_CTX);
1807 struct arm *arm = target_to_arm(target);
1808 struct adiv5_dap *dap = arm->dap;
1810 uint32_t apsel, apid;
1818 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1819 /* AP address is in bits 31:24 of DP_SELECT */
1821 return ERROR_COMMAND_SYNTAX_ERROR;
1824 return ERROR_COMMAND_SYNTAX_ERROR;
1828 dap_ap_select(dap, apsel);
1830 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1831 if (retval != ERROR_OK)
1833 retval = dap_run(dap);
1834 if (retval != ERROR_OK)
1837 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1843 COMMAND_HANDLER(dap_apcsw_command)
1845 struct target *target = get_current_target(CMD_CTX);
1846 struct arm *arm = target_to_arm(target);
1847 struct adiv5_dap *dap = arm->dap;
1849 uint32_t apcsw = dap->apcsw[dap->apsel], sprot = 0;
1853 command_print(CMD_CTX, "apsel %" PRIi32 " selected, csw 0x%8.8" PRIx32,
1854 (dap->apsel), apcsw);
1857 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], sprot);
1858 /* AP address is in bits 31:24 of DP_SELECT */
1860 return ERROR_COMMAND_SYNTAX_ERROR;
1864 apcsw &= ~CSW_SPROT;
1867 return ERROR_COMMAND_SYNTAX_ERROR;
1869 dap->apcsw[dap->apsel] = apcsw;
1876 COMMAND_HANDLER(dap_apid_command)
1878 struct target *target = get_current_target(CMD_CTX);
1879 struct arm *arm = target_to_arm(target);
1880 struct adiv5_dap *dap = arm->dap;
1882 uint32_t apsel, apid;
1890 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1891 /* AP address is in bits 31:24 of DP_SELECT */
1893 return ERROR_COMMAND_SYNTAX_ERROR;
1896 return ERROR_COMMAND_SYNTAX_ERROR;
1899 dap_ap_select(dap, apsel);
1901 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1902 if (retval != ERROR_OK)
1904 retval = dap_run(dap);
1905 if (retval != ERROR_OK)
1908 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1913 static const struct command_registration dap_commands[] = {
1916 .handler = handle_dap_info_command,
1917 .mode = COMMAND_EXEC,
1918 .help = "display ROM table for MEM-AP "
1919 "(default currently selected AP)",
1920 .usage = "[ap_num]",
1924 .handler = dap_apsel_command,
1925 .mode = COMMAND_EXEC,
1926 .help = "Set the currently selected AP (default 0) "
1927 "and display the result",
1928 .usage = "[ap_num]",
1932 .handler = dap_apcsw_command,
1933 .mode = COMMAND_EXEC,
1934 .help = "Set csw access bit ",
1940 .handler = dap_apid_command,
1941 .mode = COMMAND_EXEC,
1942 .help = "return ID register from AP "
1943 "(default currently selected AP)",
1944 .usage = "[ap_num]",
1948 .handler = dap_baseaddr_command,
1949 .mode = COMMAND_EXEC,
1950 .help = "return debug base address from MEM-AP "
1951 "(default currently selected AP)",
1952 .usage = "[ap_num]",
1955 .name = "memaccess",
1956 .handler = dap_memaccess_command,
1957 .mode = COMMAND_EXEC,
1958 .help = "set/get number of extra tck for MEM-AP memory "
1959 "bus access [0-255]",
1960 .usage = "[cycles]",
1962 COMMAND_REGISTRATION_DONE
1965 const struct command_registration dap_command_handlers[] = {
1968 .mode = COMMAND_EXEC,
1969 .help = "DAP command group",
1971 .chain = dap_commands,
1973 COMMAND_REGISTRATION_DONE