1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * Copyright (C) 2009-2010 by David Brownell *
13 * This program is free software; you can redistribute it and/or modify *
14 * it under the terms of the GNU General Public License as published by *
15 * the Free Software Foundation; either version 2 of the License, or *
16 * (at your option) any later version. *
18 * This program is distributed in the hope that it will be useful, *
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
21 * GNU General Public License for more details. *
23 * You should have received a copy of the GNU General Public License *
24 * along with this program; if not, write to the *
25 * Free Software Foundation, Inc., *
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 ***************************************************************************/
31 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
32 * debugging architecture. Compared with previous versions, this includes
33 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
34 * transport, and focusses on memory mapped resources as defined by the
35 * CoreSight architecture.
37 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
38 * basic components: a Debug Port (DP) transporting messages to and from a
39 * debugger, and an Access Port (AP) accessing resources. Three types of DP
40 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
41 * One uses only SWD for communication, and is called SW-DP. The third can
42 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
43 * is used to access memory mapped resources and is called a MEM-AP. Also a
44 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
46 * This programming interface allows DAP pipelined operations through a
47 * transaction queue. This primarily affects AP operations (such as using
48 * a MEM-AP to access memory or registers). If the current transaction has
49 * not finished by the time the next one must begin, and the ORUNDETECT bit
50 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
51 * further AP operations will fail. There are two basic methods to avoid
52 * such overrun errors. One involves polling for status instead of using
53 * transaction piplining. The other involves adding delays to ensure the
54 * AP has enough time to complete one operation before starting the next
55 * one. (For JTAG these delays are controlled by memaccess_tck.)
59 * Relevant specifications from ARM include:
61 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
62 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
64 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
65 * Cortex-M3(tm) TRM, ARM DDI 0337G
73 #include "arm_adi_v5.h"
74 #include <helper/time_support.h>
77 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
80 uint32_t tar_block_size(uint32_t address)
81 Return the largest block starting at address that does not cross a tar block size alignment boundary
83 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
85 return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
88 /***************************************************************************
90 * DP and MEM-AP register access through APACC and DPACC *
92 ***************************************************************************/
95 * Select one of the APs connected to the specified DAP. The
96 * selection is implicitly used with future AP transactions.
97 * This is a NOP if the specified AP is already selected.
100 * @param apsel Number of the AP to (implicitly) use with further
101 * transactions. This normally identifies a MEM-AP.
103 void dap_ap_select(struct adiv5_dap *dap,uint8_t apsel)
105 uint32_t select_apsel = (apsel << 24) & 0xFF000000;
107 if (select_apsel != dap->apsel)
109 dap->apsel = select_apsel;
110 /* Switching AP invalidates cached values.
111 * Values MUST BE UPDATED BEFORE AP ACCESS.
113 dap->ap_bank_value = -1;
114 dap->ap_csw_value = -1;
115 dap->ap_tar_value = -1;
120 * Queue transactions setting up transfer parameters for the
121 * currently selected MEM-AP.
123 * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
124 * initiate data reads or writes using memory or peripheral addresses.
125 * If the CSW is configured for it, the TAR may be automatically
126 * incremented after each transfer.
128 * @todo Rename to reflect it being specifically a MEM-AP function.
130 * @param dap The DAP connected to the MEM-AP.
131 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
132 * matches the cached value, the register is not changed.
133 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
134 * matches the cached address, the register is not changed.
136 * @return ERROR_OK if the transaction was properly queued, else a fault code.
138 int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
142 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
143 if (csw != dap->ap_csw_value)
145 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
146 retval = dap_queue_ap_write(dap, AP_REG_CSW, csw);
147 if (retval != ERROR_OK)
149 dap->ap_csw_value = csw;
151 if (tar != dap->ap_tar_value)
153 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
154 retval = dap_queue_ap_write(dap, AP_REG_TAR, tar);
155 if (retval != ERROR_OK)
157 dap->ap_tar_value = tar;
159 /* Disable TAR cache when autoincrementing */
160 if (csw & CSW_ADDRINC_MASK)
161 dap->ap_tar_value = -1;
166 * Asynchronous (queued) read of a word from memory or a system register.
168 * @param dap The DAP connected to the MEM-AP performing the read.
169 * @param address Address of the 32-bit word to read; it must be
170 * readable by the currently selected MEM-AP.
171 * @param value points to where the word will be stored when the
172 * transaction queue is flushed (assuming no errors).
174 * @return ERROR_OK for success. Otherwise a fault code.
176 int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
181 /* Use banked addressing (REG_BDx) to avoid some link traffic
182 * (updating TAR) when reading several consecutive addresses.
184 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
185 address & 0xFFFFFFF0);
186 if (retval != ERROR_OK)
189 return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value);
193 * Synchronous read of a word from memory or a system register.
194 * As a side effect, this flushes any queued transactions.
196 * @param dap The DAP connected to the MEM-AP performing the read.
197 * @param address Address of the 32-bit word to read; it must be
198 * readable by the currently selected MEM-AP.
199 * @param value points to where the result will be stored.
201 * @return ERROR_OK for success; *value holds the result.
202 * Otherwise a fault code.
204 int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
209 retval = mem_ap_read_u32(dap, address, value);
210 if (retval != ERROR_OK)
217 * Asynchronous (queued) write of a word to memory or a system register.
219 * @param dap The DAP connected to the MEM-AP.
220 * @param address Address to be written; it must be writable by
221 * the currently selected MEM-AP.
222 * @param value Word that will be written to the address when transaction
223 * queue is flushed (assuming no errors).
225 * @return ERROR_OK for success. Otherwise a fault code.
227 int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
232 /* Use banked addressing (REG_BDx) to avoid some link traffic
233 * (updating TAR) when writing several consecutive addresses.
235 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
236 address & 0xFFFFFFF0);
237 if (retval != ERROR_OK)
240 return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC),
245 * Synchronous write of a word to memory or a system register.
246 * As a side effect, this flushes any queued transactions.
248 * @param dap The DAP connected to the MEM-AP.
249 * @param address Address to be written; it must be writable by
250 * the currently selected MEM-AP.
251 * @param value Word that will be written.
253 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
255 int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
258 int retval = mem_ap_write_u32(dap, address, value);
260 if (retval != ERROR_OK)
266 /*****************************************************************************
268 * mem_ap_write_buf(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address) *
270 * Write a buffer in target order (little endian) *
272 *****************************************************************************/
273 int mem_ap_write_buf_u32(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
275 int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
276 uint32_t adr = address;
277 uint8_t* pBuffer = buffer;
282 /* if we have an unaligned access - reorder data */
285 for (writecount = 0; writecount < count; writecount++)
289 memcpy(&outvalue, pBuffer, sizeof(uint32_t));
291 for (i = 0; i < 4; i++)
293 *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
297 pBuffer += sizeof(uint32_t);
303 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
304 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
305 if (wcount < blocksize)
308 /* handle unaligned data at 4k boundary */
312 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
313 if (retval != ERROR_OK)
316 for (writecount = 0; writecount < blocksize; writecount++)
318 retval = dap_queue_ap_write(dap, AP_REG_DRW,
319 *(uint32_t *) (buffer + 4 * writecount));
320 if (retval != ERROR_OK)
324 if (dap_run(dap) == ERROR_OK)
326 wcount = wcount - blocksize;
327 address = address + 4 * blocksize;
328 buffer = buffer + 4 * blocksize;
337 LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
338 /* REVISIT return the *actual* fault code */
339 return ERROR_JTAG_DEVICE_ERROR;
346 static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap,
347 uint8_t *buffer, int count, uint32_t address)
349 int retval = ERROR_OK;
350 int wcount, blocksize, writecount, i;
358 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
359 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
361 if (wcount < blocksize)
364 /* handle unaligned data at 4k boundary */
368 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
369 if (retval != ERROR_OK)
371 writecount = blocksize;
375 nbytes = MIN((writecount << 1), 4);
379 retval = mem_ap_write_buf_u16(dap, buffer,
381 if (retval != ERROR_OK)
383 LOG_WARNING("Block write error address "
384 "0x%" PRIx32 ", count 0x%x",
389 address += nbytes >> 1;
394 memcpy(&outvalue, buffer, sizeof(uint32_t));
396 for (i = 0; i < nbytes; i++)
398 *((uint8_t*)buffer + (address & 0x3)) = outvalue;
403 memcpy(&outvalue, buffer, sizeof(uint32_t));
404 retval = dap_queue_ap_write(dap,
405 AP_REG_DRW, outvalue);
406 if (retval != ERROR_OK)
409 if (dap_run(dap) != ERROR_OK)
411 LOG_WARNING("Block write error address "
412 "0x%" PRIx32 ", count 0x%x",
414 /* REVISIT return *actual* fault code */
415 return ERROR_JTAG_DEVICE_ERROR;
419 buffer += nbytes >> 1;
420 writecount -= nbytes >> 1;
422 } while (writecount);
429 int mem_ap_write_buf_u16(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
431 int retval = ERROR_OK;
434 return mem_ap_write_buf_packed_u16(dap, buffer, count, address);
438 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
439 if (retval != ERROR_OK)
442 memcpy(&svalue, buffer, sizeof(uint16_t));
443 uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
444 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
445 if (retval != ERROR_OK)
448 retval = dap_run(dap);
449 if (retval != ERROR_OK)
460 static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap,
461 uint8_t *buffer, int count, uint32_t address)
463 int retval = ERROR_OK;
464 int wcount, blocksize, writecount, i;
472 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
473 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
475 if (wcount < blocksize)
478 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
479 if (retval != ERROR_OK)
481 writecount = blocksize;
485 nbytes = MIN(writecount, 4);
489 retval = mem_ap_write_buf_u8(dap, buffer, nbytes, address);
490 if (retval != ERROR_OK)
492 LOG_WARNING("Block write error address "
493 "0x%" PRIx32 ", count 0x%x",
503 memcpy(&outvalue, buffer, sizeof(uint32_t));
505 for (i = 0; i < nbytes; i++)
507 *((uint8_t*)buffer + (address & 0x3)) = outvalue;
512 memcpy(&outvalue, buffer, sizeof(uint32_t));
513 retval = dap_queue_ap_write(dap,
514 AP_REG_DRW, outvalue);
515 if (retval != ERROR_OK)
518 if (dap_run(dap) != ERROR_OK)
520 LOG_WARNING("Block write error address "
521 "0x%" PRIx32 ", count 0x%x",
523 /* REVISIT return *actual* fault code */
524 return ERROR_JTAG_DEVICE_ERROR;
529 writecount -= nbytes;
531 } while (writecount);
538 int mem_ap_write_buf_u8(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
540 int retval = ERROR_OK;
543 return mem_ap_write_buf_packed_u8(dap, buffer, count, address);
547 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
548 if (retval != ERROR_OK)
550 uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
551 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
552 if (retval != ERROR_OK)
555 retval = dap_run(dap);
556 if (retval != ERROR_OK)
567 /* FIXME don't import ... this is a temporary workaround for the
568 * mem_ap_read_buf_u32() mess, until it's no longer JTAG-specific.
570 extern int adi_jtag_dp_scan(struct adiv5_dap *dap,
571 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
572 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack);
575 * Synchronously read a block of 32-bit words into a buffer
576 * @param dap The DAP connected to the MEM-AP.
577 * @param buffer where the words will be stored (in host byte order).
578 * @param count How many words to read.
579 * @param address Memory address from which to read words; all the
580 * words must be readable by the currently selected MEM-AP.
582 int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer,
583 int count, uint32_t address)
585 int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
586 uint32_t adr = address;
587 uint8_t* pBuffer = buffer;
594 /* Adjust to read blocks within boundaries aligned to the
595 * TAR autoincrement size (at least 2^10). Autoincrement
596 * mode avoids an extra per-word roundtrip to update TAR.
598 blocksize = max_tar_block_size(dap->tar_autoincr_block,
600 if (wcount < blocksize)
603 /* handle unaligned data at 4k boundary */
607 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE,
609 if (retval != ERROR_OK)
612 /* FIXME remove these three calls to adi_jtag_dp_scan(),
613 * so this routine becomes transport-neutral. Be careful
614 * not to cause performance problems with JTAG; would it
615 * suffice to loop over dap_queue_ap_read(), or would that
616 * be slower when JTAG is the chosen transport?
619 /* Scan out first read */
620 retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
621 DPAP_READ, 0, NULL, NULL);
622 if (retval != ERROR_OK)
624 for (readcount = 0; readcount < blocksize - 1; readcount++)
626 /* Scan out next read; scan in posted value for the
627 * previous one. Assumes read is acked "OK/FAULT",
628 * and CTRL_STAT says that meant "OK".
630 retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
631 DPAP_READ, 0, buffer + 4 * readcount,
633 if (retval != ERROR_OK)
637 /* Scan in last posted value; RDBUFF has no other effect,
638 * assuming ack is OK/FAULT and CTRL_STAT says "OK".
640 retval = adi_jtag_dp_scan(dap, JTAG_DP_DPACC, DP_RDBUFF,
641 DPAP_READ, 0, buffer + 4 * readcount,
643 if (retval != ERROR_OK)
646 retval = dap_run(dap);
647 if (retval != ERROR_OK)
655 LOG_WARNING("Block read error address 0x%" PRIx32, address);
658 wcount = wcount - blocksize;
659 address += 4 * blocksize;
660 buffer += 4 * blocksize;
663 /* if we have an unaligned access - reorder data */
666 for (readcount = 0; readcount < count; readcount++)
670 memcpy(&data, pBuffer, sizeof(uint32_t));
672 for (i = 0; i < 4; i++)
674 *((uint8_t*)pBuffer) =
675 (data >> 8 * (adr & 0x3));
685 static int mem_ap_read_buf_packed_u16(struct adiv5_dap *dap,
686 uint8_t *buffer, int count, uint32_t address)
689 int retval = ERROR_OK;
690 int wcount, blocksize, readcount, i;
698 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
699 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
700 if (wcount < blocksize)
703 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
704 if (retval != ERROR_OK)
707 /* handle unaligned data at 4k boundary */
710 readcount = blocksize;
714 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
715 if (dap_run(dap) != ERROR_OK)
717 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
718 /* REVISIT return the *actual* fault code */
719 return ERROR_JTAG_DEVICE_ERROR;
722 nbytes = MIN((readcount << 1), 4);
724 for (i = 0; i < nbytes; i++)
726 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
731 readcount -= (nbytes >> 1);
740 * Synchronously read a block of 16-bit halfwords into a buffer
741 * @param dap The DAP connected to the MEM-AP.
742 * @param buffer where the halfwords will be stored (in host byte order).
743 * @param count How many halfwords to read.
744 * @param address Memory address from which to read words; all the
745 * words must be readable by the currently selected MEM-AP.
747 int mem_ap_read_buf_u16(struct adiv5_dap *dap, uint8_t *buffer,
748 int count, uint32_t address)
751 int retval = ERROR_OK;
754 return mem_ap_read_buf_packed_u16(dap, buffer, count, address);
758 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
759 if (retval != ERROR_OK)
761 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
762 if (retval != ERROR_OK)
765 retval = dap_run(dap);
766 if (retval != ERROR_OK)
771 for (i = 0; i < 2; i++)
773 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
780 uint16_t svalue = (invalue >> 8 * (address & 0x3));
781 memcpy(buffer, &svalue, sizeof(uint16_t));
791 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
792 * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
794 * The solution is to arrange for a large out/in scan in this loop and
795 * and convert data afterwards.
797 static int mem_ap_read_buf_packed_u8(struct adiv5_dap *dap,
798 uint8_t *buffer, int count, uint32_t address)
801 int retval = ERROR_OK;
802 int wcount, blocksize, readcount, i;
810 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
811 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
813 if (wcount < blocksize)
816 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
817 if (retval != ERROR_OK)
819 readcount = blocksize;
823 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
824 if (dap_run(dap) != ERROR_OK)
826 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
827 /* REVISIT return the *actual* fault code */
828 return ERROR_JTAG_DEVICE_ERROR;
831 nbytes = MIN(readcount, 4);
833 for (i = 0; i < nbytes; i++)
835 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
849 * Synchronously read a block of bytes into a buffer
850 * @param dap The DAP connected to the MEM-AP.
851 * @param buffer where the bytes will be stored.
852 * @param count How many bytes to read.
853 * @param address Memory address from which to read data; all the
854 * data must be readable by the currently selected MEM-AP.
856 int mem_ap_read_buf_u8(struct adiv5_dap *dap, uint8_t *buffer,
857 int count, uint32_t address)
860 int retval = ERROR_OK;
863 return mem_ap_read_buf_packed_u8(dap, buffer, count, address);
867 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
868 if (retval != ERROR_OK)
870 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
871 if (retval != ERROR_OK)
873 retval = dap_run(dap);
874 if (retval != ERROR_OK)
877 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
886 /*--------------------------------------------------------------------------*/
889 /* FIXME don't import ... just initialize as
890 * part of DAP transport setup
892 extern const struct dap_ops jtag_dp_ops;
894 /*--------------------------------------------------------------------------*/
897 * Initialize a DAP. This sets up the power domains, prepares the DP
898 * for further use, and arranges to use AP #0 for all AP operations
899 * until dap_ap-select() changes that policy.
901 * @param dap The DAP being initialized.
903 * @todo Rename this. We also need an initialization scheme which account
904 * for SWD transports not just JTAG; that will need to address differences
905 * in layering. (JTAG is useful without any debug target; but not SWD.)
906 * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
908 int ahbap_debugport_init(struct adiv5_dap *dap)
910 uint32_t idreg, romaddr, dummy;
917 /* JTAG-DP or SWJ-DP, in JTAG mode */
918 dap->ops = &jtag_dp_ops;
920 /* Default MEM-AP setup.
922 * REVISIT AP #0 may be an inappropriate default for this.
923 * Should we probe, or take a hint from the caller?
924 * Presumably we can ignore the possibility of multiple APs.
927 dap_ap_select(dap, 0);
929 /* DP initialization */
931 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
932 if (retval != ERROR_OK)
935 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
936 if (retval != ERROR_OK)
939 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
940 if (retval != ERROR_OK)
943 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
944 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
945 if (retval != ERROR_OK)
948 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
949 if (retval != ERROR_OK)
951 if ((retval = dap_run(dap)) != ERROR_OK)
954 /* Check that we have debug power domains activated */
955 while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
957 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
958 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
959 if (retval != ERROR_OK)
961 if ((retval = dap_run(dap)) != ERROR_OK)
966 while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
968 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
969 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
970 if (retval != ERROR_OK)
972 if ((retval = dap_run(dap)) != ERROR_OK)
977 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
978 if (retval != ERROR_OK)
980 /* With debug power on we can activate OVERRUN checking */
981 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
982 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
983 if (retval != ERROR_OK)
985 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
986 if (retval != ERROR_OK)
990 * REVISIT this isn't actually *initializing* anything in an AP,
991 * and doesn't care if it's a MEM-AP at all (much less AHB-AP).
992 * Should it? If the ROM address is valid, is this the right
993 * place to scan the table and do any topology detection?
995 retval = dap_queue_ap_read(dap, AP_REG_IDR, &idreg);
996 retval = dap_queue_ap_read(dap, AP_REG_BASE, &romaddr);
998 if ((retval = dap_run(dap)) != ERROR_OK)
1001 LOG_DEBUG("MEM-AP #%" PRId32 " ID Register 0x%" PRIx32
1002 ", Debug ROM Address 0x%" PRIx32,
1003 dap->apsel, idreg, romaddr);
1008 /* CID interpretation -- see ARM IHI 0029B section 3
1009 * and ARM IHI 0031A table 13-3.
1011 static const char *class_description[16] ={
1012 "Reserved", "ROM table", "Reserved", "Reserved",
1013 "Reserved", "Reserved", "Reserved", "Reserved",
1014 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1015 "Reserved", "OptimoDE DESS",
1016 "Generic IP component", "PrimeCell or System component"
1020 is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
1022 return cid3 == 0xb1 && cid2 == 0x05
1023 && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1026 static int dap_info_command(struct command_context *cmd_ctx,
1027 struct adiv5_dap *dap, int apsel)
1030 uint32_t dbgbase, apid;
1031 int romtable_present = 0;
1035 /* AP address is in bits 31:24 of DP_SELECT */
1037 return ERROR_INVALID_ARGUMENTS;
1039 apselold = dap->apsel;
1040 dap_ap_select(dap, apsel);
1041 retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase);
1042 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1043 retval = dap_run(dap);
1044 if (retval != ERROR_OK)
1047 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1048 mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1049 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1055 command_print(cmd_ctx, "\tType is JTAG-AP");
1058 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1061 command_print(cmd_ctx, "\tType is MEM-AP APB");
1064 command_print(cmd_ctx, "\tUnknown AP type");
1068 /* NOTE: a MEM-AP may have a single CoreSight component that's
1069 * not a ROM table ... or have no such components at all.
1072 command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32,
1077 command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel);
1080 romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1081 if (romtable_present)
1083 uint32_t cid0,cid1,cid2,cid3,memtype,romentry;
1084 uint16_t entry_offset;
1086 /* bit 16 of apid indicates a memory access port */
1088 command_print(cmd_ctx, "\tValid ROM table present");
1090 command_print(cmd_ctx, "\tROM table in legacy format");
1092 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1093 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1094 if (retval != ERROR_OK)
1096 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1097 if (retval != ERROR_OK)
1099 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1100 if (retval != ERROR_OK)
1102 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1103 if (retval != ERROR_OK)
1105 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1106 if (retval != ERROR_OK)
1108 retval = dap_run(dap);
1109 if (retval != ERROR_OK)
1112 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1113 command_print(cmd_ctx, "\tCID3 0x%2.2x"
1117 (unsigned) cid3, (unsigned)cid2,
1118 (unsigned) cid1, (unsigned) cid0);
1120 command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1122 command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1123 "Dedicated debug bus.");
1125 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1129 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1130 if (retval != ERROR_OK)
1132 command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
1135 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1136 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1137 uint32_t component_base;
1141 component_base = (dbgbase & 0xFFFFF000)
1142 + (romentry & 0xFFFFF000);
1144 /* IDs are in last 4K section */
1147 retval = mem_ap_read_atomic_u32(dap,
1148 component_base + 0xFE0, &c_pid0);
1149 if (retval != ERROR_OK)
1152 retval = mem_ap_read_atomic_u32(dap,
1153 component_base + 0xFE4, &c_pid1);
1154 if (retval != ERROR_OK)
1157 retval = mem_ap_read_atomic_u32(dap,
1158 component_base + 0xFE8, &c_pid2);
1159 if (retval != ERROR_OK)
1162 retval = mem_ap_read_atomic_u32(dap,
1163 component_base + 0xFEC, &c_pid3);
1164 if (retval != ERROR_OK)
1167 retval = mem_ap_read_atomic_u32(dap,
1168 component_base + 0xFD0, &c_pid4);
1169 if (retval != ERROR_OK)
1173 retval = mem_ap_read_atomic_u32(dap,
1174 component_base + 0xFF0, &c_cid0);
1175 if (retval != ERROR_OK)
1178 retval = mem_ap_read_atomic_u32(dap,
1179 component_base + 0xFF4, &c_cid1);
1180 if (retval != ERROR_OK)
1183 retval = mem_ap_read_atomic_u32(dap,
1184 component_base + 0xFF8, &c_cid2);
1185 if (retval != ERROR_OK)
1188 retval = mem_ap_read_atomic_u32(dap,
1189 component_base + 0xFFC, &c_cid3);
1190 if (retval != ERROR_OK)
1195 command_print(cmd_ctx,
1196 "\t\tComponent base address 0x%" PRIx32
1197 ", start address 0x%" PRIx32,
1199 /* component may take multiple 4K pages */
1200 component_base - 0x1000*(c_pid4 >> 4));
1201 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1202 (int) (c_cid1 >> 4) & 0xf,
1203 /* See ARM IHI 0029B Table 3-3 */
1204 class_description[(c_cid1 >> 4) & 0xf]);
1206 /* CoreSight component? */
1207 if (((c_cid1 >> 4) & 0x0f) == 9) {
1210 char *major = "Reserved", *subtype = "Reserved";
1212 retval = mem_ap_read_atomic_u32(dap,
1213 (component_base & 0xfffff000) | 0xfcc,
1215 if (retval != ERROR_OK)
1217 minor = (devtype >> 4) & 0x0f;
1218 switch (devtype & 0x0f) {
1220 major = "Miscellaneous";
1226 subtype = "Validation component";
1231 major = "Trace Sink";
1245 major = "Trace Link";
1251 subtype = "Funnel, router";
1257 subtype = "FIFO, buffer";
1262 major = "Trace Source";
1268 subtype = "Processor";
1274 subtype = "Engine/Coprocessor";
1282 major = "Debug Control";
1288 subtype = "Trigger Matrix";
1291 subtype = "Debug Auth";
1296 major = "Debug Logic";
1302 subtype = "Processor";
1308 subtype = "Engine/Coprocessor";
1313 command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1314 (unsigned) (devtype & 0xff),
1316 /* REVISIT also show 0xfc8 DevId */
1319 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1320 command_print(cmd_ctx,
1329 command_print(cmd_ctx,
1330 "\t\tPeripheral ID[4..0] = hex "
1331 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1332 (int) c_pid4, (int) c_pid3, (int) c_pid2,
1333 (int) c_pid1, (int) c_pid0);
1335 /* Part number interpretations are from Cortex
1336 * core specs, the CoreSight components TRM
1337 * (ARM DDI 0314H), and ETM specs; also from
1338 * chip observation (e.g. TI SDTI).
1340 part_num = (c_pid0 & 0xff);
1341 part_num |= (c_pid1 & 0x0f) << 8;
1344 type = "Cortex-M3 NVIC";
1345 full = "(Interrupt Controller)";
1348 type = "Cortex-M3 ITM";
1349 full = "(Instrumentation Trace Module)";
1352 type = "Cortex-M3 DWT";
1353 full = "(Data Watchpoint and Trace)";
1356 type = "Cortex-M3 FBP";
1357 full = "(Flash Patch and Breakpoint)";
1360 type = "CoreSight ETM11";
1361 full = "(Embedded Trace)";
1363 // case 0x113: what?
1364 case 0x120: /* from OMAP3 memmap */
1366 full = "(System Debug Trace Interface)";
1368 case 0x343: /* from OMAP3 memmap */
1373 type = "Coresight CTI";
1374 full = "(Cross Trigger)";
1377 type = "Coresight ETB";
1378 full = "(Trace Buffer)";
1381 type = "Coresight CSTF";
1382 full = "(Trace Funnel)";
1385 type = "CoreSight ETM9";
1386 full = "(Embedded Trace)";
1389 type = "Coresight TPIU";
1390 full = "(Trace Port Interface Unit)";
1393 type = "Cortex-A8 ETM";
1394 full = "(Embedded Trace)";
1397 type = "Cortex-A8 CTI";
1398 full = "(Cross Trigger)";
1401 type = "Cortex-M3 TPIU";
1402 full = "(Trace Port Interface Unit)";
1405 type = "Cortex-M3 ETM";
1406 full = "(Embedded Trace)";
1409 type = "Cortex-A8 Debug";
1410 full = "(Debug Unit)";
1413 type = "-*- unrecognized -*-";
1417 command_print(cmd_ctx, "\t\tPart is %s %s",
1423 command_print(cmd_ctx, "\t\tComponent not present");
1425 command_print(cmd_ctx, "\t\tEnd of ROM table");
1428 } while (romentry > 0);
1432 command_print(cmd_ctx, "\tNo ROM table present");
1434 dap_ap_select(dap, apselold);
1439 COMMAND_HANDLER(handle_dap_info_command)
1441 struct target *target = get_current_target(CMD_CTX);
1442 struct arm *arm = target_to_arm(target);
1443 struct adiv5_dap *dap = arm->dap;
1451 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1454 return ERROR_COMMAND_SYNTAX_ERROR;
1457 return dap_info_command(CMD_CTX, dap, apsel);
1460 COMMAND_HANDLER(dap_baseaddr_command)
1462 struct target *target = get_current_target(CMD_CTX);
1463 struct arm *arm = target_to_arm(target);
1464 struct adiv5_dap *dap = arm->dap;
1466 uint32_t apsel, apselsave, baseaddr;
1469 apselsave = dap->apsel;
1475 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1476 /* AP address is in bits 31:24 of DP_SELECT */
1478 return ERROR_INVALID_ARGUMENTS;
1481 return ERROR_COMMAND_SYNTAX_ERROR;
1484 if (apselsave != apsel)
1485 dap_ap_select(dap, apsel);
1487 /* NOTE: assumes we're talking to a MEM-AP, which
1488 * has a base address. There are other kinds of AP,
1489 * though they're not common for now. This should
1490 * use the ID register to verify it's a MEM-AP.
1492 retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
1493 retval = dap_run(dap);
1494 if (retval != ERROR_OK)
1497 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1499 if (apselsave != apsel)
1500 dap_ap_select(dap, apselsave);
1505 COMMAND_HANDLER(dap_memaccess_command)
1507 struct target *target = get_current_target(CMD_CTX);
1508 struct arm *arm = target_to_arm(target);
1509 struct adiv5_dap *dap = arm->dap;
1511 uint32_t memaccess_tck;
1515 memaccess_tck = dap->memaccess_tck;
1518 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1521 return ERROR_COMMAND_SYNTAX_ERROR;
1523 dap->memaccess_tck = memaccess_tck;
1525 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1526 dap->memaccess_tck);
1531 COMMAND_HANDLER(dap_apsel_command)
1533 struct target *target = get_current_target(CMD_CTX);
1534 struct arm *arm = target_to_arm(target);
1535 struct adiv5_dap *dap = arm->dap;
1537 uint32_t apsel, apid;
1545 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1546 /* AP address is in bits 31:24 of DP_SELECT */
1548 return ERROR_INVALID_ARGUMENTS;
1551 return ERROR_COMMAND_SYNTAX_ERROR;
1554 dap_ap_select(dap, apsel);
1555 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1556 retval = dap_run(dap);
1557 if (retval != ERROR_OK)
1560 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1566 COMMAND_HANDLER(dap_apid_command)
1568 struct target *target = get_current_target(CMD_CTX);
1569 struct arm *arm = target_to_arm(target);
1570 struct adiv5_dap *dap = arm->dap;
1572 uint32_t apsel, apselsave, apid;
1575 apselsave = dap->apsel;
1581 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1582 /* AP address is in bits 31:24 of DP_SELECT */
1584 return ERROR_INVALID_ARGUMENTS;
1587 return ERROR_COMMAND_SYNTAX_ERROR;
1590 if (apselsave != apsel)
1591 dap_ap_select(dap, apsel);
1593 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1594 retval = dap_run(dap);
1595 if (retval != ERROR_OK)
1598 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1599 if (apselsave != apsel)
1600 dap_ap_select(dap, apselsave);
1605 static const struct command_registration dap_commands[] = {
1608 .handler = handle_dap_info_command,
1609 .mode = COMMAND_EXEC,
1610 .help = "display ROM table for MEM-AP "
1611 "(default currently selected AP)",
1612 .usage = "[ap_num]",
1616 .handler = dap_apsel_command,
1617 .mode = COMMAND_EXEC,
1618 .help = "Set the currently selected AP (default 0) "
1619 "and display the result",
1620 .usage = "[ap_num]",
1624 .handler = dap_apid_command,
1625 .mode = COMMAND_EXEC,
1626 .help = "return ID register from AP "
1627 "(default currently selected AP)",
1628 .usage = "[ap_num]",
1632 .handler = dap_baseaddr_command,
1633 .mode = COMMAND_EXEC,
1634 .help = "return debug base address from MEM-AP "
1635 "(default currently selected AP)",
1636 .usage = "[ap_num]",
1639 .name = "memaccess",
1640 .handler = dap_memaccess_command,
1641 .mode = COMMAND_EXEC,
1642 .help = "set/get number of extra tck for MEM-AP memory "
1643 "bus access [0-255]",
1644 .usage = "[cycles]",
1646 COMMAND_REGISTRATION_DONE
1649 const struct command_registration dap_command_handlers[] = {
1652 .mode = COMMAND_EXEC,
1653 .help = "DAP command group",
1654 .chain = dap_commands,
1656 COMMAND_REGISTRATION_DONE