1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * Copyright (C) 2009-2010 by David Brownell *
13 * Copyright (C) 2013 by Andreas Fritiofson *
14 * andreas.fritiofson@gmail.com *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published by *
18 * the Free Software Foundation; either version 2 of the License, or *
19 * (at your option) any later version. *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
26 * You should have received a copy of the GNU General Public License *
27 * along with this program; if not, write to the *
28 * Free Software Foundation, Inc., *
29 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
30 ***************************************************************************/
34 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
35 * debugging architecture. Compared with previous versions, this includes
36 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
37 * transport, and focusses on memory mapped resources as defined by the
38 * CoreSight architecture.
40 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
41 * basic components: a Debug Port (DP) transporting messages to and from a
42 * debugger, and an Access Port (AP) accessing resources. Three types of DP
43 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
44 * One uses only SWD for communication, and is called SW-DP. The third can
45 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
46 * is used to access memory mapped resources and is called a MEM-AP. Also a
47 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
49 * This programming interface allows DAP pipelined operations through a
50 * transaction queue. This primarily affects AP operations (such as using
51 * a MEM-AP to access memory or registers). If the current transaction has
52 * not finished by the time the next one must begin, and the ORUNDETECT bit
53 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
54 * further AP operations will fail. There are two basic methods to avoid
55 * such overrun errors. One involves polling for status instead of using
56 * transaction piplining. The other involves adding delays to ensure the
57 * AP has enough time to complete one operation before starting the next
58 * one. (For JTAG these delays are controlled by memaccess_tck.)
62 * Relevant specifications from ARM include:
64 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
65 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
67 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
68 * Cortex-M3(tm) TRM, ARM DDI 0337G
75 #include "jtag/interface.h"
77 #include "arm_adi_v5.h"
78 #include <helper/time_support.h>
80 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
83 uint32_t tar_block_size(uint32_t address)
84 Return the largest block starting at address that does not cross a tar block size alignment boundary
86 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
88 return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
91 /***************************************************************************
93 * DP and MEM-AP register access through APACC and DPACC *
95 ***************************************************************************/
98 * Select one of the APs connected to the specified DAP. The
99 * selection is implicitly used with future AP transactions.
100 * This is a NOP if the specified AP is already selected.
103 * @param apsel Number of the AP to (implicitly) use with further
104 * transactions. This normally identifies a MEM-AP.
106 void dap_ap_select(struct adiv5_dap *dap, uint8_t ap)
108 uint32_t new_ap = (ap << 24) & 0xFF000000;
110 if (new_ap != dap->ap_current) {
111 dap->ap_current = new_ap;
112 /* Switching AP invalidates cached values.
113 * Values MUST BE UPDATED BEFORE AP ACCESS.
115 dap->ap_bank_value = -1;
116 dap->ap_csw_value = -1;
117 dap->ap_tar_value = -1;
121 static int dap_setup_accessport_csw(struct adiv5_dap *dap, uint32_t csw)
123 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT |
124 dap->apcsw[dap->ap_current >> 24];
126 if (csw != dap->ap_csw_value) {
127 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
128 int retval = dap_queue_ap_write(dap, AP_REG_CSW, csw);
129 if (retval != ERROR_OK)
131 dap->ap_csw_value = csw;
136 static int dap_setup_accessport_tar(struct adiv5_dap *dap, uint32_t tar)
138 if (tar != dap->ap_tar_value || dap->ap_csw_value & CSW_ADDRINC_MASK) {
139 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
140 int retval = dap_queue_ap_write(dap, AP_REG_TAR, tar);
141 if (retval != ERROR_OK)
143 dap->ap_tar_value = tar;
149 * Queue transactions setting up transfer parameters for the
150 * currently selected MEM-AP.
152 * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
153 * initiate data reads or writes using memory or peripheral addresses.
154 * If the CSW is configured for it, the TAR may be automatically
155 * incremented after each transfer.
157 * @todo Rename to reflect it being specifically a MEM-AP function.
159 * @param dap The DAP connected to the MEM-AP.
160 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
161 * matches the cached value, the register is not changed.
162 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
163 * matches the cached address, the register is not changed.
165 * @return ERROR_OK if the transaction was properly queued, else a fault code.
167 int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
170 retval = dap_setup_accessport_csw(dap, csw);
171 if (retval != ERROR_OK)
173 retval = dap_setup_accessport_tar(dap, tar);
174 if (retval != ERROR_OK)
180 * Asynchronous (queued) read of a word from memory or a system register.
182 * @param dap The DAP connected to the MEM-AP performing the read.
183 * @param address Address of the 32-bit word to read; it must be
184 * readable by the currently selected MEM-AP.
185 * @param value points to where the word will be stored when the
186 * transaction queue is flushed (assuming no errors).
188 * @return ERROR_OK for success. Otherwise a fault code.
190 int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
195 /* Use banked addressing (REG_BDx) to avoid some link traffic
196 * (updating TAR) when reading several consecutive addresses.
198 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
199 address & 0xFFFFFFF0);
200 if (retval != ERROR_OK)
203 return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value);
207 * Synchronous read of a word from memory or a system register.
208 * As a side effect, this flushes any queued transactions.
210 * @param dap The DAP connected to the MEM-AP performing the read.
211 * @param address Address of the 32-bit word to read; it must be
212 * readable by the currently selected MEM-AP.
213 * @param value points to where the result will be stored.
215 * @return ERROR_OK for success; *value holds the result.
216 * Otherwise a fault code.
218 int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
223 retval = mem_ap_read_u32(dap, address, value);
224 if (retval != ERROR_OK)
231 * Asynchronous (queued) write of a word to memory or a system register.
233 * @param dap The DAP connected to the MEM-AP.
234 * @param address Address to be written; it must be writable by
235 * the currently selected MEM-AP.
236 * @param value Word that will be written to the address when transaction
237 * queue is flushed (assuming no errors).
239 * @return ERROR_OK for success. Otherwise a fault code.
241 int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
246 /* Use banked addressing (REG_BDx) to avoid some link traffic
247 * (updating TAR) when writing several consecutive addresses.
249 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
250 address & 0xFFFFFFF0);
251 if (retval != ERROR_OK)
254 return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC),
259 * Synchronous write of a word to memory or a system register.
260 * As a side effect, this flushes any queued transactions.
262 * @param dap The DAP connected to the MEM-AP.
263 * @param address Address to be written; it must be writable by
264 * the currently selected MEM-AP.
265 * @param value Word that will be written.
267 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
269 int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
272 int retval = mem_ap_write_u32(dap, address, value);
274 if (retval != ERROR_OK)
281 * Synchronous write of a block of memory, using a specific access size.
283 * @param dap The DAP connected to the MEM-AP.
284 * @param buffer The data buffer to write. No particular alignment is assumed.
285 * @param size Which access size to use, in bytes. 1, 2 or 4.
286 * @param count The number of writes to do (in size units, not bytes).
287 * @param address Address to be written; it must be writable by the currently selected MEM-AP.
288 * @param addrinc Whether the target address should be increased for each write or not. This
289 * should normally be true, except when writing to e.g. a FIFO.
290 * @return ERROR_OK on success, otherwise an error code.
292 int mem_ap_write(struct adiv5_dap *dap, const uint8_t *buffer, uint32_t size, uint32_t count,
293 uint32_t address, bool addrinc)
295 size_t nbytes = size * count;
296 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
301 csw_size = CSW_32BIT;
303 csw_size = CSW_16BIT;
307 return ERROR_TARGET_UNALIGNED_ACCESS;
309 retval = dap_setup_accessport_tar(dap, address);
310 if (retval != ERROR_OK)
314 uint32_t this_size = size;
316 /* Select packed transfer if possible */
317 if (addrinc && dap->packed_transfers && nbytes >= 4
318 && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
320 retval = dap_setup_accessport_csw(dap, csw_size | CSW_ADDRINC_PACKED);
322 retval = dap_setup_accessport_csw(dap, csw_size | csw_addrincr);
325 if (retval != ERROR_OK)
328 /* How many source bytes each transfer will consume, and their location in the DRW,
329 * depends on the type of transfer and alignment. See ARM document IHI0031C. */
330 uint32_t outvalue = 0;
333 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
334 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
336 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
338 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
343 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
344 if (retval != ERROR_OK)
347 /* Rewrite TAR if it wrapped */
348 if (addrinc && address % dap->tar_autoincr_block < size && nbytes > 0) {
349 retval = dap_setup_accessport_tar(dap, address);
350 if (retval != ERROR_OK)
355 /* REVISIT: Might want to have a queued version of this function that does not run. */
356 if (retval == ERROR_OK)
357 retval = dap_run(dap);
359 if (retval != ERROR_OK) {
361 if (dap_queue_ap_read(dap, AP_REG_TAR, &tar) == ERROR_OK
362 && dap_run(dap) == ERROR_OK)
363 LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
365 LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
372 * Synchronous read of a block of memory, using a specific access size.
374 * @param dap The DAP connected to the MEM-AP.
375 * @param buffer The data buffer to receive the data. No particular alignment is assumed.
376 * @param size Which access size to use, in bytes. 1, 2 or 4.
377 * @param count The number of reads to do (in size units, not bytes).
378 * @param address Address to be read; it must be readable by the currently selected MEM-AP.
379 * @param addrinc Whether the target address should be increased after each read or not. This
380 * should normally be true, except when reading from e.g. a FIFO.
381 * @return ERROR_OK on success, otherwise an error code.
383 int mem_ap_read(struct adiv5_dap *dap, uint8_t *buffer, uint32_t size, uint32_t count,
384 uint32_t adr, bool addrinc)
386 size_t nbytes = size * count;
387 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
389 uint32_t address = adr;
393 csw_size = CSW_32BIT;
395 csw_size = CSW_16BIT;
399 return ERROR_TARGET_UNALIGNED_ACCESS;
401 /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
402 * over-allocation if packed transfers are going to be used, but determining the real need at
403 * this point would be messy. */
404 uint32_t *read_buf = malloc(count * sizeof(uint32_t));
405 uint32_t *read_ptr = read_buf;
406 if (read_buf == NULL) {
407 LOG_ERROR("Failed to allocate read buffer");
411 retval = dap_setup_accessport_tar(dap, address);
412 if (retval != ERROR_OK) {
417 /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
418 * useful bytes it contains, and their location in the word, depends on the type of transfer
421 uint32_t this_size = size;
423 /* Select packed transfer if possible */
424 if (addrinc && dap->packed_transfers && nbytes >= 4
425 && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
427 retval = dap_setup_accessport_csw(dap, csw_size | CSW_ADDRINC_PACKED);
429 retval = dap_setup_accessport_csw(dap, csw_size | csw_addrincr);
431 if (retval != ERROR_OK)
434 retval = dap_queue_ap_read(dap, AP_REG_DRW, read_ptr++);
435 if (retval != ERROR_OK)
439 address += this_size;
441 /* Rewrite TAR if it wrapped */
442 if (addrinc && address % dap->tar_autoincr_block < size && nbytes > 0) {
443 retval = dap_setup_accessport_tar(dap, address);
444 if (retval != ERROR_OK)
449 if (retval == ERROR_OK)
450 retval = dap_run(dap);
454 nbytes = size * count;
457 /* If something failed, read TAR to find out how much data was successfully read, so we can
458 * at least give the caller what we have. */
459 if (retval != ERROR_OK) {
461 if (dap_queue_ap_read(dap, AP_REG_TAR, &tar) == ERROR_OK
462 && dap_run(dap) == ERROR_OK) {
463 LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
464 if (nbytes > tar - address)
465 nbytes = tar - address;
467 LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
472 /* Replay loop to populate caller's buffer from the correct word and byte lane */
474 uint32_t this_size = size;
476 if (addrinc && dap->packed_transfers && nbytes >= 4
477 && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
483 *buffer++ = *read_ptr >> 8 * (address++ & 3);
484 *buffer++ = *read_ptr >> 8 * (address++ & 3);
486 *buffer++ = *read_ptr >> 8 * (address++ & 3);
488 *buffer++ = *read_ptr >> 8 * (address++ & 3);
499 /*--------------------------------------------------------------------*/
500 /* Wrapping function with selection of AP */
501 /*--------------------------------------------------------------------*/
502 int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
503 uint32_t address, uint32_t *value)
505 dap_ap_select(swjdp, ap);
506 return mem_ap_read_u32(swjdp, address, value);
509 int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap,
510 uint32_t address, uint32_t value)
512 dap_ap_select(swjdp, ap);
513 return mem_ap_write_u32(swjdp, address, value);
516 int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
517 uint32_t address, uint32_t *value)
519 dap_ap_select(swjdp, ap);
520 return mem_ap_read_atomic_u32(swjdp, address, value);
523 int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
524 uint32_t address, uint32_t value)
526 dap_ap_select(swjdp, ap);
527 return mem_ap_write_atomic_u32(swjdp, address, value);
530 int mem_ap_sel_read_buf(struct adiv5_dap *swjdp, uint8_t ap,
531 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
533 dap_ap_select(swjdp, ap);
534 return mem_ap_read(swjdp, buffer, size, count, address, true);
537 int mem_ap_sel_write_buf(struct adiv5_dap *swjdp, uint8_t ap,
538 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
540 dap_ap_select(swjdp, ap);
541 return mem_ap_write(swjdp, buffer, size, count, address, true);
544 int mem_ap_sel_read_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap,
545 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
547 dap_ap_select(swjdp, ap);
548 return mem_ap_read(swjdp, buffer, size, count, address, false);
551 int mem_ap_sel_write_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap,
552 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
554 dap_ap_select(swjdp, ap);
555 return mem_ap_write(swjdp, buffer, size, count, address, false);
558 #define MDM_REG_STAT 0x00
559 #define MDM_REG_CTRL 0x04
560 #define MDM_REG_ID 0xfc
562 #define MDM_STAT_FMEACK (1<<0)
563 #define MDM_STAT_FREADY (1<<1)
564 #define MDM_STAT_SYSSEC (1<<2)
565 #define MDM_STAT_SYSRES (1<<3)
566 #define MDM_STAT_FMEEN (1<<5)
567 #define MDM_STAT_BACKDOOREN (1<<6)
568 #define MDM_STAT_LPEN (1<<7)
569 #define MDM_STAT_VLPEN (1<<8)
570 #define MDM_STAT_LLSMODEXIT (1<<9)
571 #define MDM_STAT_VLLSXMODEXIT (1<<10)
572 #define MDM_STAT_CORE_HALTED (1<<16)
573 #define MDM_STAT_CORE_SLEEPDEEP (1<<17)
574 #define MDM_STAT_CORESLEEPING (1<<18)
576 #define MEM_CTRL_FMEIP (1<<0)
577 #define MEM_CTRL_DBG_DIS (1<<1)
578 #define MEM_CTRL_DBG_REQ (1<<2)
579 #define MEM_CTRL_SYS_RES_REQ (1<<3)
580 #define MEM_CTRL_CORE_HOLD_RES (1<<4)
581 #define MEM_CTRL_VLLSX_DBG_REQ (1<<5)
582 #define MEM_CTRL_VLLSX_DBG_ACK (1<<6)
583 #define MEM_CTRL_VLLSX_STAT_ACK (1<<7)
585 #define MDM_ACCESS_TIMEOUT 3000 /* ms */
590 int dap_syssec_kinetis_mdmap(struct adiv5_dap *dap)
595 enum reset_types jtag_reset_config = jtag_get_reset_config();
597 dap_ap_select(dap, 1);
599 /* first check mdm-ap id register */
600 retval = dap_queue_ap_read(dap, MDM_REG_ID, &val);
601 if (retval != ERROR_OK)
605 if (val != 0x001C0000) {
606 LOG_DEBUG("id doesn't match %08" PRIX32 " != 0x001C0000", val);
607 dap_ap_select(dap, 0);
611 /* read and parse status register
612 * it's important that the device is out of
616 if (timeout++ > MDM_ACCESS_TIMEOUT) {
617 LOG_DEBUG("MDMAP : flash ready timeout");
620 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
621 if (retval != ERROR_OK)
625 LOG_DEBUG("MDM_REG_STAT %08" PRIX32, val);
626 if (val & MDM_STAT_FREADY)
631 if ((val & MDM_STAT_SYSSEC)) {
632 LOG_DEBUG("MDMAP: system is secured, masserase needed");
634 if (!(val & MDM_STAT_FMEEN))
635 LOG_DEBUG("MDMAP: masserase is disabled");
637 /* we need to assert reset */
638 if (jtag_reset_config & RESET_HAS_SRST) {
639 /* default to asserting srst */
640 adapter_assert_reset();
642 LOG_DEBUG("SRST not configured");
643 dap_ap_select(dap, 0);
648 if (timeout++ > MDM_ACCESS_TIMEOUT) {
649 LOG_DEBUG("MDMAP : flash ready timeout");
652 retval = dap_queue_ap_write(dap, MDM_REG_CTRL, MEM_CTRL_FMEIP);
653 if (retval != ERROR_OK)
656 /* read status register and wait for ready */
657 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
658 if (retval != ERROR_OK)
661 LOG_DEBUG("MDM_REG_STAT %08" PRIX32, val);
669 if (timeout++ > MDM_ACCESS_TIMEOUT) {
670 LOG_DEBUG("MDMAP : flash ready timeout");
673 retval = dap_queue_ap_write(dap, MDM_REG_CTRL, 0);
674 if (retval != ERROR_OK)
677 /* read status register */
678 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
679 if (retval != ERROR_OK)
682 LOG_DEBUG("MDM_REG_STAT %08" PRIX32, val);
683 /* read control register and wait for ready */
684 retval = dap_queue_ap_read(dap, MDM_REG_CTRL, &val);
685 if (retval != ERROR_OK)
688 LOG_DEBUG("MDM_REG_CTRL %08" PRIX32, val);
697 dap_ap_select(dap, 0);
703 struct dap_syssec_filter {
707 int (*dap_init)(struct adiv5_dap *dap);
711 static struct dap_syssec_filter dap_syssec_filter_data[] = {
712 { 0x4BA00477, dap_syssec_kinetis_mdmap }
718 int dap_syssec(struct adiv5_dap *dap)
721 struct jtag_tap *tap;
723 for (i = 0; i < sizeof(dap_syssec_filter_data); i++) {
724 tap = dap->jtag_info->tap;
726 while (tap != NULL) {
727 if (tap->hasidcode && (dap_syssec_filter_data[i].idcode == tap->idcode)) {
728 LOG_DEBUG("DAP: mdmap_init for idcode: %08" PRIx32, tap->idcode);
729 dap_syssec_filter_data[i].dap_init(dap);
738 /*--------------------------------------------------------------------------*/
741 /* FIXME don't import ... just initialize as
742 * part of DAP transport setup
744 extern const struct dap_ops jtag_dp_ops;
746 /*--------------------------------------------------------------------------*/
749 * Initialize a DAP. This sets up the power domains, prepares the DP
750 * for further use, and arranges to use AP #0 for all AP operations
751 * until dap_ap-select() changes that policy.
753 * @param dap The DAP being initialized.
755 * @todo Rename this. We also need an initialization scheme which account
756 * for SWD transports not just JTAG; that will need to address differences
757 * in layering. (JTAG is useful without any debug target; but not SWD.)
758 * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
760 int ahbap_debugport_init(struct adiv5_dap *dap)
768 /* JTAG-DP or SWJ-DP, in JTAG mode
769 * ... for SWD mode this is patched as part
773 dap->ops = &jtag_dp_ops;
775 /* Default MEM-AP setup.
777 * REVISIT AP #0 may be an inappropriate default for this.
778 * Should we probe, or take a hint from the caller?
779 * Presumably we can ignore the possibility of multiple APs.
781 dap->ap_current = !0;
782 dap_ap_select(dap, 0);
784 /* DP initialization */
786 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
787 if (retval != ERROR_OK)
790 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
791 if (retval != ERROR_OK)
794 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
795 if (retval != ERROR_OK)
798 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
799 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
800 if (retval != ERROR_OK)
803 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
804 if (retval != ERROR_OK)
806 retval = dap_run(dap);
807 if (retval != ERROR_OK)
810 /* Check that we have debug power domains activated */
811 while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10)) {
812 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
813 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
814 if (retval != ERROR_OK)
816 retval = dap_run(dap);
817 if (retval != ERROR_OK)
822 while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10)) {
823 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
824 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
825 if (retval != ERROR_OK)
827 retval = dap_run(dap);
828 if (retval != ERROR_OK)
833 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
834 if (retval != ERROR_OK)
836 /* With debug power on we can activate OVERRUN checking */
837 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
838 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
839 if (retval != ERROR_OK)
841 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
842 if (retval != ERROR_OK)
847 /* check that we support packed transfers */
850 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
851 if (retval != ERROR_OK)
854 retval = dap_queue_ap_read(dap, AP_REG_CSW, &csw);
855 if (retval != ERROR_OK)
858 retval = dap_run(dap);
859 if (retval != ERROR_OK)
862 if (csw & CSW_ADDRINC_PACKED)
863 dap->packed_transfers = true;
865 dap->packed_transfers = false;
867 LOG_DEBUG("MEM_AP Packed Transfers: %s",
868 dap->packed_transfers ? "enabled" : "disabled");
873 /* CID interpretation -- see ARM IHI 0029B section 3
874 * and ARM IHI 0031A table 13-3.
876 static const char *class_description[16] = {
877 "Reserved", "ROM table", "Reserved", "Reserved",
878 "Reserved", "Reserved", "Reserved", "Reserved",
879 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
880 "Reserved", "OptimoDE DESS",
881 "Generic IP component", "PrimeCell or System component"
884 static bool is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
886 return cid3 == 0xb1 && cid2 == 0x05
887 && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
891 * This function checks the ID for each access port to find the requested Access Port type
893 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, uint8_t *ap_num_out)
897 /* Maximum AP number is 255 since the SELECT register is 8 bits */
898 for (ap = 0; ap <= 255; ap++) {
900 /* read the IDR register of the Access Port */
902 dap_ap_select(dap, ap);
904 int retval = dap_queue_ap_read(dap, AP_REG_IDR, &id_val);
905 if (retval != ERROR_OK)
908 retval = dap_run(dap);
912 * 27-24 : JEDEC bank (0x4 for ARM)
913 * 23-17 : JEDEC code (0x3B for ARM)
916 * 7-0 : AP Identity (1=AHB-AP 2=APB-AP 0x10=JTAG-AP)
919 /* Reading register for a non-existant AP should not cause an error,
920 * but just to be sure, try to continue searching if an error does happen.
922 if ((retval == ERROR_OK) && /* Register read success */
923 ((id_val & 0x0FFF0000) == 0x04770000) && /* Jedec codes match */
924 ((id_val & 0xFF) == type_to_find)) { /* type matches*/
926 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
927 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
928 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
929 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
937 LOG_DEBUG("No %s found",
938 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
939 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
940 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
944 int dap_get_debugbase(struct adiv5_dap *dap, int ap,
945 uint32_t *out_dbgbase, uint32_t *out_apid)
949 uint32_t dbgbase, apid;
951 /* AP address is in bits 31:24 of DP_SELECT */
953 return ERROR_COMMAND_SYNTAX_ERROR;
955 ap_old = dap->ap_current;
956 dap_ap_select(dap, ap);
958 retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase);
959 if (retval != ERROR_OK)
961 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
962 if (retval != ERROR_OK)
964 retval = dap_run(dap);
965 if (retval != ERROR_OK)
968 /* Excavate the device ID code */
969 struct jtag_tap *tap = dap->jtag_info->tap;
970 while (tap != NULL) {
975 if (tap == NULL || !tap->hasidcode)
978 dap_ap_select(dap, ap_old);
980 /* The asignment happens only here to prevent modification of these
981 * values before they are certain. */
982 *out_dbgbase = dbgbase;
988 int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
989 uint32_t dbgbase, uint8_t type, uint32_t *addr)
992 uint32_t romentry, entry_offset = 0, component_base, devtype;
993 int retval = ERROR_FAIL;
996 return ERROR_COMMAND_SYNTAX_ERROR;
998 ap_old = dap->ap_current;
999 dap_ap_select(dap, ap);
1002 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) |
1003 entry_offset, &romentry);
1004 if (retval != ERROR_OK)
1007 component_base = (dbgbase & 0xFFFFF000)
1008 + (romentry & 0xFFFFF000);
1010 if (romentry & 0x1) {
1011 retval = mem_ap_read_atomic_u32(dap,
1012 (component_base & 0xfffff000) | 0xfcc,
1014 if (retval != ERROR_OK)
1016 if ((devtype & 0xff) == type) {
1017 *addr = component_base;
1023 } while (romentry > 0);
1025 dap_ap_select(dap, ap_old);
1030 static int dap_rom_display(struct command_context *cmd_ctx,
1031 struct adiv5_dap *dap, int ap, uint32_t dbgbase, int depth)
1034 uint32_t cid0, cid1, cid2, cid3, memtype, romentry;
1035 uint16_t entry_offset;
1039 command_print(cmd_ctx, "\tTables too deep");
1044 snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
1046 /* bit 16 of apid indicates a memory access port */
1048 command_print(cmd_ctx, "\t%sValid ROM table present", tabs);
1050 command_print(cmd_ctx, "\t%sROM table in legacy format", tabs);
1052 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1053 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1054 if (retval != ERROR_OK)
1056 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1057 if (retval != ERROR_OK)
1059 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1060 if (retval != ERROR_OK)
1062 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1063 if (retval != ERROR_OK)
1065 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1066 if (retval != ERROR_OK)
1068 retval = dap_run(dap);
1069 if (retval != ERROR_OK)
1072 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1073 command_print(cmd_ctx, "\t%sCID3 0x%02x"
1078 (unsigned)cid3, (unsigned)cid2,
1079 (unsigned)cid1, (unsigned)cid0);
1081 command_print(cmd_ctx, "\t%sMEMTYPE system memory present on bus", tabs);
1083 command_print(cmd_ctx, "\t%sMEMTYPE system memory not present: dedicated debug bus", tabs);
1085 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1086 for (entry_offset = 0; ; entry_offset += 4) {
1087 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1088 if (retval != ERROR_OK)
1090 command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
1091 tabs, entry_offset, romentry);
1092 if (romentry & 0x01) {
1093 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1094 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1095 uint32_t component_base;
1099 component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000);
1101 /* IDs are in last 4K section */
1102 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE0, &c_pid0);
1103 if (retval != ERROR_OK) {
1104 command_print(cmd_ctx, "\t%s\tCan't read component with base address 0x%" PRIx32
1105 ", the corresponding core might be turned off", tabs, component_base);
1109 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE4, &c_pid1);
1110 if (retval != ERROR_OK)
1113 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE8, &c_pid2);
1114 if (retval != ERROR_OK)
1117 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFEC, &c_pid3);
1118 if (retval != ERROR_OK)
1121 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFD0, &c_pid4);
1122 if (retval != ERROR_OK)
1126 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF0, &c_cid0);
1127 if (retval != ERROR_OK)
1130 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF4, &c_cid1);
1131 if (retval != ERROR_OK)
1134 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF8, &c_cid2);
1135 if (retval != ERROR_OK)
1138 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFFC, &c_cid3);
1139 if (retval != ERROR_OK)
1143 command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 ", "
1144 "start address 0x%" PRIx32, component_base,
1145 /* component may take multiple 4K pages */
1146 (uint32_t)(component_base - 0x1000*(c_pid4 >> 4)));
1147 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1148 (c_cid1 >> 4) & 0xf,
1149 /* See ARM IHI 0029B Table 3-3 */
1150 class_description[(c_cid1 >> 4) & 0xf]);
1152 /* CoreSight component? */
1153 if (((c_cid1 >> 4) & 0x0f) == 9) {
1156 char *major = "Reserved", *subtype = "Reserved";
1158 retval = mem_ap_read_atomic_u32(dap,
1159 (component_base & 0xfffff000) | 0xfcc,
1161 if (retval != ERROR_OK)
1163 minor = (devtype >> 4) & 0x0f;
1164 switch (devtype & 0x0f) {
1166 major = "Miscellaneous";
1172 subtype = "Validation component";
1177 major = "Trace Sink";
1191 major = "Trace Link";
1197 subtype = "Funnel, router";
1203 subtype = "FIFO, buffer";
1208 major = "Trace Source";
1214 subtype = "Processor";
1220 subtype = "Engine/Coprocessor";
1228 major = "Debug Control";
1234 subtype = "Trigger Matrix";
1237 subtype = "Debug Auth";
1242 major = "Debug Logic";
1248 subtype = "Processor";
1254 subtype = "Engine/Coprocessor";
1259 command_print(cmd_ctx, "\t\tType is 0x%02x, %s, %s",
1262 /* REVISIT also show 0xfc8 DevId */
1265 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1266 command_print(cmd_ctx,
1275 command_print(cmd_ctx,
1276 "\t\tPeripheral ID[4..0] = hex "
1277 "%02x %02x %02x %02x %02x",
1278 (int)c_pid4, (int)c_pid3, (int)c_pid2,
1279 (int)c_pid1, (int)c_pid0);
1281 /* Part number interpretations are from Cortex
1282 * core specs, the CoreSight components TRM
1283 * (ARM DDI 0314H), CoreSight System Design
1284 * Guide (ARM DGI 0012D) and ETM specs; also
1285 * from chip observation (e.g. TI SDTI).
1287 part_num = (c_pid0 & 0xff);
1288 part_num |= (c_pid1 & 0x0f) << 8;
1291 type = "Cortex-M3 NVIC";
1292 full = "(Interrupt Controller)";
1295 type = "Cortex-M3 ITM";
1296 full = "(Instrumentation Trace Module)";
1299 type = "Cortex-M3 DWT";
1300 full = "(Data Watchpoint and Trace)";
1303 type = "Cortex-M3 FBP";
1304 full = "(Flash Patch and Breakpoint)";
1307 type = "Cortex-M4 SCS";
1308 full = "(System Control Space)";
1311 type = "CoreSight ETM11";
1312 full = "(Embedded Trace)";
1314 /* case 0x113: what? */
1315 case 0x120: /* from OMAP3 memmap */
1317 full = "(System Debug Trace Interface)";
1319 case 0x343: /* from OMAP3 memmap */
1324 type = "Coresight CTI";
1325 full = "(Cross Trigger)";
1328 type = "Coresight ETB";
1329 full = "(Trace Buffer)";
1332 type = "Coresight CSTF";
1333 full = "(Trace Funnel)";
1336 type = "CoreSight ETM9";
1337 full = "(Embedded Trace)";
1340 type = "Coresight TPIU";
1341 full = "(Trace Port Interface Unit)";
1344 type = "Coresight ITM";
1345 full = "(Instrumentation Trace Macrocell)";
1348 type = "Cortex-A8 ETM";
1349 full = "(Embedded Trace)";
1352 type = "Cortex-A8 CTI";
1353 full = "(Cross Trigger)";
1356 type = "Cortex-M3 TPIU";
1357 full = "(Trace Port Interface Unit)";
1360 type = "Cortex-M3 ETM";
1361 full = "(Embedded Trace)";
1364 type = "Cortex-M4 ETM";
1365 full = "(Embedded Trace)";
1368 type = "Cortex-R4 ETM";
1369 full = "(Embedded Trace)";
1372 type = "CoreSight Component";
1373 full = "(unidentified Cortex-A9 component)";
1376 type = "CoreSight PMU";
1377 full = "(Performance Monitoring Unit)";
1380 type = "Cortex-M4 TPUI";
1381 full = "(Trace Port Interface Unit)";
1384 type = "Cortex-A8 Debug";
1385 full = "(Debug Unit)";
1388 type = "Cortex-A9 Debug";
1389 full = "(Debug Unit)";
1392 type = "-*- unrecognized -*-";
1396 command_print(cmd_ctx, "\t\tPart is %s %s",
1400 if (((c_cid1 >> 4) & 0x0f) == 1) {
1401 retval = dap_rom_display(cmd_ctx, dap, ap, component_base, depth + 1);
1402 if (retval != ERROR_OK)
1407 command_print(cmd_ctx, "\t\tComponent not present");
1412 command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs);
1416 static int dap_info_command(struct command_context *cmd_ctx,
1417 struct adiv5_dap *dap, int ap)
1420 uint32_t dbgbase = 0, apid = 0; /* Silence gcc by initializing */
1421 int romtable_present = 0;
1425 retval = dap_get_debugbase(dap, ap, &dbgbase, &apid);
1426 if (retval != ERROR_OK)
1429 ap_old = dap->ap_current;
1430 dap_ap_select(dap, ap);
1432 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1433 mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1434 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1436 switch (apid&0x0F) {
1438 command_print(cmd_ctx, "\tType is JTAG-AP");
1441 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1444 command_print(cmd_ctx, "\tType is MEM-AP APB");
1447 command_print(cmd_ctx, "\tUnknown AP type");
1451 /* NOTE: a MEM-AP may have a single CoreSight component that's
1452 * not a ROM table ... or have no such components at all.
1455 command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32, dbgbase);
1457 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap);
1459 romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1460 if (romtable_present) {
1461 dap_rom_display(cmd_ctx, dap, ap, dbgbase, 0);
1463 command_print(cmd_ctx, "\tNo ROM table present");
1464 dap_ap_select(dap, ap_old);
1469 COMMAND_HANDLER(handle_dap_info_command)
1471 struct target *target = get_current_target(CMD_CTX);
1472 struct arm *arm = target_to_arm(target);
1473 struct adiv5_dap *dap = arm->dap;
1481 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1484 return ERROR_COMMAND_SYNTAX_ERROR;
1487 return dap_info_command(CMD_CTX, dap, apsel);
1490 COMMAND_HANDLER(dap_baseaddr_command)
1492 struct target *target = get_current_target(CMD_CTX);
1493 struct arm *arm = target_to_arm(target);
1494 struct adiv5_dap *dap = arm->dap;
1496 uint32_t apsel, baseaddr;
1504 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1505 /* AP address is in bits 31:24 of DP_SELECT */
1507 return ERROR_COMMAND_SYNTAX_ERROR;
1510 return ERROR_COMMAND_SYNTAX_ERROR;
1513 dap_ap_select(dap, apsel);
1515 /* NOTE: assumes we're talking to a MEM-AP, which
1516 * has a base address. There are other kinds of AP,
1517 * though they're not common for now. This should
1518 * use the ID register to verify it's a MEM-AP.
1520 retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
1521 if (retval != ERROR_OK)
1523 retval = dap_run(dap);
1524 if (retval != ERROR_OK)
1527 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1532 COMMAND_HANDLER(dap_memaccess_command)
1534 struct target *target = get_current_target(CMD_CTX);
1535 struct arm *arm = target_to_arm(target);
1536 struct adiv5_dap *dap = arm->dap;
1538 uint32_t memaccess_tck;
1542 memaccess_tck = dap->memaccess_tck;
1545 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1548 return ERROR_COMMAND_SYNTAX_ERROR;
1550 dap->memaccess_tck = memaccess_tck;
1552 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1553 dap->memaccess_tck);
1558 COMMAND_HANDLER(dap_apsel_command)
1560 struct target *target = get_current_target(CMD_CTX);
1561 struct arm *arm = target_to_arm(target);
1562 struct adiv5_dap *dap = arm->dap;
1564 uint32_t apsel, apid;
1572 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1573 /* AP address is in bits 31:24 of DP_SELECT */
1575 return ERROR_COMMAND_SYNTAX_ERROR;
1578 return ERROR_COMMAND_SYNTAX_ERROR;
1582 dap_ap_select(dap, apsel);
1584 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1585 if (retval != ERROR_OK)
1587 retval = dap_run(dap);
1588 if (retval != ERROR_OK)
1591 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1597 COMMAND_HANDLER(dap_apcsw_command)
1599 struct target *target = get_current_target(CMD_CTX);
1600 struct arm *arm = target_to_arm(target);
1601 struct adiv5_dap *dap = arm->dap;
1603 uint32_t apcsw = dap->apcsw[dap->apsel], sprot = 0;
1607 command_print(CMD_CTX, "apsel %" PRIi32 " selected, csw 0x%8.8" PRIx32,
1608 (dap->apsel), apcsw);
1611 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], sprot);
1612 /* AP address is in bits 31:24 of DP_SELECT */
1614 return ERROR_COMMAND_SYNTAX_ERROR;
1618 apcsw &= ~CSW_SPROT;
1621 return ERROR_COMMAND_SYNTAX_ERROR;
1623 dap->apcsw[dap->apsel] = apcsw;
1630 COMMAND_HANDLER(dap_apid_command)
1632 struct target *target = get_current_target(CMD_CTX);
1633 struct arm *arm = target_to_arm(target);
1634 struct adiv5_dap *dap = arm->dap;
1636 uint32_t apsel, apid;
1644 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1645 /* AP address is in bits 31:24 of DP_SELECT */
1647 return ERROR_COMMAND_SYNTAX_ERROR;
1650 return ERROR_COMMAND_SYNTAX_ERROR;
1653 dap_ap_select(dap, apsel);
1655 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1656 if (retval != ERROR_OK)
1658 retval = dap_run(dap);
1659 if (retval != ERROR_OK)
1662 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1667 static const struct command_registration dap_commands[] = {
1670 .handler = handle_dap_info_command,
1671 .mode = COMMAND_EXEC,
1672 .help = "display ROM table for MEM-AP "
1673 "(default currently selected AP)",
1674 .usage = "[ap_num]",
1678 .handler = dap_apsel_command,
1679 .mode = COMMAND_EXEC,
1680 .help = "Set the currently selected AP (default 0) "
1681 "and display the result",
1682 .usage = "[ap_num]",
1686 .handler = dap_apcsw_command,
1687 .mode = COMMAND_EXEC,
1688 .help = "Set csw access bit ",
1694 .handler = dap_apid_command,
1695 .mode = COMMAND_EXEC,
1696 .help = "return ID register from AP "
1697 "(default currently selected AP)",
1698 .usage = "[ap_num]",
1702 .handler = dap_baseaddr_command,
1703 .mode = COMMAND_EXEC,
1704 .help = "return debug base address from MEM-AP "
1705 "(default currently selected AP)",
1706 .usage = "[ap_num]",
1709 .name = "memaccess",
1710 .handler = dap_memaccess_command,
1711 .mode = COMMAND_EXEC,
1712 .help = "set/get number of extra tck for MEM-AP memory "
1713 "bus access [0-255]",
1714 .usage = "[cycles]",
1716 COMMAND_REGISTRATION_DONE
1719 const struct command_registration dap_command_handlers[] = {
1722 .mode = COMMAND_EXEC,
1723 .help = "DAP command group",
1725 .chain = dap_commands,
1727 COMMAND_REGISTRATION_DONE