1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * Copyright (C) 2009-2010 by David Brownell *
13 * Copyright (C) 2013 by Andreas Fritiofson *
14 * andreas.fritiofson@gmail.com *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published by *
18 * the Free Software Foundation; either version 2 of the License, or *
19 * (at your option) any later version. *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
26 * You should have received a copy of the GNU General Public License *
27 * along with this program; if not, write to the *
28 * Free Software Foundation, Inc., *
29 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
30 ***************************************************************************/
34 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
35 * debugging architecture. Compared with previous versions, this includes
36 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
37 * transport, and focusses on memory mapped resources as defined by the
38 * CoreSight architecture.
40 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
41 * basic components: a Debug Port (DP) transporting messages to and from a
42 * debugger, and an Access Port (AP) accessing resources. Three types of DP
43 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
44 * One uses only SWD for communication, and is called SW-DP. The third can
45 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
46 * is used to access memory mapped resources and is called a MEM-AP. Also a
47 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
49 * This programming interface allows DAP pipelined operations through a
50 * transaction queue. This primarily affects AP operations (such as using
51 * a MEM-AP to access memory or registers). If the current transaction has
52 * not finished by the time the next one must begin, and the ORUNDETECT bit
53 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
54 * further AP operations will fail. There are two basic methods to avoid
55 * such overrun errors. One involves polling for status instead of using
56 * transaction piplining. The other involves adding delays to ensure the
57 * AP has enough time to complete one operation before starting the next
58 * one. (For JTAG these delays are controlled by memaccess_tck.)
62 * Relevant specifications from ARM include:
64 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
65 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
67 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
68 * Cortex-M3(tm) TRM, ARM DDI 0337G
75 #include "jtag/interface.h"
77 #include "arm_adi_v5.h"
78 #include <helper/jep106.h>
79 #include <helper/time_support.h>
80 #include <helper/list.h>
82 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
85 uint32_t tar_block_size(uint32_t address)
86 Return the largest block starting at address that does not cross a tar block size alignment boundary
88 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
90 return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
93 /***************************************************************************
95 * DP and MEM-AP register access through APACC and DPACC *
97 ***************************************************************************/
99 static int mem_ap_setup_csw(struct adiv5_ap *ap, uint32_t csw)
101 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT |
104 if (csw != ap->csw_value) {
105 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
106 int retval = dap_queue_ap_write(ap, MEM_AP_REG_CSW, csw);
107 if (retval != ERROR_OK)
114 static int mem_ap_setup_tar(struct adiv5_ap *ap, uint32_t tar)
116 if (tar != ap->tar_value ||
117 (ap->csw_value & CSW_ADDRINC_MASK)) {
118 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
119 int retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR, tar);
120 if (retval != ERROR_OK)
128 * Queue transactions setting up transfer parameters for the
129 * currently selected MEM-AP.
131 * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2
132 * initiate data reads or writes using memory or peripheral addresses.
133 * If the CSW is configured for it, the TAR may be automatically
134 * incremented after each transfer.
136 * @param ap The MEM-AP.
137 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
138 * matches the cached value, the register is not changed.
139 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
140 * matches the cached address, the register is not changed.
142 * @return ERROR_OK if the transaction was properly queued, else a fault code.
144 static int mem_ap_setup_transfer(struct adiv5_ap *ap, uint32_t csw, uint32_t tar)
147 retval = mem_ap_setup_csw(ap, csw);
148 if (retval != ERROR_OK)
150 retval = mem_ap_setup_tar(ap, tar);
151 if (retval != ERROR_OK)
157 * Asynchronous (queued) read of a word from memory or a system register.
159 * @param ap The MEM-AP to access.
160 * @param address Address of the 32-bit word to read; it must be
161 * readable by the currently selected MEM-AP.
162 * @param value points to where the word will be stored when the
163 * transaction queue is flushed (assuming no errors).
165 * @return ERROR_OK for success. Otherwise a fault code.
167 int mem_ap_read_u32(struct adiv5_ap *ap, uint32_t address,
172 /* Use banked addressing (REG_BDx) to avoid some link traffic
173 * (updating TAR) when reading several consecutive addresses.
175 retval = mem_ap_setup_transfer(ap, CSW_32BIT | CSW_ADDRINC_OFF,
176 address & 0xFFFFFFF0);
177 if (retval != ERROR_OK)
180 return dap_queue_ap_read(ap, MEM_AP_REG_BD0 | (address & 0xC), value);
184 * Synchronous read of a word from memory or a system register.
185 * As a side effect, this flushes any queued transactions.
187 * @param ap The MEM-AP to access.
188 * @param address Address of the 32-bit word to read; it must be
189 * readable by the currently selected MEM-AP.
190 * @param value points to where the result will be stored.
192 * @return ERROR_OK for success; *value holds the result.
193 * Otherwise a fault code.
195 int mem_ap_read_atomic_u32(struct adiv5_ap *ap, uint32_t address,
200 retval = mem_ap_read_u32(ap, address, value);
201 if (retval != ERROR_OK)
204 return dap_run(ap->dap);
208 * Asynchronous (queued) write of a word to memory or a system register.
210 * @param ap The MEM-AP to access.
211 * @param address Address to be written; it must be writable by
212 * the currently selected MEM-AP.
213 * @param value Word that will be written to the address when transaction
214 * queue is flushed (assuming no errors).
216 * @return ERROR_OK for success. Otherwise a fault code.
218 int mem_ap_write_u32(struct adiv5_ap *ap, uint32_t address,
223 /* Use banked addressing (REG_BDx) to avoid some link traffic
224 * (updating TAR) when writing several consecutive addresses.
226 retval = mem_ap_setup_transfer(ap, CSW_32BIT | CSW_ADDRINC_OFF,
227 address & 0xFFFFFFF0);
228 if (retval != ERROR_OK)
231 return dap_queue_ap_write(ap, MEM_AP_REG_BD0 | (address & 0xC),
236 * Synchronous write of a word to memory or a system register.
237 * As a side effect, this flushes any queued transactions.
239 * @param ap The MEM-AP to access.
240 * @param address Address to be written; it must be writable by
241 * the currently selected MEM-AP.
242 * @param value Word that will be written.
244 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
246 int mem_ap_write_atomic_u32(struct adiv5_ap *ap, uint32_t address,
249 int retval = mem_ap_write_u32(ap, address, value);
251 if (retval != ERROR_OK)
254 return dap_run(ap->dap);
258 * Synchronous write of a block of memory, using a specific access size.
260 * @param ap The MEM-AP to access.
261 * @param buffer The data buffer to write. No particular alignment is assumed.
262 * @param size Which access size to use, in bytes. 1, 2 or 4.
263 * @param count The number of writes to do (in size units, not bytes).
264 * @param address Address to be written; it must be writable by the currently selected MEM-AP.
265 * @param addrinc Whether the target address should be increased for each write or not. This
266 * should normally be true, except when writing to e.g. a FIFO.
267 * @return ERROR_OK on success, otherwise an error code.
269 static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count,
270 uint32_t address, bool addrinc)
272 struct adiv5_dap *dap = ap->dap;
273 size_t nbytes = size * count;
274 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
279 /* TI BE-32 Quirks mode:
280 * Writes on big-endian TMS570 behave very strangely. Observed behavior:
281 * size write address bytes written in order
282 * 4 TAR ^ 0 (val >> 24), (val >> 16), (val >> 8), (val)
283 * 2 TAR ^ 2 (val >> 8), (val)
285 * For example, if you attempt to write a single byte to address 0, the processor
286 * will actually write a byte to address 3.
288 * To make writes of size < 4 work as expected, we xor a value with the address before
289 * setting the TAP, and we set the TAP after every transfer rather then relying on
290 * address increment. */
293 csw_size = CSW_32BIT;
295 } else if (size == 2) {
296 csw_size = CSW_16BIT;
297 addr_xor = dap->ti_be_32_quirks ? 2 : 0;
298 } else if (size == 1) {
300 addr_xor = dap->ti_be_32_quirks ? 3 : 0;
302 return ERROR_TARGET_UNALIGNED_ACCESS;
305 if (ap->unaligned_access_bad && (address % size != 0))
306 return ERROR_TARGET_UNALIGNED_ACCESS;
308 retval = mem_ap_setup_tar(ap, address ^ addr_xor);
309 if (retval != ERROR_OK)
313 uint32_t this_size = size;
315 /* Select packed transfer if possible */
316 if (addrinc && ap->packed_transfers && nbytes >= 4
317 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
319 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
321 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
324 if (retval != ERROR_OK)
327 /* How many source bytes each transfer will consume, and their location in the DRW,
328 * depends on the type of transfer and alignment. See ARM document IHI0031C. */
329 uint32_t outvalue = 0;
330 if (dap->ti_be_32_quirks) {
333 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
334 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
335 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
336 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
339 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
340 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
343 outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (address++ & 3) ^ addr_xor);
349 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
350 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
352 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
354 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
360 retval = dap_queue_ap_write(ap, MEM_AP_REG_DRW, outvalue);
361 if (retval != ERROR_OK)
364 /* Rewrite TAR if it wrapped or we're xoring addresses */
365 if (addrinc && (addr_xor || (address % ap->tar_autoincr_block < size && nbytes > 0))) {
366 retval = mem_ap_setup_tar(ap, address ^ addr_xor);
367 if (retval != ERROR_OK)
372 /* REVISIT: Might want to have a queued version of this function that does not run. */
373 if (retval == ERROR_OK)
374 retval = dap_run(dap);
376 if (retval != ERROR_OK) {
378 if (dap_queue_ap_read(ap, MEM_AP_REG_TAR, &tar) == ERROR_OK
379 && dap_run(dap) == ERROR_OK)
380 LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
382 LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
389 * Synchronous read of a block of memory, using a specific access size.
391 * @param ap The MEM-AP to access.
392 * @param buffer The data buffer to receive the data. No particular alignment is assumed.
393 * @param size Which access size to use, in bytes. 1, 2 or 4.
394 * @param count The number of reads to do (in size units, not bytes).
395 * @param address Address to be read; it must be readable by the currently selected MEM-AP.
396 * @param addrinc Whether the target address should be increased after each read or not. This
397 * should normally be true, except when reading from e.g. a FIFO.
398 * @return ERROR_OK on success, otherwise an error code.
400 static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count,
401 uint32_t adr, bool addrinc)
403 struct adiv5_dap *dap = ap->dap;
404 size_t nbytes = size * count;
405 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
407 uint32_t address = adr;
410 /* TI BE-32 Quirks mode:
411 * Reads on big-endian TMS570 behave strangely differently than writes.
412 * They read from the physical address requested, but with DRW byte-reversed.
413 * For example, a byte read from address 0 will place the result in the high bytes of DRW.
414 * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
418 csw_size = CSW_32BIT;
420 csw_size = CSW_16BIT;
424 return ERROR_TARGET_UNALIGNED_ACCESS;
426 if (ap->unaligned_access_bad && (adr % size != 0))
427 return ERROR_TARGET_UNALIGNED_ACCESS;
429 /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
430 * over-allocation if packed transfers are going to be used, but determining the real need at
431 * this point would be messy. */
432 uint32_t *read_buf = malloc(count * sizeof(uint32_t));
433 uint32_t *read_ptr = read_buf;
434 if (read_buf == NULL) {
435 LOG_ERROR("Failed to allocate read buffer");
439 retval = mem_ap_setup_tar(ap, address);
440 if (retval != ERROR_OK) {
445 /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
446 * useful bytes it contains, and their location in the word, depends on the type of transfer
449 uint32_t this_size = size;
451 /* Select packed transfer if possible */
452 if (addrinc && ap->packed_transfers && nbytes >= 4
453 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
455 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
457 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
459 if (retval != ERROR_OK)
462 retval = dap_queue_ap_read(ap, MEM_AP_REG_DRW, read_ptr++);
463 if (retval != ERROR_OK)
467 address += this_size;
469 /* Rewrite TAR if it wrapped */
470 if (addrinc && address % ap->tar_autoincr_block < size && nbytes > 0) {
471 retval = mem_ap_setup_tar(ap, address);
472 if (retval != ERROR_OK)
477 if (retval == ERROR_OK)
478 retval = dap_run(dap);
482 nbytes = size * count;
485 /* If something failed, read TAR to find out how much data was successfully read, so we can
486 * at least give the caller what we have. */
487 if (retval != ERROR_OK) {
489 if (dap_queue_ap_read(ap, MEM_AP_REG_TAR, &tar) == ERROR_OK
490 && dap_run(dap) == ERROR_OK) {
491 LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
492 if (nbytes > tar - address)
493 nbytes = tar - address;
495 LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
500 /* Replay loop to populate caller's buffer from the correct word and byte lane */
502 uint32_t this_size = size;
504 if (addrinc && ap->packed_transfers && nbytes >= 4
505 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
509 if (dap->ti_be_32_quirks) {
512 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
513 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
515 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
517 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
522 *buffer++ = *read_ptr >> 8 * (address++ & 3);
523 *buffer++ = *read_ptr >> 8 * (address++ & 3);
525 *buffer++ = *read_ptr >> 8 * (address++ & 3);
527 *buffer++ = *read_ptr >> 8 * (address++ & 3);
539 int mem_ap_read_buf(struct adiv5_ap *ap,
540 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
542 return mem_ap_read(ap, buffer, size, count, address, true);
545 int mem_ap_write_buf(struct adiv5_ap *ap,
546 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
548 return mem_ap_write(ap, buffer, size, count, address, true);
551 int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
552 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
554 return mem_ap_read(ap, buffer, size, count, address, false);
557 int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
558 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
560 return mem_ap_write(ap, buffer, size, count, address, false);
563 /*--------------------------------------------------------------------------*/
566 #define DAP_POWER_DOMAIN_TIMEOUT (10)
568 /* FIXME don't import ... just initialize as
569 * part of DAP transport setup
571 extern const struct dap_ops jtag_dp_ops;
573 /*--------------------------------------------------------------------------*/
578 struct adiv5_dap *dap_init(void)
580 struct adiv5_dap *dap = calloc(1, sizeof(struct adiv5_dap));
582 /* Set up with safe defaults */
583 for (i = 0; i <= 255; i++) {
584 dap->ap[i].dap = dap;
585 dap->ap[i].ap_num = i;
586 /* memaccess_tck max is 255 */
587 dap->ap[i].memaccess_tck = 255;
588 /* Number of bits for tar autoincrement, impl. dep. at least 10 */
589 dap->ap[i].tar_autoincr_block = (1<<10);
591 INIT_LIST_HEAD(&dap->cmd_journal);
596 * Initialize a DAP. This sets up the power domains, prepares the DP
597 * for further use and activates overrun checking.
599 * @param dap The DAP being initialized.
601 int dap_dp_init(struct adiv5_dap *dap)
606 /* JTAG-DP or SWJ-DP, in JTAG mode
607 * ... for SWD mode this is patched as part
609 * FIXME: This should already be setup by the respective transport specific DAP creation.
612 dap->ops = &jtag_dp_ops;
614 dap->select = DP_SELECT_INVALID;
615 dap->last_read = NULL;
617 for (size_t i = 0; i < 10; i++) {
618 /* DP initialization */
620 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
621 if (retval != ERROR_OK)
624 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
625 if (retval != ERROR_OK)
628 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
629 if (retval != ERROR_OK)
632 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
633 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
634 if (retval != ERROR_OK)
637 /* Check that we have debug power domains activated */
638 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
639 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
640 CDBGPWRUPACK, CDBGPWRUPACK,
641 DAP_POWER_DOMAIN_TIMEOUT);
642 if (retval != ERROR_OK)
645 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
646 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
647 CSYSPWRUPACK, CSYSPWRUPACK,
648 DAP_POWER_DOMAIN_TIMEOUT);
649 if (retval != ERROR_OK)
652 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
653 if (retval != ERROR_OK)
656 /* With debug power on we can activate OVERRUN checking */
657 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
658 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
659 if (retval != ERROR_OK)
661 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
662 if (retval != ERROR_OK)
665 retval = dap_run(dap);
666 if (retval != ERROR_OK)
676 * Initialize a DAP. This sets up the power domains, prepares the DP
677 * for further use, and arranges to use AP #0 for all AP operations
678 * until dap_ap-select() changes that policy.
680 * @param ap The MEM-AP being initialized.
682 int mem_ap_init(struct adiv5_ap *ap)
684 /* check that we support packed transfers */
687 struct adiv5_dap *dap = ap->dap;
689 retval = mem_ap_setup_transfer(ap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
690 if (retval != ERROR_OK)
693 retval = dap_queue_ap_read(ap, MEM_AP_REG_CSW, &csw);
694 if (retval != ERROR_OK)
697 retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &cfg);
698 if (retval != ERROR_OK)
701 retval = dap_run(dap);
702 if (retval != ERROR_OK)
705 if (csw & CSW_ADDRINC_PACKED)
706 ap->packed_transfers = true;
708 ap->packed_transfers = false;
710 /* Packed transfers on TI BE-32 processors do not work correctly in
712 if (dap->ti_be_32_quirks)
713 ap->packed_transfers = false;
715 LOG_DEBUG("MEM_AP Packed Transfers: %s",
716 ap->packed_transfers ? "enabled" : "disabled");
718 /* The ARM ADI spec leaves implementation-defined whether unaligned
719 * memory accesses work, only work partially, or cause a sticky error.
720 * On TI BE-32 processors, reads seem to return garbage in some bytes
721 * and unaligned writes seem to cause a sticky error.
722 * TODO: it would be nice to have a way to detect whether unaligned
723 * operations are supported on other processors. */
724 ap->unaligned_access_bad = dap->ti_be_32_quirks;
726 LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
727 !!(cfg & 0x04), !!(cfg & 0x02), !!(cfg & 0x01));
732 /* CID interpretation -- see ARM IHI 0029B section 3
733 * and ARM IHI 0031A table 13-3.
735 static const char *class_description[16] = {
736 "Reserved", "ROM table", "Reserved", "Reserved",
737 "Reserved", "Reserved", "Reserved", "Reserved",
738 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
739 "Reserved", "OptimoDE DESS",
740 "Generic IP component", "PrimeCell or System component"
743 static bool is_dap_cid_ok(uint32_t cid)
745 return (cid & 0xffff0fff) == 0xb105000d;
749 * This function checks the ID for each access port to find the requested Access Port type
751 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out)
755 /* Maximum AP number is 255 since the SELECT register is 8 bits */
756 for (ap_num = 0; ap_num <= 255; ap_num++) {
758 /* read the IDR register of the Access Port */
761 int retval = dap_queue_ap_read(dap_ap(dap, ap_num), AP_REG_IDR, &id_val);
762 if (retval != ERROR_OK)
765 retval = dap_run(dap);
769 * 27-24 : JEDEC bank (0x4 for ARM)
770 * 23-17 : JEDEC code (0x3B for ARM)
771 * 16-13 : Class (0b1000=Mem-AP)
773 * 7-4 : AP Variant (non-zero for JTAG-AP)
774 * 3-0 : AP Type (0=JTAG-AP 1=AHB-AP 2=APB-AP 4=AXI-AP)
777 /* Reading register for a non-existant AP should not cause an error,
778 * but just to be sure, try to continue searching if an error does happen.
780 if ((retval == ERROR_OK) && /* Register read success */
781 ((id_val & IDR_JEP106) == IDR_JEP106_ARM) && /* Jedec codes match */
782 ((id_val & IDR_TYPE) == type_to_find)) { /* type matches*/
784 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
785 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
786 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
787 (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
788 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
791 *ap_out = &dap->ap[ap_num];
796 LOG_DEBUG("No %s found",
797 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
798 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
799 (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
800 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
804 int dap_get_debugbase(struct adiv5_ap *ap,
805 uint32_t *dbgbase, uint32_t *apid)
807 struct adiv5_dap *dap = ap->dap;
810 retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE, dbgbase);
811 if (retval != ERROR_OK)
813 retval = dap_queue_ap_read(ap, AP_REG_IDR, apid);
814 if (retval != ERROR_OK)
816 retval = dap_run(dap);
817 if (retval != ERROR_OK)
823 int dap_lookup_cs_component(struct adiv5_ap *ap,
824 uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx)
826 uint32_t romentry, entry_offset = 0, component_base, devtype;
832 retval = mem_ap_read_atomic_u32(ap, (dbgbase&0xFFFFF000) |
833 entry_offset, &romentry);
834 if (retval != ERROR_OK)
837 component_base = (dbgbase & 0xFFFFF000)
838 + (romentry & 0xFFFFF000);
840 if (romentry & 0x1) {
842 retval = mem_ap_read_atomic_u32(ap, component_base | 0xff4, &c_cid1);
843 if (retval != ERROR_OK) {
844 LOG_ERROR("Can't read component with base address 0x%" PRIx32
845 ", the corresponding core might be turned off", component_base);
848 if (((c_cid1 >> 4) & 0x0f) == 1) {
849 retval = dap_lookup_cs_component(ap, component_base,
851 if (retval == ERROR_OK)
853 if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
857 retval = mem_ap_read_atomic_u32(ap,
858 (component_base & 0xfffff000) | 0xfcc,
860 if (retval != ERROR_OK)
862 if ((devtype & 0xff) == type) {
864 *addr = component_base;
871 } while (romentry > 0);
874 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
879 static int dap_read_part_id(struct adiv5_ap *ap, uint32_t component_base, uint32_t *cid, uint64_t *pid)
881 assert((component_base & 0xFFF) == 0);
882 assert(ap != NULL && cid != NULL && pid != NULL);
884 uint32_t cid0, cid1, cid2, cid3;
885 uint32_t pid0, pid1, pid2, pid3, pid4;
888 /* IDs are in last 4K section */
889 retval = mem_ap_read_u32(ap, component_base + 0xFE0, &pid0);
890 if (retval != ERROR_OK)
892 retval = mem_ap_read_u32(ap, component_base + 0xFE4, &pid1);
893 if (retval != ERROR_OK)
895 retval = mem_ap_read_u32(ap, component_base + 0xFE8, &pid2);
896 if (retval != ERROR_OK)
898 retval = mem_ap_read_u32(ap, component_base + 0xFEC, &pid3);
899 if (retval != ERROR_OK)
901 retval = mem_ap_read_u32(ap, component_base + 0xFD0, &pid4);
902 if (retval != ERROR_OK)
904 retval = mem_ap_read_u32(ap, component_base + 0xFF0, &cid0);
905 if (retval != ERROR_OK)
907 retval = mem_ap_read_u32(ap, component_base + 0xFF4, &cid1);
908 if (retval != ERROR_OK)
910 retval = mem_ap_read_u32(ap, component_base + 0xFF8, &cid2);
911 if (retval != ERROR_OK)
913 retval = mem_ap_read_u32(ap, component_base + 0xFFC, &cid3);
914 if (retval != ERROR_OK)
917 retval = dap_run(ap->dap);
918 if (retval != ERROR_OK)
921 *cid = (cid3 & 0xff) << 24
922 | (cid2 & 0xff) << 16
925 *pid = (uint64_t)(pid4 & 0xff) << 32
926 | (pid3 & 0xff) << 24
927 | (pid2 & 0xff) << 16
934 /* The designer identity code is encoded as:
935 * bits 11:8 : JEP106 Bank (number of continuation codes), only valid when bit 7 is 1.
936 * bit 7 : Set when bits 6:0 represent a JEP106 ID and cleared when bits 6:0 represent
937 * a legacy ASCII Identity Code.
938 * bits 6:0 : JEP106 Identity Code (without parity) or legacy ASCII code according to bit 7.
939 * JEP106 is a standard available from jedec.org
942 /* Part number interpretations are from Cortex
943 * core specs, the CoreSight components TRM
944 * (ARM DDI 0314H), CoreSight System Design
945 * Guide (ARM DGI 0012D) and ETM specs; also
946 * from chip observation (e.g. TI SDTI).
949 /* The legacy code only used the part number field to identify CoreSight peripherals.
950 * This meant that the same part number from two different manufacturers looked the same.
951 * It is desirable for all future additions to identify with both part number and JEP106.
952 * "ANY_ID" is a wildcard (any JEP106) only to preserve legacy behavior for legacy entries.
955 #define ANY_ID 0x1000
959 static const struct {
960 uint16_t designer_id;
965 { ARM_ID, 0x000, "Cortex-M3 SCS", "(System Control Space)", },
966 { ARM_ID, 0x001, "Cortex-M3 ITM", "(Instrumentation Trace Module)", },
967 { ARM_ID, 0x002, "Cortex-M3 DWT", "(Data Watchpoint and Trace)", },
968 { ARM_ID, 0x003, "Cortex-M3 FBP", "(Flash Patch and Breakpoint)", },
969 { ARM_ID, 0x008, "Cortex-M0 SCS", "(System Control Space)", },
970 { ARM_ID, 0x00a, "Cortex-M0 DWT", "(Data Watchpoint and Trace)", },
971 { ARM_ID, 0x00b, "Cortex-M0 BPU", "(Breakpoint Unit)", },
972 { ARM_ID, 0x00c, "Cortex-M4 SCS", "(System Control Space)", },
973 { ARM_ID, 0x00d, "CoreSight ETM11", "(Embedded Trace)", },
974 { ARM_ID, 0x490, "Cortex-A15 GIC", "(Generic Interrupt Controller)", },
975 { ARM_ID, 0x4c0, "Cortex-M0+ ROM", "(ROM Table)", },
976 { ARM_ID, 0x4c7, "Cortex-M7 PPB", "(Private Peripheral Bus ROM Table)", },
977 { ARM_ID, 0x906, "CoreSight CTI", "(Cross Trigger)", },
978 { ARM_ID, 0x907, "CoreSight ETB", "(Trace Buffer)", },
979 { ARM_ID, 0x908, "CoreSight CSTF", "(Trace Funnel)", },
980 { ARM_ID, 0x910, "CoreSight ETM9", "(Embedded Trace)", },
981 { ARM_ID, 0x912, "CoreSight TPIU", "(Trace Port Interface Unit)", },
982 { ARM_ID, 0x913, "CoreSight ITM", "(Instrumentation Trace Macrocell)", },
983 { ARM_ID, 0x914, "CoreSight SWO", "(Single Wire Output)", },
984 { ARM_ID, 0x917, "CoreSight HTM", "(AHB Trace Macrocell)", },
985 { ARM_ID, 0x920, "CoreSight ETM11", "(Embedded Trace)", },
986 { ARM_ID, 0x921, "Cortex-A8 ETM", "(Embedded Trace)", },
987 { ARM_ID, 0x922, "Cortex-A8 CTI", "(Cross Trigger)", },
988 { ARM_ID, 0x923, "Cortex-M3 TPIU", "(Trace Port Interface Unit)", },
989 { ARM_ID, 0x924, "Cortex-M3 ETM", "(Embedded Trace)", },
990 { ARM_ID, 0x925, "Cortex-M4 ETM", "(Embedded Trace)", },
991 { ARM_ID, 0x930, "Cortex-R4 ETM", "(Embedded Trace)", },
992 { ARM_ID, 0x931, "Cortex-R5 ETM", "(Embedded Trace)", },
993 { ARM_ID, 0x932, "CoreSight MTB-M0+", "(Micro Trace Buffer)", },
994 { ARM_ID, 0x941, "CoreSight TPIU-Lite", "(Trace Port Interface Unit)", },
995 { ARM_ID, 0x950, "Cortex-A9 PTM", "(Program Trace Macrocell)", },
996 { ARM_ID, 0x955, "Cortex-A5 ETM", "(Embedded Trace)", },
997 { ARM_ID, 0x95a, "Cortex-A72 ETM", "(Embedded Trace)", },
998 { ARM_ID, 0x95b, "Cortex-A17 PTM", "(Program Trace Macrocell)", },
999 { ARM_ID, 0x95d, "Cortex-A53 ETM", "(Embedded Trace)", },
1000 { ARM_ID, 0x95e, "Cortex-A57 ETM", "(Embedded Trace)", },
1001 { ARM_ID, 0x95f, "Cortex-A15 PTM", "(Program Trace Macrocell)", },
1002 { ARM_ID, 0x961, "CoreSight TMC", "(Trace Memory Controller)", },
1003 { ARM_ID, 0x962, "CoreSight STM", "(System Trace Macrocell)", },
1004 { ARM_ID, 0x9a0, "CoreSight PMU", "(Performance Monitoring Unit)", },
1005 { ARM_ID, 0x9a1, "Cortex-M4 TPIU", "(Trace Port Interface Unit)", },
1006 { ARM_ID, 0x9a5, "Cortex-A5 PMU", "(Performance Monitor Unit)", },
1007 { ARM_ID, 0x9a7, "Cortex-A7 PMU", "(Performance Monitor Unit)", },
1008 { ARM_ID, 0x9a8, "Cortex-A53 CTI", "(Cross Trigger)", },
1009 { ARM_ID, 0x9ae, "Cortex-A17 PMU", "(Performance Monitor Unit)", },
1010 { ARM_ID, 0x9af, "Cortex-A15 PMU", "(Performance Monitor Unit)", },
1011 { ARM_ID, 0x9b7, "Cortex-R7 PMU", "(Performance Monitoring Unit)", },
1012 { ARM_ID, 0x9d3, "Cortex-A53 PMU", "(Performance Monitor Unit)", },
1013 { ARM_ID, 0x9d7, "Cortex-A57 PMU", "(Performance Monitor Unit)", },
1014 { ARM_ID, 0x9d8, "Cortex-A72 PMU", "(Performance Monitor Unit)", },
1015 { ARM_ID, 0xc05, "Cortex-A5 Debug", "(Debug Unit)", },
1016 { ARM_ID, 0xc07, "Cortex-A7 Debug", "(Debug Unit)", },
1017 { ARM_ID, 0xc08, "Cortex-A8 Debug", "(Debug Unit)", },
1018 { ARM_ID, 0xc09, "Cortex-A9 Debug", "(Debug Unit)", },
1019 { ARM_ID, 0xc0e, "Cortex-A17 Debug", "(Debug Unit)", },
1020 { ARM_ID, 0xc0f, "Cortex-A15 Debug", "(Debug Unit)", },
1021 { ARM_ID, 0xc14, "Cortex-R4 Debug", "(Debug Unit)", },
1022 { ARM_ID, 0xc15, "Cortex-R5 Debug", "(Debug Unit)", },
1023 { ARM_ID, 0xc17, "Cortex-R7 Debug", "(Debug Unit)", },
1024 { ARM_ID, 0xd03, "Cortex-A53 Debug", "(Debug Unit)", },
1025 { ARM_ID, 0xd07, "Cortex-A57 Debug", "(Debug Unit)", },
1026 { ARM_ID, 0xd08, "Cortex-A72 Debug", "(Debug Unit)", },
1027 { 0x0E5, 0x000, "SHARC+/Blackfin+", "", },
1028 /* legacy comment: 0x113: what? */
1029 { ANY_ID, 0x120, "TI SDTI", "(System Debug Trace Interface)", }, /* from OMAP3 memmap */
1030 { ANY_ID, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */
1032 { 0x09f, 0xcd0, "Atmel CPU with DSU", "(CPU)" },
1035 static int dap_rom_display(struct command_context *cmd_ctx,
1036 struct adiv5_ap *ap, uint32_t dbgbase, int depth)
1044 command_print(cmd_ctx, "\tTables too deep");
1049 snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
1051 uint32_t base_addr = dbgbase & 0xFFFFF000;
1052 command_print(cmd_ctx, "\t\tComponent base address 0x%08" PRIx32, base_addr);
1054 retval = dap_read_part_id(ap, base_addr, &cid, &pid);
1055 if (retval != ERROR_OK) {
1056 command_print(cmd_ctx, "\t\tCan't read component, the corresponding core might be turned off");
1057 return ERROR_OK; /* Don't abort recursion */
1060 if (!is_dap_cid_ok(cid)) {
1061 command_print(cmd_ctx, "\t\tInvalid CID 0x%08" PRIx32, cid);
1062 return ERROR_OK; /* Don't abort recursion */
1065 /* component may take multiple 4K pages */
1066 uint32_t size = (pid >> 36) & 0xf;
1068 command_print(cmd_ctx, "\t\tStart address 0x%08" PRIx32, (uint32_t)(base_addr - 0x1000 * size));
1070 command_print(cmd_ctx, "\t\tPeripheral ID 0x%010" PRIx64, pid);
1072 uint8_t class = (cid >> 12) & 0xf;
1073 uint16_t part_num = pid & 0xfff;
1074 uint16_t designer_id = ((pid >> 32) & 0xf) << 8 | ((pid >> 12) & 0xff);
1076 if (designer_id & 0x80) {
1078 command_print(cmd_ctx, "\t\tDesigner is 0x%03" PRIx16 ", %s",
1079 designer_id, jep106_manufacturer(designer_id >> 8, designer_id & 0x7f));
1081 /* Legacy ASCII ID, clear invalid bits */
1082 designer_id &= 0x7f;
1083 command_print(cmd_ctx, "\t\tDesigner ASCII code 0x%02" PRIx16 ", %s",
1084 designer_id, designer_id == 0x41 ? "ARM" : "<unknown>");
1087 /* default values to be overwritten upon finding a match */
1088 const char *type = "Unrecognized";
1089 const char *full = "";
1091 /* search dap_partnums[] array for a match */
1092 for (unsigned entry = 0; entry < ARRAY_SIZE(dap_partnums); entry++) {
1094 if ((dap_partnums[entry].designer_id != designer_id) && (dap_partnums[entry].designer_id != ANY_ID))
1097 if (dap_partnums[entry].part_num != part_num)
1100 type = dap_partnums[entry].type;
1101 full = dap_partnums[entry].full;
1105 command_print(cmd_ctx, "\t\tPart is 0x%" PRIx16", %s %s", part_num, type, full);
1106 command_print(cmd_ctx, "\t\tComponent class is 0x%" PRIx8 ", %s", class, class_description[class]);
1108 if (class == 1) { /* ROM Table */
1110 retval = mem_ap_read_atomic_u32(ap, base_addr | 0xFCC, &memtype);
1111 if (retval != ERROR_OK)
1115 command_print(cmd_ctx, "\t\tMEMTYPE system memory present on bus");
1117 command_print(cmd_ctx, "\t\tMEMTYPE system memory not present: dedicated debug bus");
1119 /* Read ROM table entries from base address until we get 0x00000000 or reach the reserved area */
1120 for (uint16_t entry_offset = 0; entry_offset < 0xF00; entry_offset += 4) {
1122 retval = mem_ap_read_atomic_u32(ap, base_addr | entry_offset, &romentry);
1123 if (retval != ERROR_OK)
1125 command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
1126 tabs, entry_offset, romentry);
1127 if (romentry & 0x01) {
1129 retval = dap_rom_display(cmd_ctx, ap, base_addr + (romentry & 0xFFFFF000), depth + 1);
1130 if (retval != ERROR_OK)
1132 } else if (romentry != 0) {
1133 command_print(cmd_ctx, "\t\tComponent not present");
1135 command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs);
1139 } else if (class == 9) { /* CoreSight component */
1140 const char *major = "Reserved", *subtype = "Reserved";
1143 retval = mem_ap_read_atomic_u32(ap, base_addr | 0xFCC, &devtype);
1144 if (retval != ERROR_OK)
1146 unsigned minor = (devtype >> 4) & 0x0f;
1147 switch (devtype & 0x0f) {
1149 major = "Miscellaneous";
1155 subtype = "Validation component";
1160 major = "Trace Sink";
1177 major = "Trace Link";
1183 subtype = "Funnel, router";
1189 subtype = "FIFO, buffer";
1194 major = "Trace Source";
1200 subtype = "Processor";
1206 subtype = "Engine/Coprocessor";
1212 subtype = "Software";
1217 major = "Debug Control";
1223 subtype = "Trigger Matrix";
1226 subtype = "Debug Auth";
1229 subtype = "Power Requestor";
1234 major = "Debug Logic";
1240 subtype = "Processor";
1246 subtype = "Engine/Coprocessor";
1257 major = "Perfomance Monitor";
1263 subtype = "Processor";
1269 subtype = "Engine/Coprocessor";
1280 command_print(cmd_ctx, "\t\tType is 0x%02" PRIx8 ", %s, %s",
1281 (uint8_t)(devtype & 0xff),
1283 /* REVISIT also show 0xfc8 DevId */
1289 static int dap_info_command(struct command_context *cmd_ctx,
1290 struct adiv5_ap *ap)
1293 uint32_t dbgbase, apid;
1296 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1297 retval = dap_get_debugbase(ap, &dbgbase, &apid);
1298 if (retval != ERROR_OK)
1301 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1303 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap->ap_num);
1307 switch (apid & (IDR_JEP106 | IDR_TYPE)) {
1308 case IDR_JEP106_ARM | AP_TYPE_JTAG_AP:
1309 command_print(cmd_ctx, "\tType is JTAG-AP");
1311 case IDR_JEP106_ARM | AP_TYPE_AHB_AP:
1312 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1314 case IDR_JEP106_ARM | AP_TYPE_APB_AP:
1315 command_print(cmd_ctx, "\tType is MEM-AP APB");
1317 case IDR_JEP106_ARM | AP_TYPE_AXI_AP:
1318 command_print(cmd_ctx, "\tType is MEM-AP AXI");
1321 command_print(cmd_ctx, "\tUnknown AP type");
1325 /* NOTE: a MEM-AP may have a single CoreSight component that's
1326 * not a ROM table ... or have no such components at all.
1328 mem_ap = (apid & IDR_CLASS) == AP_CLASS_MEM_AP;
1330 command_print(cmd_ctx, "MEM-AP BASE 0x%8.8" PRIx32, dbgbase);
1332 if (dbgbase == 0xFFFFFFFF || (dbgbase & 0x3) == 0x2) {
1333 command_print(cmd_ctx, "\tNo ROM table present");
1336 command_print(cmd_ctx, "\tValid ROM table present");
1338 command_print(cmd_ctx, "\tROM table in legacy format");
1340 dap_rom_display(cmd_ctx, ap, dbgbase & 0xFFFFF000, 0);
1347 COMMAND_HANDLER(handle_dap_info_command)
1349 struct target *target = get_current_target(CMD_CTX);
1350 struct arm *arm = target_to_arm(target);
1351 struct adiv5_dap *dap = arm->dap;
1359 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1361 return ERROR_COMMAND_SYNTAX_ERROR;
1364 return ERROR_COMMAND_SYNTAX_ERROR;
1367 return dap_info_command(CMD_CTX, &dap->ap[apsel]);
1370 COMMAND_HANDLER(dap_baseaddr_command)
1372 struct target *target = get_current_target(CMD_CTX);
1373 struct arm *arm = target_to_arm(target);
1374 struct adiv5_dap *dap = arm->dap;
1376 uint32_t apsel, baseaddr;
1384 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1385 /* AP address is in bits 31:24 of DP_SELECT */
1387 return ERROR_COMMAND_SYNTAX_ERROR;
1390 return ERROR_COMMAND_SYNTAX_ERROR;
1393 /* NOTE: assumes we're talking to a MEM-AP, which
1394 * has a base address. There are other kinds of AP,
1395 * though they're not common for now. This should
1396 * use the ID register to verify it's a MEM-AP.
1398 retval = dap_queue_ap_read(dap_ap(dap, apsel), MEM_AP_REG_BASE, &baseaddr);
1399 if (retval != ERROR_OK)
1401 retval = dap_run(dap);
1402 if (retval != ERROR_OK)
1405 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1410 COMMAND_HANDLER(dap_memaccess_command)
1412 struct target *target = get_current_target(CMD_CTX);
1413 struct arm *arm = target_to_arm(target);
1414 struct adiv5_dap *dap = arm->dap;
1416 uint32_t memaccess_tck;
1420 memaccess_tck = dap->ap[dap->apsel].memaccess_tck;
1423 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1426 return ERROR_COMMAND_SYNTAX_ERROR;
1428 dap->ap[dap->apsel].memaccess_tck = memaccess_tck;
1430 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1431 dap->ap[dap->apsel].memaccess_tck);
1436 COMMAND_HANDLER(dap_apsel_command)
1438 struct target *target = get_current_target(CMD_CTX);
1439 struct arm *arm = target_to_arm(target);
1440 struct adiv5_dap *dap = arm->dap;
1442 uint32_t apsel, apid;
1450 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1451 /* AP address is in bits 31:24 of DP_SELECT */
1453 return ERROR_COMMAND_SYNTAX_ERROR;
1456 return ERROR_COMMAND_SYNTAX_ERROR;
1461 retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid);
1462 if (retval != ERROR_OK)
1464 retval = dap_run(dap);
1465 if (retval != ERROR_OK)
1468 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1474 COMMAND_HANDLER(dap_apcsw_command)
1476 struct target *target = get_current_target(CMD_CTX);
1477 struct arm *arm = target_to_arm(target);
1478 struct adiv5_dap *dap = arm->dap;
1480 uint32_t apcsw = dap->ap[dap->apsel].csw_default, sprot = 0;
1484 command_print(CMD_CTX, "apsel %" PRIi32 " selected, csw 0x%8.8" PRIx32,
1485 (dap->apsel), apcsw);
1488 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], sprot);
1489 /* AP address is in bits 31:24 of DP_SELECT */
1491 return ERROR_COMMAND_SYNTAX_ERROR;
1495 apcsw &= ~CSW_SPROT;
1498 return ERROR_COMMAND_SYNTAX_ERROR;
1500 dap->ap[dap->apsel].csw_default = apcsw;
1507 COMMAND_HANDLER(dap_apid_command)
1509 struct target *target = get_current_target(CMD_CTX);
1510 struct arm *arm = target_to_arm(target);
1511 struct adiv5_dap *dap = arm->dap;
1513 uint32_t apsel, apid;
1521 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1522 /* AP address is in bits 31:24 of DP_SELECT */
1524 return ERROR_COMMAND_SYNTAX_ERROR;
1527 return ERROR_COMMAND_SYNTAX_ERROR;
1530 retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid);
1531 if (retval != ERROR_OK)
1533 retval = dap_run(dap);
1534 if (retval != ERROR_OK)
1537 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1542 COMMAND_HANDLER(dap_ti_be_32_quirks_command)
1544 struct target *target = get_current_target(CMD_CTX);
1545 struct arm *arm = target_to_arm(target);
1546 struct adiv5_dap *dap = arm->dap;
1548 uint32_t enable = dap->ti_be_32_quirks;
1554 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], enable);
1556 return ERROR_COMMAND_SYNTAX_ERROR;
1559 return ERROR_COMMAND_SYNTAX_ERROR;
1561 dap->ti_be_32_quirks = enable;
1562 command_print(CMD_CTX, "TI BE-32 quirks mode %s",
1563 enable ? "enabled" : "disabled");
1568 static const struct command_registration dap_commands[] = {
1571 .handler = handle_dap_info_command,
1572 .mode = COMMAND_EXEC,
1573 .help = "display ROM table for MEM-AP "
1574 "(default currently selected AP)",
1575 .usage = "[ap_num]",
1579 .handler = dap_apsel_command,
1580 .mode = COMMAND_EXEC,
1581 .help = "Set the currently selected AP (default 0) "
1582 "and display the result",
1583 .usage = "[ap_num]",
1587 .handler = dap_apcsw_command,
1588 .mode = COMMAND_EXEC,
1589 .help = "Set csw access bit ",
1595 .handler = dap_apid_command,
1596 .mode = COMMAND_EXEC,
1597 .help = "return ID register from AP "
1598 "(default currently selected AP)",
1599 .usage = "[ap_num]",
1603 .handler = dap_baseaddr_command,
1604 .mode = COMMAND_EXEC,
1605 .help = "return debug base address from MEM-AP "
1606 "(default currently selected AP)",
1607 .usage = "[ap_num]",
1610 .name = "memaccess",
1611 .handler = dap_memaccess_command,
1612 .mode = COMMAND_EXEC,
1613 .help = "set/get number of extra tck for MEM-AP memory "
1614 "bus access [0-255]",
1615 .usage = "[cycles]",
1618 .name = "ti_be_32_quirks",
1619 .handler = dap_ti_be_32_quirks_command,
1620 .mode = COMMAND_CONFIG,
1621 .help = "set/get quirks mode for TI TMS450/TMS570 processors",
1622 .usage = "[enable]",
1624 COMMAND_REGISTRATION_DONE
1627 const struct command_registration dap_command_handlers[] = {
1630 .mode = COMMAND_EXEC,
1631 .help = "DAP command group",
1633 .chain = dap_commands,
1635 COMMAND_REGISTRATION_DONE