1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * Copyright (C) 2009-2010 by David Brownell *
13 * Copyright (C) 2013 by Andreas Fritiofson *
14 * andreas.fritiofson@gmail.com *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published by *
18 * the Free Software Foundation; either version 2 of the License, or *
19 * (at your option) any later version. *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
26 * You should have received a copy of the GNU General Public License *
27 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
28 ***************************************************************************/
32 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
33 * debugging architecture. Compared with previous versions, this includes
34 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
35 * transport, and focusses on memory mapped resources as defined by the
36 * CoreSight architecture.
38 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
39 * basic components: a Debug Port (DP) transporting messages to and from a
40 * debugger, and an Access Port (AP) accessing resources. Three types of DP
41 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
42 * One uses only SWD for communication, and is called SW-DP. The third can
43 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
44 * is used to access memory mapped resources and is called a MEM-AP. Also a
45 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
47 * This programming interface allows DAP pipelined operations through a
48 * transaction queue. This primarily affects AP operations (such as using
49 * a MEM-AP to access memory or registers). If the current transaction has
50 * not finished by the time the next one must begin, and the ORUNDETECT bit
51 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
52 * further AP operations will fail. There are two basic methods to avoid
53 * such overrun errors. One involves polling for status instead of using
54 * transaction piplining. The other involves adding delays to ensure the
55 * AP has enough time to complete one operation before starting the next
56 * one. (For JTAG these delays are controlled by memaccess_tck.)
60 * Relevant specifications from ARM include:
62 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
63 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
65 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
66 * Cortex-M3(tm) TRM, ARM DDI 0337G
73 #include "jtag/interface.h"
75 #include "arm_adi_v5.h"
76 #include <helper/jep106.h>
77 #include <helper/time_support.h>
78 #include <helper/list.h>
80 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
83 uint32_t tar_block_size(uint32_t address)
84 Return the largest block starting at address that does not cross a tar block size alignment boundary
86 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
88 return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
91 /***************************************************************************
93 * DP and MEM-AP register access through APACC and DPACC *
95 ***************************************************************************/
97 static int mem_ap_setup_csw(struct adiv5_ap *ap, uint32_t csw)
99 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT |
102 if (csw != ap->csw_value) {
103 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
104 int retval = dap_queue_ap_write(ap, MEM_AP_REG_CSW, csw);
105 if (retval != ERROR_OK)
112 static int mem_ap_setup_tar(struct adiv5_ap *ap, uint32_t tar)
114 if (!ap->tar_valid || tar != ap->tar_value) {
115 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
116 int retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR, tar);
117 if (retval != ERROR_OK)
120 ap->tar_valid = true;
125 static int mem_ap_read_tar(struct adiv5_ap *ap, uint32_t *tar)
127 int retval = dap_queue_ap_read(ap, MEM_AP_REG_TAR, tar);
128 if (retval != ERROR_OK) {
129 ap->tar_valid = false;
133 retval = dap_run(ap->dap);
134 if (retval != ERROR_OK) {
135 ap->tar_valid = false;
139 ap->tar_value = *tar;
140 ap->tar_valid = true;
144 static uint32_t mem_ap_get_tar_increment(struct adiv5_ap *ap)
146 switch (ap->csw_value & CSW_ADDRINC_MASK) {
147 case CSW_ADDRINC_SINGLE:
148 switch (ap->csw_value & CSW_SIZE_MASK) {
156 case CSW_ADDRINC_PACKED:
162 /* mem_ap_update_tar_cache is called after an access to MEM_AP_REG_DRW
164 static void mem_ap_update_tar_cache(struct adiv5_ap *ap)
169 uint32_t inc = mem_ap_get_tar_increment(ap);
170 if (inc >= max_tar_block_size(ap->tar_autoincr_block, ap->tar_value))
171 ap->tar_valid = false;
173 ap->tar_value += inc;
177 * Queue transactions setting up transfer parameters for the
178 * currently selected MEM-AP.
180 * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2
181 * initiate data reads or writes using memory or peripheral addresses.
182 * If the CSW is configured for it, the TAR may be automatically
183 * incremented after each transfer.
185 * @param ap The MEM-AP.
186 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
187 * matches the cached value, the register is not changed.
188 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
189 * matches the cached address, the register is not changed.
191 * @return ERROR_OK if the transaction was properly queued, else a fault code.
193 static int mem_ap_setup_transfer(struct adiv5_ap *ap, uint32_t csw, uint32_t tar)
196 retval = mem_ap_setup_csw(ap, csw);
197 if (retval != ERROR_OK)
199 retval = mem_ap_setup_tar(ap, tar);
200 if (retval != ERROR_OK)
206 * Asynchronous (queued) read of a word from memory or a system register.
208 * @param ap The MEM-AP to access.
209 * @param address Address of the 32-bit word to read; it must be
210 * readable by the currently selected MEM-AP.
211 * @param value points to where the word will be stored when the
212 * transaction queue is flushed (assuming no errors).
214 * @return ERROR_OK for success. Otherwise a fault code.
216 int mem_ap_read_u32(struct adiv5_ap *ap, uint32_t address,
221 /* Use banked addressing (REG_BDx) to avoid some link traffic
222 * (updating TAR) when reading several consecutive addresses.
224 retval = mem_ap_setup_transfer(ap,
225 CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK),
226 address & 0xFFFFFFF0);
227 if (retval != ERROR_OK)
230 return dap_queue_ap_read(ap, MEM_AP_REG_BD0 | (address & 0xC), value);
234 * Synchronous read of a word from memory or a system register.
235 * As a side effect, this flushes any queued transactions.
237 * @param ap The MEM-AP to access.
238 * @param address Address of the 32-bit word to read; it must be
239 * readable by the currently selected MEM-AP.
240 * @param value points to where the result will be stored.
242 * @return ERROR_OK for success; *value holds the result.
243 * Otherwise a fault code.
245 int mem_ap_read_atomic_u32(struct adiv5_ap *ap, uint32_t address,
250 retval = mem_ap_read_u32(ap, address, value);
251 if (retval != ERROR_OK)
254 return dap_run(ap->dap);
258 * Asynchronous (queued) write of a word to memory or a system register.
260 * @param ap The MEM-AP to access.
261 * @param address Address to be written; it must be writable by
262 * the currently selected MEM-AP.
263 * @param value Word that will be written to the address when transaction
264 * queue is flushed (assuming no errors).
266 * @return ERROR_OK for success. Otherwise a fault code.
268 int mem_ap_write_u32(struct adiv5_ap *ap, uint32_t address,
273 /* Use banked addressing (REG_BDx) to avoid some link traffic
274 * (updating TAR) when writing several consecutive addresses.
276 retval = mem_ap_setup_transfer(ap,
277 CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK),
278 address & 0xFFFFFFF0);
279 if (retval != ERROR_OK)
282 return dap_queue_ap_write(ap, MEM_AP_REG_BD0 | (address & 0xC),
287 * Synchronous write of a word to memory or a system register.
288 * As a side effect, this flushes any queued transactions.
290 * @param ap The MEM-AP to access.
291 * @param address Address to be written; it must be writable by
292 * the currently selected MEM-AP.
293 * @param value Word that will be written.
295 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
297 int mem_ap_write_atomic_u32(struct adiv5_ap *ap, uint32_t address,
300 int retval = mem_ap_write_u32(ap, address, value);
302 if (retval != ERROR_OK)
305 return dap_run(ap->dap);
309 * Synchronous write of a block of memory, using a specific access size.
311 * @param ap The MEM-AP to access.
312 * @param buffer The data buffer to write. No particular alignment is assumed.
313 * @param size Which access size to use, in bytes. 1, 2 or 4.
314 * @param count The number of writes to do (in size units, not bytes).
315 * @param address Address to be written; it must be writable by the currently selected MEM-AP.
316 * @param addrinc Whether the target address should be increased for each write or not. This
317 * should normally be true, except when writing to e.g. a FIFO.
318 * @return ERROR_OK on success, otherwise an error code.
320 static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count,
321 uint32_t address, bool addrinc)
323 struct adiv5_dap *dap = ap->dap;
324 size_t nbytes = size * count;
325 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
330 /* TI BE-32 Quirks mode:
331 * Writes on big-endian TMS570 behave very strangely. Observed behavior:
332 * size write address bytes written in order
333 * 4 TAR ^ 0 (val >> 24), (val >> 16), (val >> 8), (val)
334 * 2 TAR ^ 2 (val >> 8), (val)
336 * For example, if you attempt to write a single byte to address 0, the processor
337 * will actually write a byte to address 3.
339 * To make writes of size < 4 work as expected, we xor a value with the address before
340 * setting the TAP, and we set the TAP after every transfer rather then relying on
341 * address increment. */
344 csw_size = CSW_32BIT;
346 } else if (size == 2) {
347 csw_size = CSW_16BIT;
348 addr_xor = dap->ti_be_32_quirks ? 2 : 0;
349 } else if (size == 1) {
351 addr_xor = dap->ti_be_32_quirks ? 3 : 0;
353 return ERROR_TARGET_UNALIGNED_ACCESS;
356 if (ap->unaligned_access_bad && (address % size != 0))
357 return ERROR_TARGET_UNALIGNED_ACCESS;
360 uint32_t this_size = size;
362 /* Select packed transfer if possible */
363 if (addrinc && ap->packed_transfers && nbytes >= 4
364 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
366 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
368 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
371 if (retval != ERROR_OK)
374 retval = mem_ap_setup_tar(ap, address ^ addr_xor);
375 if (retval != ERROR_OK)
378 /* How many source bytes each transfer will consume, and their location in the DRW,
379 * depends on the type of transfer and alignment. See ARM document IHI0031C. */
380 uint32_t outvalue = 0;
381 uint32_t drw_byte_idx = address;
382 if (dap->ti_be_32_quirks) {
385 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
386 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
387 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
388 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx & 3) ^ addr_xor);
391 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (drw_byte_idx++ & 3) ^ addr_xor);
392 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (drw_byte_idx & 3) ^ addr_xor);
395 outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (drw_byte_idx & 3) ^ addr_xor);
401 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
402 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
405 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
408 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx & 3);
414 retval = dap_queue_ap_write(ap, MEM_AP_REG_DRW, outvalue);
415 if (retval != ERROR_OK)
418 mem_ap_update_tar_cache(ap);
420 address += this_size;
423 /* REVISIT: Might want to have a queued version of this function that does not run. */
424 if (retval == ERROR_OK)
425 retval = dap_run(dap);
427 if (retval != ERROR_OK) {
429 if (mem_ap_read_tar(ap, &tar) == ERROR_OK)
430 LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
432 LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
439 * Synchronous read of a block of memory, using a specific access size.
441 * @param ap The MEM-AP to access.
442 * @param buffer The data buffer to receive the data. No particular alignment is assumed.
443 * @param size Which access size to use, in bytes. 1, 2 or 4.
444 * @param count The number of reads to do (in size units, not bytes).
445 * @param address Address to be read; it must be readable by the currently selected MEM-AP.
446 * @param addrinc Whether the target address should be increased after each read or not. This
447 * should normally be true, except when reading from e.g. a FIFO.
448 * @return ERROR_OK on success, otherwise an error code.
450 static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count,
451 uint32_t adr, bool addrinc)
453 struct adiv5_dap *dap = ap->dap;
454 size_t nbytes = size * count;
455 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
457 uint32_t address = adr;
460 /* TI BE-32 Quirks mode:
461 * Reads on big-endian TMS570 behave strangely differently than writes.
462 * They read from the physical address requested, but with DRW byte-reversed.
463 * For example, a byte read from address 0 will place the result in the high bytes of DRW.
464 * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
468 csw_size = CSW_32BIT;
470 csw_size = CSW_16BIT;
474 return ERROR_TARGET_UNALIGNED_ACCESS;
476 if (ap->unaligned_access_bad && (adr % size != 0))
477 return ERROR_TARGET_UNALIGNED_ACCESS;
479 /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
480 * over-allocation if packed transfers are going to be used, but determining the real need at
481 * this point would be messy. */
482 uint32_t *read_buf = malloc(count * sizeof(uint32_t));
483 uint32_t *read_ptr = read_buf;
484 if (read_buf == NULL) {
485 LOG_ERROR("Failed to allocate read buffer");
489 /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
490 * useful bytes it contains, and their location in the word, depends on the type of transfer
493 uint32_t this_size = size;
495 /* Select packed transfer if possible */
496 if (addrinc && ap->packed_transfers && nbytes >= 4
497 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
499 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
501 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
503 if (retval != ERROR_OK)
506 retval = mem_ap_setup_tar(ap, address);
507 if (retval != ERROR_OK)
510 retval = dap_queue_ap_read(ap, MEM_AP_REG_DRW, read_ptr++);
511 if (retval != ERROR_OK)
516 address += this_size;
518 mem_ap_update_tar_cache(ap);
521 if (retval == ERROR_OK)
522 retval = dap_run(dap);
526 nbytes = size * count;
529 /* If something failed, read TAR to find out how much data was successfully read, so we can
530 * at least give the caller what we have. */
531 if (retval != ERROR_OK) {
533 if (mem_ap_read_tar(ap, &tar) == ERROR_OK) {
534 /* TAR is incremented after failed transfer on some devices (eg Cortex-M4) */
535 LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
536 if (nbytes > tar - address)
537 nbytes = tar - address;
539 LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
544 /* Replay loop to populate caller's buffer from the correct word and byte lane */
546 uint32_t this_size = size;
548 if (addrinc && ap->packed_transfers && nbytes >= 4
549 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
553 if (dap->ti_be_32_quirks) {
556 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
557 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
560 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
563 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
568 *buffer++ = *read_ptr >> 8 * (address++ & 3);
569 *buffer++ = *read_ptr >> 8 * (address++ & 3);
572 *buffer++ = *read_ptr >> 8 * (address++ & 3);
575 *buffer++ = *read_ptr >> 8 * (address++ & 3);
587 int mem_ap_read_buf(struct adiv5_ap *ap,
588 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
590 return mem_ap_read(ap, buffer, size, count, address, true);
593 int mem_ap_write_buf(struct adiv5_ap *ap,
594 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
596 return mem_ap_write(ap, buffer, size, count, address, true);
599 int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
600 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
602 return mem_ap_read(ap, buffer, size, count, address, false);
605 int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
606 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
608 return mem_ap_write(ap, buffer, size, count, address, false);
611 /*--------------------------------------------------------------------------*/
614 #define DAP_POWER_DOMAIN_TIMEOUT (10)
616 /* FIXME don't import ... just initialize as
617 * part of DAP transport setup
619 extern const struct dap_ops jtag_dp_ops;
621 /*--------------------------------------------------------------------------*/
626 struct adiv5_dap *dap_init(void)
628 struct adiv5_dap *dap = calloc(1, sizeof(struct adiv5_dap));
630 /* Set up with safe defaults */
631 for (i = 0; i <= 255; i++) {
632 dap->ap[i].dap = dap;
633 dap->ap[i].ap_num = i;
634 /* memaccess_tck max is 255 */
635 dap->ap[i].memaccess_tck = 255;
636 /* Number of bits for tar autoincrement, impl. dep. at least 10 */
637 dap->ap[i].tar_autoincr_block = (1<<10);
639 INIT_LIST_HEAD(&dap->cmd_journal);
644 * Invalidate cached DP select and cached TAR and CSW of all APs
646 void dap_invalidate_cache(struct adiv5_dap *dap)
648 dap->select = DP_SELECT_INVALID;
649 dap->last_read = NULL;
652 for (i = 0; i <= 255; i++) {
653 /* force csw and tar write on the next mem-ap access */
654 dap->ap[i].tar_valid = false;
655 dap->ap[i].csw_value = 0;
660 * Initialize a DAP. This sets up the power domains, prepares the DP
661 * for further use and activates overrun checking.
663 * @param dap The DAP being initialized.
665 int dap_dp_init(struct adiv5_dap *dap)
670 /* JTAG-DP or SWJ-DP, in JTAG mode
671 * ... for SWD mode this is patched as part
673 * FIXME: This should already be setup by the respective transport specific DAP creation.
676 dap->ops = &jtag_dp_ops;
678 dap_invalidate_cache(dap);
680 for (size_t i = 0; i < 30; i++) {
681 /* DP initialization */
683 retval = dap_dp_read_atomic(dap, DP_CTRL_STAT, NULL);
684 if (retval == ERROR_OK)
688 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
689 if (retval != ERROR_OK)
692 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
693 if (retval != ERROR_OK)
696 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
697 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
698 if (retval != ERROR_OK)
701 /* Check that we have debug power domains activated */
702 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
703 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
704 CDBGPWRUPACK, CDBGPWRUPACK,
705 DAP_POWER_DOMAIN_TIMEOUT);
706 if (retval != ERROR_OK)
709 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
710 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
711 CSYSPWRUPACK, CSYSPWRUPACK,
712 DAP_POWER_DOMAIN_TIMEOUT);
713 if (retval != ERROR_OK)
716 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
717 if (retval != ERROR_OK)
720 /* With debug power on we can activate OVERRUN checking */
721 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
722 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
723 if (retval != ERROR_OK)
725 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
726 if (retval != ERROR_OK)
729 retval = dap_run(dap);
730 if (retval != ERROR_OK)
737 * Initialize a DAP. This sets up the power domains, prepares the DP
738 * for further use, and arranges to use AP #0 for all AP operations
739 * until dap_ap-select() changes that policy.
741 * @param ap The MEM-AP being initialized.
743 int mem_ap_init(struct adiv5_ap *ap)
745 /* check that we support packed transfers */
748 struct adiv5_dap *dap = ap->dap;
750 ap->tar_valid = false;
751 ap->csw_value = 0; /* force csw and tar write */
752 retval = mem_ap_setup_transfer(ap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
753 if (retval != ERROR_OK)
756 retval = dap_queue_ap_read(ap, MEM_AP_REG_CSW, &csw);
757 if (retval != ERROR_OK)
760 retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &cfg);
761 if (retval != ERROR_OK)
764 retval = dap_run(dap);
765 if (retval != ERROR_OK)
768 if (csw & CSW_ADDRINC_PACKED)
769 ap->packed_transfers = true;
771 ap->packed_transfers = false;
773 /* Packed transfers on TI BE-32 processors do not work correctly in
775 if (dap->ti_be_32_quirks)
776 ap->packed_transfers = false;
778 LOG_DEBUG("MEM_AP Packed Transfers: %s",
779 ap->packed_transfers ? "enabled" : "disabled");
781 /* The ARM ADI spec leaves implementation-defined whether unaligned
782 * memory accesses work, only work partially, or cause a sticky error.
783 * On TI BE-32 processors, reads seem to return garbage in some bytes
784 * and unaligned writes seem to cause a sticky error.
785 * TODO: it would be nice to have a way to detect whether unaligned
786 * operations are supported on other processors. */
787 ap->unaligned_access_bad = dap->ti_be_32_quirks;
789 LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
790 !!(cfg & 0x04), !!(cfg & 0x02), !!(cfg & 0x01));
795 /* CID interpretation -- see ARM IHI 0029B section 3
796 * and ARM IHI 0031A table 13-3.
798 static const char *class_description[16] = {
799 "Reserved", "ROM table", "Reserved", "Reserved",
800 "Reserved", "Reserved", "Reserved", "Reserved",
801 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
802 "Reserved", "OptimoDE DESS",
803 "Generic IP component", "PrimeCell or System component"
806 static bool is_dap_cid_ok(uint32_t cid)
808 return (cid & 0xffff0fff) == 0xb105000d;
812 * This function checks the ID for each access port to find the requested Access Port type
814 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out)
818 /* Maximum AP number is 255 since the SELECT register is 8 bits */
819 for (ap_num = 0; ap_num <= 255; ap_num++) {
821 /* read the IDR register of the Access Port */
824 int retval = dap_queue_ap_read(dap_ap(dap, ap_num), AP_REG_IDR, &id_val);
825 if (retval != ERROR_OK)
828 retval = dap_run(dap);
832 * 27-24 : JEDEC bank (0x4 for ARM)
833 * 23-17 : JEDEC code (0x3B for ARM)
834 * 16-13 : Class (0b1000=Mem-AP)
836 * 7-4 : AP Variant (non-zero for JTAG-AP)
837 * 3-0 : AP Type (0=JTAG-AP 1=AHB-AP 2=APB-AP 4=AXI-AP)
840 /* Reading register for a non-existant AP should not cause an error,
841 * but just to be sure, try to continue searching if an error does happen.
843 if ((retval == ERROR_OK) && /* Register read success */
844 ((id_val & IDR_JEP106) == IDR_JEP106_ARM) && /* Jedec codes match */
845 ((id_val & IDR_TYPE) == type_to_find)) { /* type matches*/
847 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
848 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
849 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
850 (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
851 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
854 *ap_out = &dap->ap[ap_num];
859 LOG_DEBUG("No %s found",
860 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
861 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
862 (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
863 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
867 int dap_get_debugbase(struct adiv5_ap *ap,
868 uint32_t *dbgbase, uint32_t *apid)
870 struct adiv5_dap *dap = ap->dap;
873 retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE, dbgbase);
874 if (retval != ERROR_OK)
876 retval = dap_queue_ap_read(ap, AP_REG_IDR, apid);
877 if (retval != ERROR_OK)
879 retval = dap_run(dap);
880 if (retval != ERROR_OK)
886 int dap_lookup_cs_component(struct adiv5_ap *ap,
887 uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx)
889 uint32_t romentry, entry_offset = 0, component_base, devtype;
895 retval = mem_ap_read_atomic_u32(ap, (dbgbase&0xFFFFF000) |
896 entry_offset, &romentry);
897 if (retval != ERROR_OK)
900 component_base = (dbgbase & 0xFFFFF000)
901 + (romentry & 0xFFFFF000);
903 if (romentry & 0x1) {
905 retval = mem_ap_read_atomic_u32(ap, component_base | 0xff4, &c_cid1);
906 if (retval != ERROR_OK) {
907 LOG_ERROR("Can't read component with base address 0x%" PRIx32
908 ", the corresponding core might be turned off", component_base);
911 if (((c_cid1 >> 4) & 0x0f) == 1) {
912 retval = dap_lookup_cs_component(ap, component_base,
914 if (retval == ERROR_OK)
916 if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
920 retval = mem_ap_read_atomic_u32(ap,
921 (component_base & 0xfffff000) | 0xfcc,
923 if (retval != ERROR_OK)
925 if ((devtype & 0xff) == type) {
927 *addr = component_base;
934 } while (romentry > 0);
937 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
942 static int dap_read_part_id(struct adiv5_ap *ap, uint32_t component_base, uint32_t *cid, uint64_t *pid)
944 assert((component_base & 0xFFF) == 0);
945 assert(ap != NULL && cid != NULL && pid != NULL);
947 uint32_t cid0, cid1, cid2, cid3;
948 uint32_t pid0, pid1, pid2, pid3, pid4;
951 /* IDs are in last 4K section */
952 retval = mem_ap_read_u32(ap, component_base + 0xFE0, &pid0);
953 if (retval != ERROR_OK)
955 retval = mem_ap_read_u32(ap, component_base + 0xFE4, &pid1);
956 if (retval != ERROR_OK)
958 retval = mem_ap_read_u32(ap, component_base + 0xFE8, &pid2);
959 if (retval != ERROR_OK)
961 retval = mem_ap_read_u32(ap, component_base + 0xFEC, &pid3);
962 if (retval != ERROR_OK)
964 retval = mem_ap_read_u32(ap, component_base + 0xFD0, &pid4);
965 if (retval != ERROR_OK)
967 retval = mem_ap_read_u32(ap, component_base + 0xFF0, &cid0);
968 if (retval != ERROR_OK)
970 retval = mem_ap_read_u32(ap, component_base + 0xFF4, &cid1);
971 if (retval != ERROR_OK)
973 retval = mem_ap_read_u32(ap, component_base + 0xFF8, &cid2);
974 if (retval != ERROR_OK)
976 retval = mem_ap_read_u32(ap, component_base + 0xFFC, &cid3);
977 if (retval != ERROR_OK)
980 retval = dap_run(ap->dap);
981 if (retval != ERROR_OK)
984 *cid = (cid3 & 0xff) << 24
985 | (cid2 & 0xff) << 16
988 *pid = (uint64_t)(pid4 & 0xff) << 32
989 | (pid3 & 0xff) << 24
990 | (pid2 & 0xff) << 16
997 /* The designer identity code is encoded as:
998 * bits 11:8 : JEP106 Bank (number of continuation codes), only valid when bit 7 is 1.
999 * bit 7 : Set when bits 6:0 represent a JEP106 ID and cleared when bits 6:0 represent
1000 * a legacy ASCII Identity Code.
1001 * bits 6:0 : JEP106 Identity Code (without parity) or legacy ASCII code according to bit 7.
1002 * JEP106 is a standard available from jedec.org
1005 /* Part number interpretations are from Cortex
1006 * core specs, the CoreSight components TRM
1007 * (ARM DDI 0314H), CoreSight System Design
1008 * Guide (ARM DGI 0012D) and ETM specs; also
1009 * from chip observation (e.g. TI SDTI).
1012 /* The legacy code only used the part number field to identify CoreSight peripherals.
1013 * This meant that the same part number from two different manufacturers looked the same.
1014 * It is desirable for all future additions to identify with both part number and JEP106.
1015 * "ANY_ID" is a wildcard (any JEP106) only to preserve legacy behavior for legacy entries.
1018 #define ANY_ID 0x1000
1020 #define ARM_ID 0x4BB
1022 static const struct {
1023 uint16_t designer_id;
1027 } dap_partnums[] = {
1028 { ARM_ID, 0x000, "Cortex-M3 SCS", "(System Control Space)", },
1029 { ARM_ID, 0x001, "Cortex-M3 ITM", "(Instrumentation Trace Module)", },
1030 { ARM_ID, 0x002, "Cortex-M3 DWT", "(Data Watchpoint and Trace)", },
1031 { ARM_ID, 0x003, "Cortex-M3 FPB", "(Flash Patch and Breakpoint)", },
1032 { ARM_ID, 0x008, "Cortex-M0 SCS", "(System Control Space)", },
1033 { ARM_ID, 0x00a, "Cortex-M0 DWT", "(Data Watchpoint and Trace)", },
1034 { ARM_ID, 0x00b, "Cortex-M0 BPU", "(Breakpoint Unit)", },
1035 { ARM_ID, 0x00c, "Cortex-M4 SCS", "(System Control Space)", },
1036 { ARM_ID, 0x00d, "CoreSight ETM11", "(Embedded Trace)", },
1037 { ARM_ID, 0x00e, "Cortex-M7 FPB", "(Flash Patch and Breakpoint)", },
1038 { ARM_ID, 0x490, "Cortex-A15 GIC", "(Generic Interrupt Controller)", },
1039 { ARM_ID, 0x4a1, "Cortex-A53 ROM", "(v8 Memory Map ROM Table)", },
1040 { ARM_ID, 0x4a2, "Cortex-A57 ROM", "(ROM Table)", },
1041 { ARM_ID, 0x4a3, "Cortex-A53 ROM", "(v7 Memory Map ROM Table)", },
1042 { ARM_ID, 0x4a4, "Cortex-A72 ROM", "(ROM Table)", },
1043 { ARM_ID, 0x4a9, "Cortex-A9 ROM", "(ROM Table)", },
1044 { ARM_ID, 0x4af, "Cortex-A15 ROM", "(ROM Table)", },
1045 { ARM_ID, 0x4c0, "Cortex-M0+ ROM", "(ROM Table)", },
1046 { ARM_ID, 0x4c3, "Cortex-M3 ROM", "(ROM Table)", },
1047 { ARM_ID, 0x4c4, "Cortex-M4 ROM", "(ROM Table)", },
1048 { ARM_ID, 0x4c7, "Cortex-M7 PPB ROM", "(Private Peripheral Bus ROM Table)", },
1049 { ARM_ID, 0x4c8, "Cortex-M7 ROM", "(ROM Table)", },
1050 { ARM_ID, 0x4b5, "Cortex-R5 ROM", "(ROM Table)", },
1051 { ARM_ID, 0x470, "Cortex-M1 ROM", "(ROM Table)", },
1052 { ARM_ID, 0x471, "Cortex-M0 ROM", "(ROM Table)", },
1053 { ARM_ID, 0x906, "CoreSight CTI", "(Cross Trigger)", },
1054 { ARM_ID, 0x907, "CoreSight ETB", "(Trace Buffer)", },
1055 { ARM_ID, 0x908, "CoreSight CSTF", "(Trace Funnel)", },
1056 { ARM_ID, 0x909, "CoreSight ATBR", "(Advanced Trace Bus Replicator)", },
1057 { ARM_ID, 0x910, "CoreSight ETM9", "(Embedded Trace)", },
1058 { ARM_ID, 0x912, "CoreSight TPIU", "(Trace Port Interface Unit)", },
1059 { ARM_ID, 0x913, "CoreSight ITM", "(Instrumentation Trace Macrocell)", },
1060 { ARM_ID, 0x914, "CoreSight SWO", "(Single Wire Output)", },
1061 { ARM_ID, 0x917, "CoreSight HTM", "(AHB Trace Macrocell)", },
1062 { ARM_ID, 0x920, "CoreSight ETM11", "(Embedded Trace)", },
1063 { ARM_ID, 0x921, "Cortex-A8 ETM", "(Embedded Trace)", },
1064 { ARM_ID, 0x922, "Cortex-A8 CTI", "(Cross Trigger)", },
1065 { ARM_ID, 0x923, "Cortex-M3 TPIU", "(Trace Port Interface Unit)", },
1066 { ARM_ID, 0x924, "Cortex-M3 ETM", "(Embedded Trace)", },
1067 { ARM_ID, 0x925, "Cortex-M4 ETM", "(Embedded Trace)", },
1068 { ARM_ID, 0x930, "Cortex-R4 ETM", "(Embedded Trace)", },
1069 { ARM_ID, 0x931, "Cortex-R5 ETM", "(Embedded Trace)", },
1070 { ARM_ID, 0x932, "CoreSight MTB-M0+", "(Micro Trace Buffer)", },
1071 { ARM_ID, 0x941, "CoreSight TPIU-Lite", "(Trace Port Interface Unit)", },
1072 { ARM_ID, 0x950, "Cortex-A9 PTM", "(Program Trace Macrocell)", },
1073 { ARM_ID, 0x955, "Cortex-A5 ETM", "(Embedded Trace)", },
1074 { ARM_ID, 0x95a, "Cortex-A72 ETM", "(Embedded Trace)", },
1075 { ARM_ID, 0x95b, "Cortex-A17 PTM", "(Program Trace Macrocell)", },
1076 { ARM_ID, 0x95d, "Cortex-A53 ETM", "(Embedded Trace)", },
1077 { ARM_ID, 0x95e, "Cortex-A57 ETM", "(Embedded Trace)", },
1078 { ARM_ID, 0x95f, "Cortex-A15 PTM", "(Program Trace Macrocell)", },
1079 { ARM_ID, 0x961, "CoreSight TMC", "(Trace Memory Controller)", },
1080 { ARM_ID, 0x962, "CoreSight STM", "(System Trace Macrocell)", },
1081 { ARM_ID, 0x975, "Cortex-M7 ETM", "(Embedded Trace)", },
1082 { ARM_ID, 0x9a0, "CoreSight PMU", "(Performance Monitoring Unit)", },
1083 { ARM_ID, 0x9a1, "Cortex-M4 TPIU", "(Trace Port Interface Unit)", },
1084 { ARM_ID, 0x9a4, "CoreSight GPR", "(Granular Power Requester)", },
1085 { ARM_ID, 0x9a5, "Cortex-A5 PMU", "(Performance Monitor Unit)", },
1086 { ARM_ID, 0x9a7, "Cortex-A7 PMU", "(Performance Monitor Unit)", },
1087 { ARM_ID, 0x9a8, "Cortex-A53 CTI", "(Cross Trigger)", },
1088 { ARM_ID, 0x9a9, "Cortex-M7 TPIU", "(Trace Port Interface Unit)", },
1089 { ARM_ID, 0x9ae, "Cortex-A17 PMU", "(Performance Monitor Unit)", },
1090 { ARM_ID, 0x9af, "Cortex-A15 PMU", "(Performance Monitor Unit)", },
1091 { ARM_ID, 0x9b7, "Cortex-R7 PMU", "(Performance Monitor Unit)", },
1092 { ARM_ID, 0x9d3, "Cortex-A53 PMU", "(Performance Monitor Unit)", },
1093 { ARM_ID, 0x9d7, "Cortex-A57 PMU", "(Performance Monitor Unit)", },
1094 { ARM_ID, 0x9d8, "Cortex-A72 PMU", "(Performance Monitor Unit)", },
1095 { ARM_ID, 0xc05, "Cortex-A5 Debug", "(Debug Unit)", },
1096 { ARM_ID, 0xc07, "Cortex-A7 Debug", "(Debug Unit)", },
1097 { ARM_ID, 0xc08, "Cortex-A8 Debug", "(Debug Unit)", },
1098 { ARM_ID, 0xc09, "Cortex-A9 Debug", "(Debug Unit)", },
1099 { ARM_ID, 0xc0e, "Cortex-A17 Debug", "(Debug Unit)", },
1100 { ARM_ID, 0xc0f, "Cortex-A15 Debug", "(Debug Unit)", },
1101 { ARM_ID, 0xc14, "Cortex-R4 Debug", "(Debug Unit)", },
1102 { ARM_ID, 0xc15, "Cortex-R5 Debug", "(Debug Unit)", },
1103 { ARM_ID, 0xc17, "Cortex-R7 Debug", "(Debug Unit)", },
1104 { ARM_ID, 0xd03, "Cortex-A53 Debug", "(Debug Unit)", },
1105 { ARM_ID, 0xd07, "Cortex-A57 Debug", "(Debug Unit)", },
1106 { ARM_ID, 0xd08, "Cortex-A72 Debug", "(Debug Unit)", },
1107 { 0x097, 0x9af, "MSP432 ROM", "(ROM Table)" },
1108 { 0x09f, 0xcd0, "Atmel CPU with DSU", "(CPU)" },
1109 { 0x0c1, 0x1db, "XMC4500 ROM", "(ROM Table)" },
1110 { 0x0c1, 0x1df, "XMC4700/4800 ROM", "(ROM Table)" },
1111 { 0x0c1, 0x1ed, "XMC1000 ROM", "(ROM Table)" },
1112 { 0x0E5, 0x000, "SHARC+/Blackfin+", "", },
1113 { 0x0F0, 0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", },
1114 { 0x3eb, 0x181, "Tegra 186 ROM", "(ROM Table)", },
1115 { 0x3eb, 0x211, "Tegra 210 ROM", "(ROM Table)", },
1116 { 0x3eb, 0x202, "Denver ETM", "(Denver Embedded Trace)", },
1117 { 0x3eb, 0x302, "Denver Debug", "(Debug Unit)", },
1118 { 0x3eb, 0x402, "Denver PMU", "(Performance Monitor Unit)", },
1119 /* legacy comment: 0x113: what? */
1120 { ANY_ID, 0x120, "TI SDTI", "(System Debug Trace Interface)", }, /* from OMAP3 memmap */
1121 { ANY_ID, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */
1124 static int dap_rom_display(struct command_context *cmd_ctx,
1125 struct adiv5_ap *ap, uint32_t dbgbase, int depth)
1133 command_print(cmd_ctx, "\tTables too deep");
1138 snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
1140 uint32_t base_addr = dbgbase & 0xFFFFF000;
1141 command_print(cmd_ctx, "\t\tComponent base address 0x%08" PRIx32, base_addr);
1143 retval = dap_read_part_id(ap, base_addr, &cid, &pid);
1144 if (retval != ERROR_OK) {
1145 command_print(cmd_ctx, "\t\tCan't read component, the corresponding core might be turned off");
1146 return ERROR_OK; /* Don't abort recursion */
1149 if (!is_dap_cid_ok(cid)) {
1150 command_print(cmd_ctx, "\t\tInvalid CID 0x%08" PRIx32, cid);
1151 return ERROR_OK; /* Don't abort recursion */
1154 /* component may take multiple 4K pages */
1155 uint32_t size = (pid >> 36) & 0xf;
1157 command_print(cmd_ctx, "\t\tStart address 0x%08" PRIx32, (uint32_t)(base_addr - 0x1000 * size));
1159 command_print(cmd_ctx, "\t\tPeripheral ID 0x%010" PRIx64, pid);
1161 uint8_t class = (cid >> 12) & 0xf;
1162 uint16_t part_num = pid & 0xfff;
1163 uint16_t designer_id = ((pid >> 32) & 0xf) << 8 | ((pid >> 12) & 0xff);
1165 if (designer_id & 0x80) {
1167 command_print(cmd_ctx, "\t\tDesigner is 0x%03" PRIx16 ", %s",
1168 designer_id, jep106_manufacturer(designer_id >> 8, designer_id & 0x7f));
1170 /* Legacy ASCII ID, clear invalid bits */
1171 designer_id &= 0x7f;
1172 command_print(cmd_ctx, "\t\tDesigner ASCII code 0x%02" PRIx16 ", %s",
1173 designer_id, designer_id == 0x41 ? "ARM" : "<unknown>");
1176 /* default values to be overwritten upon finding a match */
1177 const char *type = "Unrecognized";
1178 const char *full = "";
1180 /* search dap_partnums[] array for a match */
1181 for (unsigned entry = 0; entry < ARRAY_SIZE(dap_partnums); entry++) {
1183 if ((dap_partnums[entry].designer_id != designer_id) && (dap_partnums[entry].designer_id != ANY_ID))
1186 if (dap_partnums[entry].part_num != part_num)
1189 type = dap_partnums[entry].type;
1190 full = dap_partnums[entry].full;
1194 command_print(cmd_ctx, "\t\tPart is 0x%" PRIx16", %s %s", part_num, type, full);
1195 command_print(cmd_ctx, "\t\tComponent class is 0x%" PRIx8 ", %s", class, class_description[class]);
1197 if (class == 1) { /* ROM Table */
1199 retval = mem_ap_read_atomic_u32(ap, base_addr | 0xFCC, &memtype);
1200 if (retval != ERROR_OK)
1204 command_print(cmd_ctx, "\t\tMEMTYPE system memory present on bus");
1206 command_print(cmd_ctx, "\t\tMEMTYPE system memory not present: dedicated debug bus");
1208 /* Read ROM table entries from base address until we get 0x00000000 or reach the reserved area */
1209 for (uint16_t entry_offset = 0; entry_offset < 0xF00; entry_offset += 4) {
1211 retval = mem_ap_read_atomic_u32(ap, base_addr | entry_offset, &romentry);
1212 if (retval != ERROR_OK)
1214 command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
1215 tabs, entry_offset, romentry);
1216 if (romentry & 0x01) {
1218 retval = dap_rom_display(cmd_ctx, ap, base_addr + (romentry & 0xFFFFF000), depth + 1);
1219 if (retval != ERROR_OK)
1221 } else if (romentry != 0) {
1222 command_print(cmd_ctx, "\t\tComponent not present");
1224 command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs);
1228 } else if (class == 9) { /* CoreSight component */
1229 const char *major = "Reserved", *subtype = "Reserved";
1232 retval = mem_ap_read_atomic_u32(ap, base_addr | 0xFCC, &devtype);
1233 if (retval != ERROR_OK)
1235 unsigned minor = (devtype >> 4) & 0x0f;
1236 switch (devtype & 0x0f) {
1238 major = "Miscellaneous";
1244 subtype = "Validation component";
1249 major = "Trace Sink";
1266 major = "Trace Link";
1272 subtype = "Funnel, router";
1278 subtype = "FIFO, buffer";
1283 major = "Trace Source";
1289 subtype = "Processor";
1295 subtype = "Engine/Coprocessor";
1301 subtype = "Software";
1306 major = "Debug Control";
1312 subtype = "Trigger Matrix";
1315 subtype = "Debug Auth";
1318 subtype = "Power Requestor";
1323 major = "Debug Logic";
1329 subtype = "Processor";
1335 subtype = "Engine/Coprocessor";
1346 major = "Perfomance Monitor";
1352 subtype = "Processor";
1358 subtype = "Engine/Coprocessor";
1369 command_print(cmd_ctx, "\t\tType is 0x%02" PRIx8 ", %s, %s",
1370 (uint8_t)(devtype & 0xff),
1372 /* REVISIT also show 0xfc8 DevId */
1378 static int dap_info_command(struct command_context *cmd_ctx,
1379 struct adiv5_ap *ap)
1382 uint32_t dbgbase, apid;
1385 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1386 retval = dap_get_debugbase(ap, &dbgbase, &apid);
1387 if (retval != ERROR_OK)
1390 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1392 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap->ap_num);
1396 switch (apid & (IDR_JEP106 | IDR_TYPE)) {
1397 case IDR_JEP106_ARM | AP_TYPE_JTAG_AP:
1398 command_print(cmd_ctx, "\tType is JTAG-AP");
1400 case IDR_JEP106_ARM | AP_TYPE_AHB_AP:
1401 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1403 case IDR_JEP106_ARM | AP_TYPE_APB_AP:
1404 command_print(cmd_ctx, "\tType is MEM-AP APB");
1406 case IDR_JEP106_ARM | AP_TYPE_AXI_AP:
1407 command_print(cmd_ctx, "\tType is MEM-AP AXI");
1410 command_print(cmd_ctx, "\tUnknown AP type");
1414 /* NOTE: a MEM-AP may have a single CoreSight component that's
1415 * not a ROM table ... or have no such components at all.
1417 mem_ap = (apid & IDR_CLASS) == AP_CLASS_MEM_AP;
1419 command_print(cmd_ctx, "MEM-AP BASE 0x%8.8" PRIx32, dbgbase);
1421 if (dbgbase == 0xFFFFFFFF || (dbgbase & 0x3) == 0x2) {
1422 command_print(cmd_ctx, "\tNo ROM table present");
1425 command_print(cmd_ctx, "\tValid ROM table present");
1427 command_print(cmd_ctx, "\tROM table in legacy format");
1429 dap_rom_display(cmd_ctx, ap, dbgbase & 0xFFFFF000, 0);
1436 int adiv5_jim_configure(struct target *target, Jim_GetOptInfo *goi)
1438 struct adiv5_private_config *pc;
1443 /* check if argv[0] is for us */
1444 arg = Jim_GetString(goi->argv[0], NULL);
1445 if (strcmp(arg, "-ap-num"))
1446 return JIM_CONTINUE;
1448 e = Jim_GetOpt_String(goi, &arg, NULL);
1452 if (goi->argc == 0) {
1453 Jim_WrongNumArgs(goi->interp, goi->argc, goi->argv, "-ap-num ?ap-number? ...");
1457 e = Jim_GetOpt_Wide(goi, &ap_num);
1461 if (target->private_config == NULL) {
1462 pc = calloc(1, sizeof(struct adiv5_private_config));
1463 target->private_config = pc;
1464 pc->ap_num = ap_num;
1471 COMMAND_HANDLER(handle_dap_info_command)
1473 struct target *target = get_current_target(CMD_CTX);
1474 struct arm *arm = target_to_arm(target);
1475 struct adiv5_dap *dap = arm->dap;
1483 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1485 return ERROR_COMMAND_SYNTAX_ERROR;
1488 return ERROR_COMMAND_SYNTAX_ERROR;
1491 return dap_info_command(CMD_CTX, &dap->ap[apsel]);
1494 COMMAND_HANDLER(dap_baseaddr_command)
1496 struct target *target = get_current_target(CMD_CTX);
1497 struct arm *arm = target_to_arm(target);
1498 struct adiv5_dap *dap = arm->dap;
1500 uint32_t apsel, baseaddr;
1508 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1509 /* AP address is in bits 31:24 of DP_SELECT */
1511 return ERROR_COMMAND_SYNTAX_ERROR;
1514 return ERROR_COMMAND_SYNTAX_ERROR;
1517 /* NOTE: assumes we're talking to a MEM-AP, which
1518 * has a base address. There are other kinds of AP,
1519 * though they're not common for now. This should
1520 * use the ID register to verify it's a MEM-AP.
1522 retval = dap_queue_ap_read(dap_ap(dap, apsel), MEM_AP_REG_BASE, &baseaddr);
1523 if (retval != ERROR_OK)
1525 retval = dap_run(dap);
1526 if (retval != ERROR_OK)
1529 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1534 COMMAND_HANDLER(dap_memaccess_command)
1536 struct target *target = get_current_target(CMD_CTX);
1537 struct arm *arm = target_to_arm(target);
1538 struct adiv5_dap *dap = arm->dap;
1540 uint32_t memaccess_tck;
1544 memaccess_tck = dap->ap[dap->apsel].memaccess_tck;
1547 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1550 return ERROR_COMMAND_SYNTAX_ERROR;
1552 dap->ap[dap->apsel].memaccess_tck = memaccess_tck;
1554 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1555 dap->ap[dap->apsel].memaccess_tck);
1560 COMMAND_HANDLER(dap_apsel_command)
1562 struct target *target = get_current_target(CMD_CTX);
1563 struct arm *arm = target_to_arm(target);
1564 struct adiv5_dap *dap = arm->dap;
1566 uint32_t apsel, apid;
1574 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1575 /* AP address is in bits 31:24 of DP_SELECT */
1577 return ERROR_COMMAND_SYNTAX_ERROR;
1580 return ERROR_COMMAND_SYNTAX_ERROR;
1585 retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid);
1586 if (retval != ERROR_OK)
1588 retval = dap_run(dap);
1589 if (retval != ERROR_OK)
1592 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1598 COMMAND_HANDLER(dap_apcsw_command)
1600 struct target *target = get_current_target(CMD_CTX);
1601 struct arm *arm = target_to_arm(target);
1602 struct adiv5_dap *dap = arm->dap;
1604 uint32_t apcsw = dap->ap[dap->apsel].csw_default, sprot = 0;
1608 command_print(CMD_CTX, "apsel %" PRIi32 " selected, csw 0x%8.8" PRIx32,
1609 (dap->apsel), apcsw);
1612 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], sprot);
1613 /* AP address is in bits 31:24 of DP_SELECT */
1615 return ERROR_COMMAND_SYNTAX_ERROR;
1619 apcsw &= ~CSW_SPROT;
1622 return ERROR_COMMAND_SYNTAX_ERROR;
1624 dap->ap[dap->apsel].csw_default = apcsw;
1631 COMMAND_HANDLER(dap_apid_command)
1633 struct target *target = get_current_target(CMD_CTX);
1634 struct arm *arm = target_to_arm(target);
1635 struct adiv5_dap *dap = arm->dap;
1637 uint32_t apsel, apid;
1645 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1646 /* AP address is in bits 31:24 of DP_SELECT */
1648 return ERROR_COMMAND_SYNTAX_ERROR;
1651 return ERROR_COMMAND_SYNTAX_ERROR;
1654 retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid);
1655 if (retval != ERROR_OK)
1657 retval = dap_run(dap);
1658 if (retval != ERROR_OK)
1661 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1666 COMMAND_HANDLER(dap_apreg_command)
1668 struct target *target = get_current_target(CMD_CTX);
1669 struct arm *arm = target_to_arm(target);
1670 struct adiv5_dap *dap = arm->dap;
1672 uint32_t apsel, reg, value;
1675 if (CMD_ARGC < 2 || CMD_ARGC > 3)
1676 return ERROR_COMMAND_SYNTAX_ERROR;
1678 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1679 /* AP address is in bits 31:24 of DP_SELECT */
1681 return ERROR_COMMAND_SYNTAX_ERROR;
1683 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg);
1684 if (reg >= 256 || (reg & 3))
1685 return ERROR_COMMAND_SYNTAX_ERROR;
1687 if (CMD_ARGC == 3) {
1688 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
1689 retval = dap_queue_ap_write(dap_ap(dap, apsel), reg, value);
1691 retval = dap_queue_ap_read(dap_ap(dap, apsel), reg, &value);
1693 if (retval == ERROR_OK)
1694 retval = dap_run(dap);
1696 if (retval != ERROR_OK)
1700 command_print(CMD_CTX, "0x%08" PRIx32, value);
1705 COMMAND_HANDLER(dap_ti_be_32_quirks_command)
1707 struct target *target = get_current_target(CMD_CTX);
1708 struct arm *arm = target_to_arm(target);
1709 struct adiv5_dap *dap = arm->dap;
1711 uint32_t enable = dap->ti_be_32_quirks;
1717 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], enable);
1719 return ERROR_COMMAND_SYNTAX_ERROR;
1722 return ERROR_COMMAND_SYNTAX_ERROR;
1724 dap->ti_be_32_quirks = enable;
1725 command_print(CMD_CTX, "TI BE-32 quirks mode %s",
1726 enable ? "enabled" : "disabled");
1731 static const struct command_registration dap_commands[] = {
1734 .handler = handle_dap_info_command,
1735 .mode = COMMAND_EXEC,
1736 .help = "display ROM table for MEM-AP "
1737 "(default currently selected AP)",
1738 .usage = "[ap_num]",
1742 .handler = dap_apsel_command,
1743 .mode = COMMAND_EXEC,
1744 .help = "Set the currently selected AP (default 0) "
1745 "and display the result",
1746 .usage = "[ap_num]",
1750 .handler = dap_apcsw_command,
1751 .mode = COMMAND_EXEC,
1752 .help = "Set csw access bit ",
1758 .handler = dap_apid_command,
1759 .mode = COMMAND_EXEC,
1760 .help = "return ID register from AP "
1761 "(default currently selected AP)",
1762 .usage = "[ap_num]",
1766 .handler = dap_apreg_command,
1767 .mode = COMMAND_EXEC,
1768 .help = "read/write a register from AP "
1769 "(reg is byte address of a word register, like 0 4 8...)",
1770 .usage = "ap_num reg [value]",
1774 .handler = dap_baseaddr_command,
1775 .mode = COMMAND_EXEC,
1776 .help = "return debug base address from MEM-AP "
1777 "(default currently selected AP)",
1778 .usage = "[ap_num]",
1781 .name = "memaccess",
1782 .handler = dap_memaccess_command,
1783 .mode = COMMAND_EXEC,
1784 .help = "set/get number of extra tck for MEM-AP memory "
1785 "bus access [0-255]",
1786 .usage = "[cycles]",
1789 .name = "ti_be_32_quirks",
1790 .handler = dap_ti_be_32_quirks_command,
1791 .mode = COMMAND_CONFIG,
1792 .help = "set/get quirks mode for TI TMS450/TMS570 processors",
1793 .usage = "[enable]",
1795 COMMAND_REGISTRATION_DONE
1798 const struct command_registration dap_command_handlers[] = {
1801 .mode = COMMAND_EXEC,
1802 .help = "DAP command group",
1804 .chain = dap_commands,
1806 COMMAND_REGISTRATION_DONE