1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * Copyright (C) 2009-2010 by David Brownell *
13 * This program is free software; you can redistribute it and/or modify *
14 * it under the terms of the GNU General Public License as published by *
15 * the Free Software Foundation; either version 2 of the License, or *
16 * (at your option) any later version. *
18 * This program is distributed in the hope that it will be useful, *
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
21 * GNU General Public License for more details. *
23 * You should have received a copy of the GNU General Public License *
24 * along with this program; if not, write to the *
25 * Free Software Foundation, Inc., *
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 ***************************************************************************/
31 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
32 * debugging architecture. Compared with previous versions, this includes
33 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
34 * transport, and focusses on memory mapped resources as defined by the
35 * CoreSight architecture.
37 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
38 * basic components: a Debug Port (DP) transporting messages to and from a
39 * debugger, and an Access Port (AP) accessing resources. Three types of DP
40 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
41 * One uses only SWD for communication, and is called SW-DP. The third can
42 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
43 * is used to access memory mapped resources and is called a MEM-AP. Also a
44 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
46 * This programming interface allows DAP pipelined operations through a
47 * transaction queue. This primarily affects AP operations (such as using
48 * a MEM-AP to access memory or registers). If the current transaction has
49 * not finished by the time the next one must begin, and the ORUNDETECT bit
50 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
51 * further AP operations will fail. There are two basic methods to avoid
52 * such overrun errors. One involves polling for status instead of using
53 * transaction piplining. The other involves adding delays to ensure the
54 * AP has enough time to complete one operation before starting the next
55 * one. (For JTAG these delays are controlled by memaccess_tck.)
59 * Relevant specifications from ARM include:
61 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
62 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
64 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
65 * Cortex-M3(tm) TRM, ARM DDI 0337G
73 #include "arm_adi_v5.h"
74 #include <helper/time_support.h>
77 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
80 uint32_t tar_block_size(uint32_t address)
81 Return the largest block starting at address that does not cross a tar block size alignment boundary
83 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
85 return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
88 /***************************************************************************
90 * DP and MEM-AP register access through APACC and DPACC *
92 ***************************************************************************/
95 * Select one of the APs connected to the specified DAP. The
96 * selection is implicitly used with future AP transactions.
97 * This is a NOP if the specified AP is already selected.
100 * @param apsel Number of the AP to (implicitly) use with further
101 * transactions. This normally identifies a MEM-AP.
103 void dap_ap_select(struct adiv5_dap *dap,uint8_t ap)
105 uint32_t new_ap = (ap << 24) & 0xFF000000;
107 if (new_ap != dap->ap_current)
109 dap->ap_current = new_ap;
110 /* Switching AP invalidates cached values.
111 * Values MUST BE UPDATED BEFORE AP ACCESS.
113 dap->ap_bank_value = -1;
114 dap->ap_csw_value = -1;
115 dap->ap_tar_value = -1;
120 * Queue transactions setting up transfer parameters for the
121 * currently selected MEM-AP.
123 * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
124 * initiate data reads or writes using memory or peripheral addresses.
125 * If the CSW is configured for it, the TAR may be automatically
126 * incremented after each transfer.
128 * @todo Rename to reflect it being specifically a MEM-AP function.
130 * @param dap The DAP connected to the MEM-AP.
131 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
132 * matches the cached value, the register is not changed.
133 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
134 * matches the cached address, the register is not changed.
136 * @return ERROR_OK if the transaction was properly queued, else a fault code.
138 int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
142 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
143 if (csw != dap->ap_csw_value)
145 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
146 retval = dap_queue_ap_write(dap, AP_REG_CSW, csw);
147 if (retval != ERROR_OK)
149 dap->ap_csw_value = csw;
151 if (tar != dap->ap_tar_value)
153 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
154 retval = dap_queue_ap_write(dap, AP_REG_TAR, tar);
155 if (retval != ERROR_OK)
157 dap->ap_tar_value = tar;
159 /* Disable TAR cache when autoincrementing */
160 if (csw & CSW_ADDRINC_MASK)
161 dap->ap_tar_value = -1;
166 * Asynchronous (queued) read of a word from memory or a system register.
168 * @param dap The DAP connected to the MEM-AP performing the read.
169 * @param address Address of the 32-bit word to read; it must be
170 * readable by the currently selected MEM-AP.
171 * @param value points to where the word will be stored when the
172 * transaction queue is flushed (assuming no errors).
174 * @return ERROR_OK for success. Otherwise a fault code.
176 int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
181 /* Use banked addressing (REG_BDx) to avoid some link traffic
182 * (updating TAR) when reading several consecutive addresses.
184 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
185 address & 0xFFFFFFF0);
186 if (retval != ERROR_OK)
189 return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value);
193 * Synchronous read of a word from memory or a system register.
194 * As a side effect, this flushes any queued transactions.
196 * @param dap The DAP connected to the MEM-AP performing the read.
197 * @param address Address of the 32-bit word to read; it must be
198 * readable by the currently selected MEM-AP.
199 * @param value points to where the result will be stored.
201 * @return ERROR_OK for success; *value holds the result.
202 * Otherwise a fault code.
204 int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
209 retval = mem_ap_read_u32(dap, address, value);
210 if (retval != ERROR_OK)
217 * Asynchronous (queued) write of a word to memory or a system register.
219 * @param dap The DAP connected to the MEM-AP.
220 * @param address Address to be written; it must be writable by
221 * the currently selected MEM-AP.
222 * @param value Word that will be written to the address when transaction
223 * queue is flushed (assuming no errors).
225 * @return ERROR_OK for success. Otherwise a fault code.
227 int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
232 /* Use banked addressing (REG_BDx) to avoid some link traffic
233 * (updating TAR) when writing several consecutive addresses.
235 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
236 address & 0xFFFFFFF0);
237 if (retval != ERROR_OK)
240 return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC),
245 * Synchronous write of a word to memory or a system register.
246 * As a side effect, this flushes any queued transactions.
248 * @param dap The DAP connected to the MEM-AP.
249 * @param address Address to be written; it must be writable by
250 * the currently selected MEM-AP.
251 * @param value Word that will be written.
253 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
255 int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
258 int retval = mem_ap_write_u32(dap, address, value);
260 if (retval != ERROR_OK)
266 /*****************************************************************************
268 * mem_ap_write_buf(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address) *
270 * Write a buffer in target order (little endian) *
272 *****************************************************************************/
273 int mem_ap_write_buf_u32(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
275 int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
276 uint32_t adr = address;
277 const uint8_t* pBuffer = buffer;
282 /* if we have an unaligned access - reorder data */
285 for (writecount = 0; writecount < count; writecount++)
289 memcpy(&outvalue, pBuffer, sizeof(uint32_t));
291 for (i = 0; i < 4; i++)
293 *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
297 pBuffer += sizeof(uint32_t);
303 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
304 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
305 if (wcount < blocksize)
308 /* handle unaligned data at 4k boundary */
312 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
313 if (retval != ERROR_OK)
316 for (writecount = 0; writecount < blocksize; writecount++)
318 retval = dap_queue_ap_write(dap, AP_REG_DRW,
319 *(uint32_t *) ((void *) (buffer + 4 * writecount)));
320 if (retval != ERROR_OK)
324 if ((retval = dap_run(dap)) == ERROR_OK)
326 wcount = wcount - blocksize;
327 address = address + 4 * blocksize;
328 buffer = buffer + 4 * blocksize;
337 LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
345 static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap,
346 const uint8_t *buffer, int count, uint32_t address)
348 int retval = ERROR_OK;
349 int wcount, blocksize, writecount, i;
357 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
358 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
360 if (wcount < blocksize)
363 /* handle unaligned data at 4k boundary */
367 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
368 if (retval != ERROR_OK)
370 writecount = blocksize;
374 nbytes = MIN((writecount << 1), 4);
378 retval = mem_ap_write_buf_u16(dap, buffer,
380 if (retval != ERROR_OK)
382 LOG_WARNING("Block write error address "
383 "0x%" PRIx32 ", count 0x%x",
388 address += nbytes >> 1;
393 memcpy(&outvalue, buffer, sizeof(uint32_t));
395 for (i = 0; i < nbytes; i++)
397 *((uint8_t*)buffer + (address & 0x3)) = outvalue;
402 memcpy(&outvalue, buffer, sizeof(uint32_t));
403 retval = dap_queue_ap_write(dap,
404 AP_REG_DRW, outvalue);
405 if (retval != ERROR_OK)
408 if ((retval = dap_run(dap)) != ERROR_OK)
410 LOG_WARNING("Block write error address "
411 "0x%" PRIx32 ", count 0x%x",
417 buffer += nbytes >> 1;
418 writecount -= nbytes >> 1;
420 } while (writecount);
427 int mem_ap_write_buf_u16(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
429 int retval = ERROR_OK;
432 return mem_ap_write_buf_packed_u16(dap, buffer, count, address);
436 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
437 if (retval != ERROR_OK)
440 memcpy(&svalue, buffer, sizeof(uint16_t));
441 uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
442 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
443 if (retval != ERROR_OK)
446 retval = dap_run(dap);
447 if (retval != ERROR_OK)
458 static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap,
459 const uint8_t *buffer, int count, uint32_t address)
461 int retval = ERROR_OK;
462 int wcount, blocksize, writecount, i;
470 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
471 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
473 if (wcount < blocksize)
476 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
477 if (retval != ERROR_OK)
479 writecount = blocksize;
483 nbytes = MIN(writecount, 4);
487 retval = mem_ap_write_buf_u8(dap, buffer, nbytes, address);
488 if (retval != ERROR_OK)
490 LOG_WARNING("Block write error address "
491 "0x%" PRIx32 ", count 0x%x",
501 memcpy(&outvalue, buffer, sizeof(uint32_t));
503 for (i = 0; i < nbytes; i++)
505 *((uint8_t*)buffer + (address & 0x3)) = outvalue;
510 memcpy(&outvalue, buffer, sizeof(uint32_t));
511 retval = dap_queue_ap_write(dap,
512 AP_REG_DRW, outvalue);
513 if (retval != ERROR_OK)
516 if ((retval = dap_run(dap)) != ERROR_OK)
518 LOG_WARNING("Block write error address "
519 "0x%" PRIx32 ", count 0x%x",
526 writecount -= nbytes;
528 } while (writecount);
535 int mem_ap_write_buf_u8(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
537 int retval = ERROR_OK;
540 return mem_ap_write_buf_packed_u8(dap, buffer, count, address);
544 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
545 if (retval != ERROR_OK)
547 uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
548 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
549 if (retval != ERROR_OK)
552 retval = dap_run(dap);
553 if (retval != ERROR_OK)
564 /* FIXME don't import ... this is a temporary workaround for the
565 * mem_ap_read_buf_u32() mess, until it's no longer JTAG-specific.
567 extern int adi_jtag_dp_scan(struct adiv5_dap *dap,
568 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
569 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack);
572 * Synchronously read a block of 32-bit words into a buffer
573 * @param dap The DAP connected to the MEM-AP.
574 * @param buffer where the words will be stored (in host byte order).
575 * @param count How many words to read.
576 * @param address Memory address from which to read words; all the
577 * words must be readable by the currently selected MEM-AP.
579 int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer,
580 int count, uint32_t address)
582 int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
583 uint32_t adr = address;
584 uint8_t* pBuffer = buffer;
591 /* Adjust to read blocks within boundaries aligned to the
592 * TAR autoincrement size (at least 2^10). Autoincrement
593 * mode avoids an extra per-word roundtrip to update TAR.
595 blocksize = max_tar_block_size(dap->tar_autoincr_block,
597 if (wcount < blocksize)
600 /* handle unaligned data at 4k boundary */
604 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE,
606 if (retval != ERROR_OK)
609 /* FIXME remove these three calls to adi_jtag_dp_scan(),
610 * so this routine becomes transport-neutral. Be careful
611 * not to cause performance problems with JTAG; would it
612 * suffice to loop over dap_queue_ap_read(), or would that
613 * be slower when JTAG is the chosen transport?
616 /* Scan out first read */
617 retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
618 DPAP_READ, 0, NULL, NULL);
619 if (retval != ERROR_OK)
621 for (readcount = 0; readcount < blocksize - 1; readcount++)
623 /* Scan out next read; scan in posted value for the
624 * previous one. Assumes read is acked "OK/FAULT",
625 * and CTRL_STAT says that meant "OK".
627 retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
628 DPAP_READ, 0, buffer + 4 * readcount,
630 if (retval != ERROR_OK)
634 /* Scan in last posted value; RDBUFF has no other effect,
635 * assuming ack is OK/FAULT and CTRL_STAT says "OK".
637 retval = adi_jtag_dp_scan(dap, JTAG_DP_DPACC, DP_RDBUFF,
638 DPAP_READ, 0, buffer + 4 * readcount,
640 if (retval != ERROR_OK)
643 retval = dap_run(dap);
644 if (retval != ERROR_OK)
652 LOG_WARNING("Block read error address 0x%" PRIx32, address);
655 wcount = wcount - blocksize;
656 address += 4 * blocksize;
657 buffer += 4 * blocksize;
660 /* if we have an unaligned access - reorder data */
663 for (readcount = 0; readcount < count; readcount++)
667 memcpy(&data, pBuffer, sizeof(uint32_t));
669 for (i = 0; i < 4; i++)
671 *((uint8_t*)pBuffer) =
672 (data >> 8 * (adr & 0x3));
682 static int mem_ap_read_buf_packed_u16(struct adiv5_dap *dap,
683 uint8_t *buffer, int count, uint32_t address)
686 int retval = ERROR_OK;
687 int wcount, blocksize, readcount, i;
695 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
696 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
697 if (wcount < blocksize)
700 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
701 if (retval != ERROR_OK)
704 /* handle unaligned data at 4k boundary */
707 readcount = blocksize;
711 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
712 if (retval != ERROR_OK)
714 if ((retval = dap_run(dap)) != ERROR_OK)
716 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
720 nbytes = MIN((readcount << 1), 4);
722 for (i = 0; i < nbytes; i++)
724 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
729 readcount -= (nbytes >> 1);
738 * Synchronously read a block of 16-bit halfwords into a buffer
739 * @param dap The DAP connected to the MEM-AP.
740 * @param buffer where the halfwords will be stored (in host byte order).
741 * @param count How many halfwords to read.
742 * @param address Memory address from which to read words; all the
743 * words must be readable by the currently selected MEM-AP.
745 int mem_ap_read_buf_u16(struct adiv5_dap *dap, uint8_t *buffer,
746 int count, uint32_t address)
749 int retval = ERROR_OK;
752 return mem_ap_read_buf_packed_u16(dap, buffer, count, address);
756 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
757 if (retval != ERROR_OK)
759 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
760 if (retval != ERROR_OK)
763 retval = dap_run(dap);
764 if (retval != ERROR_OK)
769 for (i = 0; i < 2; i++)
771 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
778 uint16_t svalue = (invalue >> 8 * (address & 0x3));
779 memcpy(buffer, &svalue, sizeof(uint16_t));
789 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
790 * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
792 * The solution is to arrange for a large out/in scan in this loop and
793 * and convert data afterwards.
795 static int mem_ap_read_buf_packed_u8(struct adiv5_dap *dap,
796 uint8_t *buffer, int count, uint32_t address)
799 int retval = ERROR_OK;
800 int wcount, blocksize, readcount, i;
808 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
809 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
811 if (wcount < blocksize)
814 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
815 if (retval != ERROR_OK)
817 readcount = blocksize;
821 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
822 if (retval != ERROR_OK)
824 if ((retval = dap_run(dap)) != ERROR_OK)
826 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
830 nbytes = MIN(readcount, 4);
832 for (i = 0; i < nbytes; i++)
834 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
848 * Synchronously read a block of bytes into a buffer
849 * @param dap The DAP connected to the MEM-AP.
850 * @param buffer where the bytes will be stored.
851 * @param count How many bytes to read.
852 * @param address Memory address from which to read data; all the
853 * data must be readable by the currently selected MEM-AP.
855 int mem_ap_read_buf_u8(struct adiv5_dap *dap, uint8_t *buffer,
856 int count, uint32_t address)
859 int retval = ERROR_OK;
862 return mem_ap_read_buf_packed_u8(dap, buffer, count, address);
866 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
867 if (retval != ERROR_OK)
869 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
870 if (retval != ERROR_OK)
872 retval = dap_run(dap);
873 if (retval != ERROR_OK)
876 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
885 /*--------------------------------------------------------------------*/
886 /* Wrapping function with selection of AP */
887 /*--------------------------------------------------------------------*/
888 int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
889 uint32_t address, uint32_t *value)
891 dap_ap_select(swjdp, ap);
892 return mem_ap_read_u32(swjdp, address, value);
895 int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap,
896 uint32_t address, uint32_t value)
898 dap_ap_select(swjdp, ap);
899 return mem_ap_write_u32(swjdp, address, value);
902 int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
903 uint32_t address, uint32_t *value)
905 dap_ap_select(swjdp, ap);
906 return mem_ap_read_atomic_u32(swjdp, address, value);
909 int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
910 uint32_t address, uint32_t value)
912 dap_ap_select(swjdp, ap);
913 return mem_ap_write_atomic_u32(swjdp, address, value);
916 int mem_ap_sel_read_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
917 uint8_t *buffer, int count, uint32_t address)
919 dap_ap_select(swjdp, ap);
920 return mem_ap_read_buf_u8(swjdp, buffer, count, address);
923 int mem_ap_sel_read_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
924 uint8_t *buffer, int count, uint32_t address)
926 dap_ap_select(swjdp, ap);
927 return mem_ap_read_buf_u16(swjdp, buffer, count, address);
930 int mem_ap_sel_read_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
931 uint8_t *buffer, int count, uint32_t address)
933 dap_ap_select(swjdp, ap);
934 return mem_ap_read_buf_u32(swjdp, buffer, count, address);
937 int mem_ap_sel_write_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
938 const uint8_t *buffer, int count, uint32_t address)
940 dap_ap_select(swjdp, ap);
941 return mem_ap_write_buf_u8(swjdp, buffer, count, address);
944 int mem_ap_sel_write_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
945 const uint8_t *buffer, int count, uint32_t address)
947 dap_ap_select(swjdp, ap);
948 return mem_ap_write_buf_u16(swjdp, buffer, count, address);
951 int mem_ap_sel_write_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
952 const uint8_t *buffer, int count, uint32_t address)
954 dap_ap_select(swjdp, ap);
955 return mem_ap_write_buf_u32(swjdp, buffer, count, address);
958 #define MDM_REG_STAT 0x00
959 #define MDM_REG_CTRL 0x04
960 #define MDM_REG_ID 0xfc
962 #define MDM_STAT_FMEACK (1<<0)
963 #define MDM_STAT_FREADY (1<<1)
964 #define MDM_STAT_SYSSEC (1<<2)
965 #define MDM_STAT_SYSRES (1<<3)
966 #define MDM_STAT_FMEEN (1<<5)
967 #define MDM_STAT_BACKDOOREN (1<<6)
968 #define MDM_STAT_LPEN (1<<7)
969 #define MDM_STAT_VLPEN (1<<8)
970 #define MDM_STAT_LLSMODEXIT (1<<9)
971 #define MDM_STAT_VLLSXMODEXIT (1<<10)
972 #define MDM_STAT_CORE_HALTED (1<<16)
973 #define MDM_STAT_CORE_SLEEPDEEP (1<<17)
974 #define MDM_STAT_CORESLEEPING (1<<18)
976 #define MEM_CTRL_FMEIP (1<<0)
977 #define MEM_CTRL_DBG_DIS (1<<1)
978 #define MEM_CTRL_DBG_REQ (1<<2)
979 #define MEM_CTRL_SYS_RES_REQ (1<<3)
980 #define MEM_CTRL_CORE_HOLD_RES (1<<4)
981 #define MEM_CTRL_VLLSX_DBG_REQ (1<<5)
982 #define MEM_CTRL_VLLSX_DBG_ACK (1<<6)
983 #define MEM_CTRL_VLLSX_STAT_ACK (1<<7)
988 int dap_syssec_kinetis_mdmap(struct adiv5_dap *dap)
992 enum reset_types jtag_reset_config = jtag_get_reset_config();
994 dap_ap_select(dap, 1);
996 /* first check mdm-ap id register */
997 retval = dap_queue_ap_read(dap, MDM_REG_ID, &val);
998 if (retval != ERROR_OK)
1002 if ( val != 0x001C0000 )
1004 LOG_DEBUG("id doesn't match %08X != 0x001C0000",val);
1005 dap_ap_select(dap, 0);
1009 /* read and parse status register
1010 * it's important that the device is out of
1013 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
1014 if (retval != ERROR_OK)
1018 LOG_DEBUG("MDM_REG_STAT %08X",val);
1020 if ( (val & (MDM_STAT_SYSSEC|MDM_STAT_FREADY)) != (MDM_STAT_FREADY) )
1022 LOG_DEBUG("MDMAP: system is secured, masserase needed");
1024 if ( !(val & MDM_STAT_FMEEN) )
1026 LOG_DEBUG("MDMAP: masserase is disabled");
1030 /* we need to assert reset */
1031 if ( jtag_reset_config & RESET_HAS_SRST )
1033 /* default to asserting srst */
1034 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
1036 jtag_add_reset(1, 1);
1040 jtag_add_reset(0, 1);
1045 LOG_DEBUG("SRST not configured");
1046 dap_ap_select(dap, 0);
1052 retval = dap_queue_ap_write(dap, MDM_REG_CTRL, MEM_CTRL_FMEIP);
1053 if (retval != ERROR_OK)
1056 /* read status register and wait for ready */
1057 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
1058 if (retval != ERROR_OK)
1061 LOG_DEBUG("MDM_REG_STAT %08X",val);
1069 retval = dap_queue_ap_write(dap, MDM_REG_CTRL, 0);
1070 if (retval != ERROR_OK)
1073 /* read status register */
1074 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
1075 if (retval != ERROR_OK)
1078 LOG_DEBUG("MDM_REG_STAT %08X",val);
1079 /* read control register and wait for ready */
1080 retval = dap_queue_ap_read(dap, MDM_REG_CTRL, &val);
1081 if (retval != ERROR_OK)
1084 LOG_DEBUG("MDM_REG_CTRL %08X",val);
1092 dap_ap_select(dap, 0);
1098 struct dap_syssec_filter {
1102 int (*dap_init)(struct adiv5_dap *dap);
1106 static struct dap_syssec_filter dap_syssec_filter_data[] = {
1107 { 0x4BA00477, dap_syssec_kinetis_mdmap }
1114 int dap_syssec(struct adiv5_dap *dap)
1117 struct jtag_tap *tap;
1119 for(i=0;i<sizeof(dap_syssec_filter_data);i++)
1121 tap = dap->jtag_info->tap;
1125 if ( tap->hasidcode && (dap_syssec_filter_data[i].idcode == tap->idcode) )
1127 LOG_DEBUG("DAP: mdmap_init for idcode: %08x",tap->idcode);
1128 dap_syssec_filter_data[i].dap_init(dap);
1130 tap = tap->next_tap;
1137 /*--------------------------------------------------------------------------*/
1140 /* FIXME don't import ... just initialize as
1141 * part of DAP transport setup
1143 extern const struct dap_ops jtag_dp_ops;
1145 /*--------------------------------------------------------------------------*/
1148 * Initialize a DAP. This sets up the power domains, prepares the DP
1149 * for further use, and arranges to use AP #0 for all AP operations
1150 * until dap_ap-select() changes that policy.
1152 * @param dap The DAP being initialized.
1154 * @todo Rename this. We also need an initialization scheme which account
1155 * for SWD transports not just JTAG; that will need to address differences
1156 * in layering. (JTAG is useful without any debug target; but not SWD.)
1157 * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
1159 int ahbap_debugport_init(struct adiv5_dap *dap)
1167 /* JTAG-DP or SWJ-DP, in JTAG mode
1168 * ... for SWD mode this is patched as part
1169 * of link switchover
1172 dap->ops = &jtag_dp_ops;
1174 /* Default MEM-AP setup.
1176 * REVISIT AP #0 may be an inappropriate default for this.
1177 * Should we probe, or take a hint from the caller?
1178 * Presumably we can ignore the possibility of multiple APs.
1180 dap->ap_current = !0;
1181 dap_ap_select(dap, 0);
1183 /* DP initialization */
1185 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1186 if (retval != ERROR_OK)
1189 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
1190 if (retval != ERROR_OK)
1193 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1194 if (retval != ERROR_OK)
1197 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
1198 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
1199 if (retval != ERROR_OK)
1202 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
1203 if (retval != ERROR_OK)
1205 if ((retval = dap_run(dap)) != ERROR_OK)
1208 /* Check that we have debug power domains activated */
1209 while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
1211 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
1212 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
1213 if (retval != ERROR_OK)
1215 if ((retval = dap_run(dap)) != ERROR_OK)
1220 while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
1222 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
1223 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
1224 if (retval != ERROR_OK)
1226 if ((retval = dap_run(dap)) != ERROR_OK)
1231 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1232 if (retval != ERROR_OK)
1234 /* With debug power on we can activate OVERRUN checking */
1235 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
1236 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
1237 if (retval != ERROR_OK)
1239 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1240 if (retval != ERROR_OK)
1248 /* CID interpretation -- see ARM IHI 0029B section 3
1249 * and ARM IHI 0031A table 13-3.
1251 static const char *class_description[16] ={
1252 "Reserved", "ROM table", "Reserved", "Reserved",
1253 "Reserved", "Reserved", "Reserved", "Reserved",
1254 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1255 "Reserved", "OptimoDE DESS",
1256 "Generic IP component", "PrimeCell or System component"
1260 is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
1262 return cid3 == 0xb1 && cid2 == 0x05
1263 && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1266 int dap_get_debugbase(struct adiv5_dap *dap, int ap,
1267 uint32_t *out_dbgbase, uint32_t *out_apid)
1271 uint32_t dbgbase, apid;
1273 /* AP address is in bits 31:24 of DP_SELECT */
1275 return ERROR_COMMAND_SYNTAX_ERROR;
1277 ap_old = dap->ap_current;
1278 dap_ap_select(dap, ap);
1280 retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase);
1281 if (retval != ERROR_OK)
1283 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1284 if (retval != ERROR_OK)
1286 retval = dap_run(dap);
1287 if (retval != ERROR_OK)
1290 /* Excavate the device ID code */
1291 struct jtag_tap *tap = dap->jtag_info->tap;
1292 while (tap != NULL) {
1295 tap = tap->next_tap;
1297 if (tap == NULL || !tap->hasidcode)
1300 dap_ap_select(dap, ap_old);
1302 /* The asignment happens only here to prevent modification of these
1303 * values before they are certain. */
1304 *out_dbgbase = dbgbase;
1310 int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
1311 uint32_t dbgbase, uint8_t type, uint32_t *addr)
1314 uint32_t romentry, entry_offset = 0, component_base, devtype;
1315 int retval = ERROR_FAIL;
1318 return ERROR_COMMAND_SYNTAX_ERROR;
1320 ap_old = dap->ap_current;
1321 dap_ap_select(dap, ap);
1325 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) |
1326 entry_offset, &romentry);
1327 if (retval != ERROR_OK)
1330 component_base = (dbgbase & 0xFFFFF000)
1331 + (romentry & 0xFFFFF000);
1333 if (romentry & 0x1) {
1334 retval = mem_ap_read_atomic_u32(dap,
1335 (component_base & 0xfffff000) | 0xfcc,
1337 if ((devtype & 0xff) == type) {
1338 *addr = component_base;
1344 } while (romentry > 0);
1346 dap_ap_select(dap, ap_old);
1351 static int dap_info_command(struct command_context *cmd_ctx,
1352 struct adiv5_dap *dap, int ap)
1355 uint32_t dbgbase = 0, apid = 0; /* Silence gcc by initializing */
1356 int romtable_present = 0;
1360 retval = dap_get_debugbase(dap, ap, &dbgbase, &apid);
1361 if (retval != ERROR_OK)
1364 ap_old = dap->ap_current;
1365 dap_ap_select(dap, ap);
1367 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1368 mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1369 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1375 command_print(cmd_ctx, "\tType is JTAG-AP");
1378 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1381 command_print(cmd_ctx, "\tType is MEM-AP APB");
1384 command_print(cmd_ctx, "\tUnknown AP type");
1388 /* NOTE: a MEM-AP may have a single CoreSight component that's
1389 * not a ROM table ... or have no such components at all.
1392 command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32,
1397 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap);
1400 romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1401 if (romtable_present)
1403 uint32_t cid0,cid1,cid2,cid3,memtype,romentry;
1404 uint16_t entry_offset;
1406 /* bit 16 of apid indicates a memory access port */
1408 command_print(cmd_ctx, "\tValid ROM table present");
1410 command_print(cmd_ctx, "\tROM table in legacy format");
1412 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1413 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1414 if (retval != ERROR_OK)
1416 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1417 if (retval != ERROR_OK)
1419 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1420 if (retval != ERROR_OK)
1422 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1423 if (retval != ERROR_OK)
1425 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1426 if (retval != ERROR_OK)
1428 retval = dap_run(dap);
1429 if (retval != ERROR_OK)
1432 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1433 command_print(cmd_ctx, "\tCID3 0x%2.2x"
1437 (unsigned) cid3, (unsigned)cid2,
1438 (unsigned) cid1, (unsigned) cid0);
1440 command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1442 command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1443 "Dedicated debug bus.");
1445 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1449 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1450 if (retval != ERROR_OK)
1452 command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
1455 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1456 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1457 uint32_t component_base;
1461 component_base = (dbgbase & 0xFFFFF000)
1462 + (romentry & 0xFFFFF000);
1464 /* IDs are in last 4K section */
1467 retval = mem_ap_read_atomic_u32(dap,
1468 component_base + 0xFE0, &c_pid0);
1469 if (retval != ERROR_OK)
1472 retval = mem_ap_read_atomic_u32(dap,
1473 component_base + 0xFE4, &c_pid1);
1474 if (retval != ERROR_OK)
1477 retval = mem_ap_read_atomic_u32(dap,
1478 component_base + 0xFE8, &c_pid2);
1479 if (retval != ERROR_OK)
1482 retval = mem_ap_read_atomic_u32(dap,
1483 component_base + 0xFEC, &c_pid3);
1484 if (retval != ERROR_OK)
1487 retval = mem_ap_read_atomic_u32(dap,
1488 component_base + 0xFD0, &c_pid4);
1489 if (retval != ERROR_OK)
1493 retval = mem_ap_read_atomic_u32(dap,
1494 component_base + 0xFF0, &c_cid0);
1495 if (retval != ERROR_OK)
1498 retval = mem_ap_read_atomic_u32(dap,
1499 component_base + 0xFF4, &c_cid1);
1500 if (retval != ERROR_OK)
1503 retval = mem_ap_read_atomic_u32(dap,
1504 component_base + 0xFF8, &c_cid2);
1505 if (retval != ERROR_OK)
1508 retval = mem_ap_read_atomic_u32(dap,
1509 component_base + 0xFFC, &c_cid3);
1510 if (retval != ERROR_OK)
1515 command_print(cmd_ctx,
1516 "\t\tComponent base address 0x%" PRIx32
1517 ", start address 0x%" PRIx32,
1519 /* component may take multiple 4K pages */
1520 component_base - 0x1000*(c_pid4 >> 4));
1521 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1522 (int) (c_cid1 >> 4) & 0xf,
1523 /* See ARM IHI 0029B Table 3-3 */
1524 class_description[(c_cid1 >> 4) & 0xf]);
1526 /* CoreSight component? */
1527 if (((c_cid1 >> 4) & 0x0f) == 9) {
1530 char *major = "Reserved", *subtype = "Reserved";
1532 retval = mem_ap_read_atomic_u32(dap,
1533 (component_base & 0xfffff000) | 0xfcc,
1535 if (retval != ERROR_OK)
1537 minor = (devtype >> 4) & 0x0f;
1538 switch (devtype & 0x0f) {
1540 major = "Miscellaneous";
1546 subtype = "Validation component";
1551 major = "Trace Sink";
1565 major = "Trace Link";
1571 subtype = "Funnel, router";
1577 subtype = "FIFO, buffer";
1582 major = "Trace Source";
1588 subtype = "Processor";
1594 subtype = "Engine/Coprocessor";
1602 major = "Debug Control";
1608 subtype = "Trigger Matrix";
1611 subtype = "Debug Auth";
1616 major = "Debug Logic";
1622 subtype = "Processor";
1628 subtype = "Engine/Coprocessor";
1633 command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1634 (unsigned) (devtype & 0xff),
1636 /* REVISIT also show 0xfc8 DevId */
1639 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1640 command_print(cmd_ctx,
1649 command_print(cmd_ctx,
1650 "\t\tPeripheral ID[4..0] = hex "
1651 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1652 (int) c_pid4, (int) c_pid3, (int) c_pid2,
1653 (int) c_pid1, (int) c_pid0);
1655 /* Part number interpretations are from Cortex
1656 * core specs, the CoreSight components TRM
1657 * (ARM DDI 0314H), CoreSight System Design
1658 * Guide (ARM DGI 0012D) and ETM specs; also
1659 * from chip observation (e.g. TI SDTI).
1661 part_num = (c_pid0 & 0xff);
1662 part_num |= (c_pid1 & 0x0f) << 8;
1665 type = "Cortex-M3 NVIC";
1666 full = "(Interrupt Controller)";
1669 type = "Cortex-M3 ITM";
1670 full = "(Instrumentation Trace Module)";
1673 type = "Cortex-M3 DWT";
1674 full = "(Data Watchpoint and Trace)";
1677 type = "Cortex-M3 FBP";
1678 full = "(Flash Patch and Breakpoint)";
1681 type = "CoreSight ETM11";
1682 full = "(Embedded Trace)";
1684 // case 0x113: what?
1685 case 0x120: /* from OMAP3 memmap */
1687 full = "(System Debug Trace Interface)";
1689 case 0x343: /* from OMAP3 memmap */
1694 type = "Coresight CTI";
1695 full = "(Cross Trigger)";
1698 type = "Coresight ETB";
1699 full = "(Trace Buffer)";
1702 type = "Coresight CSTF";
1703 full = "(Trace Funnel)";
1706 type = "CoreSight ETM9";
1707 full = "(Embedded Trace)";
1710 type = "Coresight TPIU";
1711 full = "(Trace Port Interface Unit)";
1714 type = "Cortex-A8 ETM";
1715 full = "(Embedded Trace)";
1718 type = "Cortex-A8 CTI";
1719 full = "(Cross Trigger)";
1722 type = "Cortex-M3 TPIU";
1723 full = "(Trace Port Interface Unit)";
1726 type = "Cortex-M3 ETM";
1727 full = "(Embedded Trace)";
1730 type = "Cortex-R4 ETM";
1731 full = "(Embedded Trace)";
1734 type = "Cortex-A8 Debug";
1735 full = "(Debug Unit)";
1738 type = "-*- unrecognized -*-";
1742 command_print(cmd_ctx, "\t\tPart is %s %s",
1748 command_print(cmd_ctx, "\t\tComponent not present");
1750 command_print(cmd_ctx, "\t\tEnd of ROM table");
1753 } while (romentry > 0);
1757 command_print(cmd_ctx, "\tNo ROM table present");
1759 dap_ap_select(dap, ap_old);
1764 COMMAND_HANDLER(handle_dap_info_command)
1766 struct target *target = get_current_target(CMD_CTX);
1767 struct arm *arm = target_to_arm(target);
1768 struct adiv5_dap *dap = arm->dap;
1776 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1779 return ERROR_COMMAND_SYNTAX_ERROR;
1782 return dap_info_command(CMD_CTX, dap, apsel);
1785 COMMAND_HANDLER(dap_baseaddr_command)
1787 struct target *target = get_current_target(CMD_CTX);
1788 struct arm *arm = target_to_arm(target);
1789 struct adiv5_dap *dap = arm->dap;
1791 uint32_t apsel, baseaddr;
1799 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1800 /* AP address is in bits 31:24 of DP_SELECT */
1802 return ERROR_COMMAND_SYNTAX_ERROR;
1805 return ERROR_COMMAND_SYNTAX_ERROR;
1808 dap_ap_select(dap, apsel);
1810 /* NOTE: assumes we're talking to a MEM-AP, which
1811 * has a base address. There are other kinds of AP,
1812 * though they're not common for now. This should
1813 * use the ID register to verify it's a MEM-AP.
1815 retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
1816 if (retval != ERROR_OK)
1818 retval = dap_run(dap);
1819 if (retval != ERROR_OK)
1822 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1827 COMMAND_HANDLER(dap_memaccess_command)
1829 struct target *target = get_current_target(CMD_CTX);
1830 struct arm *arm = target_to_arm(target);
1831 struct adiv5_dap *dap = arm->dap;
1833 uint32_t memaccess_tck;
1837 memaccess_tck = dap->memaccess_tck;
1840 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1843 return ERROR_COMMAND_SYNTAX_ERROR;
1845 dap->memaccess_tck = memaccess_tck;
1847 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1848 dap->memaccess_tck);
1853 COMMAND_HANDLER(dap_apsel_command)
1855 struct target *target = get_current_target(CMD_CTX);
1856 struct arm *arm = target_to_arm(target);
1857 struct adiv5_dap *dap = arm->dap;
1859 uint32_t apsel, apid;
1867 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1868 /* AP address is in bits 31:24 of DP_SELECT */
1870 return ERROR_COMMAND_SYNTAX_ERROR;
1873 return ERROR_COMMAND_SYNTAX_ERROR;
1877 dap_ap_select(dap, apsel);
1879 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1880 if (retval != ERROR_OK)
1882 retval = dap_run(dap);
1883 if (retval != ERROR_OK)
1886 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1892 COMMAND_HANDLER(dap_apid_command)
1894 struct target *target = get_current_target(CMD_CTX);
1895 struct arm *arm = target_to_arm(target);
1896 struct adiv5_dap *dap = arm->dap;
1898 uint32_t apsel, apid;
1906 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1907 /* AP address is in bits 31:24 of DP_SELECT */
1909 return ERROR_COMMAND_SYNTAX_ERROR;
1912 return ERROR_COMMAND_SYNTAX_ERROR;
1915 dap_ap_select(dap, apsel);
1917 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1918 if (retval != ERROR_OK)
1920 retval = dap_run(dap);
1921 if (retval != ERROR_OK)
1924 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1929 static const struct command_registration dap_commands[] = {
1932 .handler = handle_dap_info_command,
1933 .mode = COMMAND_EXEC,
1934 .help = "display ROM table for MEM-AP "
1935 "(default currently selected AP)",
1936 .usage = "[ap_num]",
1940 .handler = dap_apsel_command,
1941 .mode = COMMAND_EXEC,
1942 .help = "Set the currently selected AP (default 0) "
1943 "and display the result",
1944 .usage = "[ap_num]",
1948 .handler = dap_apid_command,
1949 .mode = COMMAND_EXEC,
1950 .help = "return ID register from AP "
1951 "(default currently selected AP)",
1952 .usage = "[ap_num]",
1956 .handler = dap_baseaddr_command,
1957 .mode = COMMAND_EXEC,
1958 .help = "return debug base address from MEM-AP "
1959 "(default currently selected AP)",
1960 .usage = "[ap_num]",
1963 .name = "memaccess",
1964 .handler = dap_memaccess_command,
1965 .mode = COMMAND_EXEC,
1966 .help = "set/get number of extra tck for MEM-AP memory "
1967 "bus access [0-255]",
1968 .usage = "[cycles]",
1970 COMMAND_REGISTRATION_DONE
1973 const struct command_registration dap_command_handlers[] = {
1976 .mode = COMMAND_EXEC,
1977 .help = "DAP command group",
1978 .chain = dap_commands,
1980 COMMAND_REGISTRATION_DONE