1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * Copyright (C) 2009-2010 by David Brownell *
13 * Copyright (C) 2013 by Andreas Fritiofson *
14 * andreas.fritiofson@gmail.com *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published by *
18 * the Free Software Foundation; either version 2 of the License, or *
19 * (at your option) any later version. *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
26 * You should have received a copy of the GNU General Public License *
27 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
28 ***************************************************************************/
32 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
33 * debugging architecture. Compared with previous versions, this includes
34 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
35 * transport, and focusses on memory mapped resources as defined by the
36 * CoreSight architecture.
38 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
39 * basic components: a Debug Port (DP) transporting messages to and from a
40 * debugger, and an Access Port (AP) accessing resources. Three types of DP
41 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
42 * One uses only SWD for communication, and is called SW-DP. The third can
43 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
44 * is used to access memory mapped resources and is called a MEM-AP. Also a
45 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
47 * This programming interface allows DAP pipelined operations through a
48 * transaction queue. This primarily affects AP operations (such as using
49 * a MEM-AP to access memory or registers). If the current transaction has
50 * not finished by the time the next one must begin, and the ORUNDETECT bit
51 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
52 * further AP operations will fail. There are two basic methods to avoid
53 * such overrun errors. One involves polling for status instead of using
54 * transaction piplining. The other involves adding delays to ensure the
55 * AP has enough time to complete one operation before starting the next
56 * one. (For JTAG these delays are controlled by memaccess_tck.)
60 * Relevant specifications from ARM include:
62 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
63 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
65 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
66 * Cortex-M3(tm) TRM, ARM DDI 0337G
73 #include "jtag/interface.h"
75 #include "arm_adi_v5.h"
76 #include <helper/jep106.h>
77 #include <helper/time_support.h>
78 #include <helper/list.h>
80 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
83 uint32_t tar_block_size(uint32_t address)
84 Return the largest block starting at address that does not cross a tar block size alignment boundary
86 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
88 return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
91 /***************************************************************************
93 * DP and MEM-AP register access through APACC and DPACC *
95 ***************************************************************************/
97 static int mem_ap_setup_csw(struct adiv5_ap *ap, uint32_t csw)
99 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT |
102 if (csw != ap->csw_value) {
103 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
104 int retval = dap_queue_ap_write(ap, MEM_AP_REG_CSW, csw);
105 if (retval != ERROR_OK)
112 static int mem_ap_setup_tar(struct adiv5_ap *ap, uint32_t tar)
114 if (tar != ap->tar_value ||
115 (ap->csw_value & CSW_ADDRINC_MASK)) {
116 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
117 int retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR, tar);
118 if (retval != ERROR_OK)
126 * Queue transactions setting up transfer parameters for the
127 * currently selected MEM-AP.
129 * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2
130 * initiate data reads or writes using memory or peripheral addresses.
131 * If the CSW is configured for it, the TAR may be automatically
132 * incremented after each transfer.
134 * @param ap The MEM-AP.
135 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
136 * matches the cached value, the register is not changed.
137 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
138 * matches the cached address, the register is not changed.
140 * @return ERROR_OK if the transaction was properly queued, else a fault code.
142 static int mem_ap_setup_transfer(struct adiv5_ap *ap, uint32_t csw, uint32_t tar)
145 retval = mem_ap_setup_csw(ap, csw);
146 if (retval != ERROR_OK)
148 retval = mem_ap_setup_tar(ap, tar);
149 if (retval != ERROR_OK)
155 * Asynchronous (queued) read of a word from memory or a system register.
157 * @param ap The MEM-AP to access.
158 * @param address Address of the 32-bit word to read; it must be
159 * readable by the currently selected MEM-AP.
160 * @param value points to where the word will be stored when the
161 * transaction queue is flushed (assuming no errors).
163 * @return ERROR_OK for success. Otherwise a fault code.
165 int mem_ap_read_u32(struct adiv5_ap *ap, uint32_t address,
170 /* Use banked addressing (REG_BDx) to avoid some link traffic
171 * (updating TAR) when reading several consecutive addresses.
173 retval = mem_ap_setup_transfer(ap, CSW_32BIT | CSW_ADDRINC_OFF,
174 address & 0xFFFFFFF0);
175 if (retval != ERROR_OK)
178 return dap_queue_ap_read(ap, MEM_AP_REG_BD0 | (address & 0xC), value);
182 * Synchronous read of a word from memory or a system register.
183 * As a side effect, this flushes any queued transactions.
185 * @param ap The MEM-AP to access.
186 * @param address Address of the 32-bit word to read; it must be
187 * readable by the currently selected MEM-AP.
188 * @param value points to where the result will be stored.
190 * @return ERROR_OK for success; *value holds the result.
191 * Otherwise a fault code.
193 int mem_ap_read_atomic_u32(struct adiv5_ap *ap, uint32_t address,
198 retval = mem_ap_read_u32(ap, address, value);
199 if (retval != ERROR_OK)
202 return dap_run(ap->dap);
206 * Asynchronous (queued) write of a word to memory or a system register.
208 * @param ap The MEM-AP to access.
209 * @param address Address to be written; it must be writable by
210 * the currently selected MEM-AP.
211 * @param value Word that will be written to the address when transaction
212 * queue is flushed (assuming no errors).
214 * @return ERROR_OK for success. Otherwise a fault code.
216 int mem_ap_write_u32(struct adiv5_ap *ap, uint32_t address,
221 /* Use banked addressing (REG_BDx) to avoid some link traffic
222 * (updating TAR) when writing several consecutive addresses.
224 retval = mem_ap_setup_transfer(ap, CSW_32BIT | CSW_ADDRINC_OFF,
225 address & 0xFFFFFFF0);
226 if (retval != ERROR_OK)
229 return dap_queue_ap_write(ap, MEM_AP_REG_BD0 | (address & 0xC),
234 * Synchronous write of a word to memory or a system register.
235 * As a side effect, this flushes any queued transactions.
237 * @param ap The MEM-AP to access.
238 * @param address Address to be written; it must be writable by
239 * the currently selected MEM-AP.
240 * @param value Word that will be written.
242 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
244 int mem_ap_write_atomic_u32(struct adiv5_ap *ap, uint32_t address,
247 int retval = mem_ap_write_u32(ap, address, value);
249 if (retval != ERROR_OK)
252 return dap_run(ap->dap);
256 * Synchronous write of a block of memory, using a specific access size.
258 * @param ap The MEM-AP to access.
259 * @param buffer The data buffer to write. No particular alignment is assumed.
260 * @param size Which access size to use, in bytes. 1, 2 or 4.
261 * @param count The number of writes to do (in size units, not bytes).
262 * @param address Address to be written; it must be writable by the currently selected MEM-AP.
263 * @param addrinc Whether the target address should be increased for each write or not. This
264 * should normally be true, except when writing to e.g. a FIFO.
265 * @return ERROR_OK on success, otherwise an error code.
267 static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count,
268 uint32_t address, bool addrinc)
270 struct adiv5_dap *dap = ap->dap;
271 size_t nbytes = size * count;
272 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
277 /* TI BE-32 Quirks mode:
278 * Writes on big-endian TMS570 behave very strangely. Observed behavior:
279 * size write address bytes written in order
280 * 4 TAR ^ 0 (val >> 24), (val >> 16), (val >> 8), (val)
281 * 2 TAR ^ 2 (val >> 8), (val)
283 * For example, if you attempt to write a single byte to address 0, the processor
284 * will actually write a byte to address 3.
286 * To make writes of size < 4 work as expected, we xor a value with the address before
287 * setting the TAP, and we set the TAP after every transfer rather then relying on
288 * address increment. */
291 csw_size = CSW_32BIT;
293 } else if (size == 2) {
294 csw_size = CSW_16BIT;
295 addr_xor = dap->ti_be_32_quirks ? 2 : 0;
296 } else if (size == 1) {
298 addr_xor = dap->ti_be_32_quirks ? 3 : 0;
300 return ERROR_TARGET_UNALIGNED_ACCESS;
303 if (ap->unaligned_access_bad && (address % size != 0))
304 return ERROR_TARGET_UNALIGNED_ACCESS;
306 retval = mem_ap_setup_tar(ap, address ^ addr_xor);
307 if (retval != ERROR_OK)
311 uint32_t this_size = size;
313 /* Select packed transfer if possible */
314 if (addrinc && ap->packed_transfers && nbytes >= 4
315 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
317 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
319 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
322 if (retval != ERROR_OK)
325 /* How many source bytes each transfer will consume, and their location in the DRW,
326 * depends on the type of transfer and alignment. See ARM document IHI0031C. */
327 uint32_t outvalue = 0;
328 if (dap->ti_be_32_quirks) {
331 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
332 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
333 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
334 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
337 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
338 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
341 outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (address++ & 3) ^ addr_xor);
347 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
348 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
350 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
352 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
358 retval = dap_queue_ap_write(ap, MEM_AP_REG_DRW, outvalue);
359 if (retval != ERROR_OK)
362 /* Rewrite TAR if it wrapped or we're xoring addresses */
363 if (addrinc && (addr_xor || (address % ap->tar_autoincr_block < size && nbytes > 0))) {
364 retval = mem_ap_setup_tar(ap, address ^ addr_xor);
365 if (retval != ERROR_OK)
370 /* REVISIT: Might want to have a queued version of this function that does not run. */
371 if (retval == ERROR_OK)
372 retval = dap_run(dap);
374 if (retval != ERROR_OK) {
376 if (dap_queue_ap_read(ap, MEM_AP_REG_TAR, &tar) == ERROR_OK
377 && dap_run(dap) == ERROR_OK)
378 LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
380 LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
387 * Synchronous read of a block of memory, using a specific access size.
389 * @param ap The MEM-AP to access.
390 * @param buffer The data buffer to receive the data. No particular alignment is assumed.
391 * @param size Which access size to use, in bytes. 1, 2 or 4.
392 * @param count The number of reads to do (in size units, not bytes).
393 * @param address Address to be read; it must be readable by the currently selected MEM-AP.
394 * @param addrinc Whether the target address should be increased after each read or not. This
395 * should normally be true, except when reading from e.g. a FIFO.
396 * @return ERROR_OK on success, otherwise an error code.
398 static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count,
399 uint32_t adr, bool addrinc)
401 struct adiv5_dap *dap = ap->dap;
402 size_t nbytes = size * count;
403 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
405 uint32_t address = adr;
408 /* TI BE-32 Quirks mode:
409 * Reads on big-endian TMS570 behave strangely differently than writes.
410 * They read from the physical address requested, but with DRW byte-reversed.
411 * For example, a byte read from address 0 will place the result in the high bytes of DRW.
412 * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
416 csw_size = CSW_32BIT;
418 csw_size = CSW_16BIT;
422 return ERROR_TARGET_UNALIGNED_ACCESS;
424 if (ap->unaligned_access_bad && (adr % size != 0))
425 return ERROR_TARGET_UNALIGNED_ACCESS;
427 /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
428 * over-allocation if packed transfers are going to be used, but determining the real need at
429 * this point would be messy. */
430 uint32_t *read_buf = malloc(count * sizeof(uint32_t));
431 uint32_t *read_ptr = read_buf;
432 if (read_buf == NULL) {
433 LOG_ERROR("Failed to allocate read buffer");
437 retval = mem_ap_setup_tar(ap, address);
438 if (retval != ERROR_OK) {
443 /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
444 * useful bytes it contains, and their location in the word, depends on the type of transfer
447 uint32_t this_size = size;
449 /* Select packed transfer if possible */
450 if (addrinc && ap->packed_transfers && nbytes >= 4
451 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
453 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
455 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
457 if (retval != ERROR_OK)
460 retval = dap_queue_ap_read(ap, MEM_AP_REG_DRW, read_ptr++);
461 if (retval != ERROR_OK)
465 address += this_size;
467 /* Rewrite TAR if it wrapped */
468 if (addrinc && address % ap->tar_autoincr_block < size && nbytes > 0) {
469 retval = mem_ap_setup_tar(ap, address);
470 if (retval != ERROR_OK)
475 if (retval == ERROR_OK)
476 retval = dap_run(dap);
480 nbytes = size * count;
483 /* If something failed, read TAR to find out how much data was successfully read, so we can
484 * at least give the caller what we have. */
485 if (retval != ERROR_OK) {
487 if (dap_queue_ap_read(ap, MEM_AP_REG_TAR, &tar) == ERROR_OK
488 && dap_run(dap) == ERROR_OK) {
489 LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
490 if (nbytes > tar - address)
491 nbytes = tar - address;
493 LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
498 /* Replay loop to populate caller's buffer from the correct word and byte lane */
500 uint32_t this_size = size;
502 if (addrinc && ap->packed_transfers && nbytes >= 4
503 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
507 if (dap->ti_be_32_quirks) {
510 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
511 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
513 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
515 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
520 *buffer++ = *read_ptr >> 8 * (address++ & 3);
521 *buffer++ = *read_ptr >> 8 * (address++ & 3);
523 *buffer++ = *read_ptr >> 8 * (address++ & 3);
525 *buffer++ = *read_ptr >> 8 * (address++ & 3);
537 int mem_ap_read_buf(struct adiv5_ap *ap,
538 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
540 return mem_ap_read(ap, buffer, size, count, address, true);
543 int mem_ap_write_buf(struct adiv5_ap *ap,
544 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
546 return mem_ap_write(ap, buffer, size, count, address, true);
549 int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
550 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
552 return mem_ap_read(ap, buffer, size, count, address, false);
555 int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
556 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
558 return mem_ap_write(ap, buffer, size, count, address, false);
561 /*--------------------------------------------------------------------------*/
564 #define DAP_POWER_DOMAIN_TIMEOUT (10)
566 /* FIXME don't import ... just initialize as
567 * part of DAP transport setup
569 extern const struct dap_ops jtag_dp_ops;
571 /*--------------------------------------------------------------------------*/
576 struct adiv5_dap *dap_init(void)
578 struct adiv5_dap *dap = calloc(1, sizeof(struct adiv5_dap));
580 /* Set up with safe defaults */
581 for (i = 0; i <= 255; i++) {
582 dap->ap[i].dap = dap;
583 dap->ap[i].ap_num = i;
584 /* memaccess_tck max is 255 */
585 dap->ap[i].memaccess_tck = 255;
586 /* Number of bits for tar autoincrement, impl. dep. at least 10 */
587 dap->ap[i].tar_autoincr_block = (1<<10);
589 INIT_LIST_HEAD(&dap->cmd_journal);
594 * Initialize a DAP. This sets up the power domains, prepares the DP
595 * for further use and activates overrun checking.
597 * @param dap The DAP being initialized.
599 int dap_dp_init(struct adiv5_dap *dap)
604 /* JTAG-DP or SWJ-DP, in JTAG mode
605 * ... for SWD mode this is patched as part
607 * FIXME: This should already be setup by the respective transport specific DAP creation.
610 dap->ops = &jtag_dp_ops;
612 dap->select = DP_SELECT_INVALID;
613 dap->last_read = NULL;
615 for (size_t i = 0; i < 10; i++) {
616 /* DP initialization */
618 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
619 if (retval != ERROR_OK)
622 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
623 if (retval != ERROR_OK)
626 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
627 if (retval != ERROR_OK)
630 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
631 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
632 if (retval != ERROR_OK)
635 /* Check that we have debug power domains activated */
636 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
637 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
638 CDBGPWRUPACK, CDBGPWRUPACK,
639 DAP_POWER_DOMAIN_TIMEOUT);
640 if (retval != ERROR_OK)
643 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
644 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
645 CSYSPWRUPACK, CSYSPWRUPACK,
646 DAP_POWER_DOMAIN_TIMEOUT);
647 if (retval != ERROR_OK)
650 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
651 if (retval != ERROR_OK)
654 /* With debug power on we can activate OVERRUN checking */
655 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
656 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
657 if (retval != ERROR_OK)
659 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
660 if (retval != ERROR_OK)
663 retval = dap_run(dap);
664 if (retval != ERROR_OK)
674 * Initialize a DAP. This sets up the power domains, prepares the DP
675 * for further use, and arranges to use AP #0 for all AP operations
676 * until dap_ap-select() changes that policy.
678 * @param ap The MEM-AP being initialized.
680 int mem_ap_init(struct adiv5_ap *ap)
682 /* check that we support packed transfers */
685 struct adiv5_dap *dap = ap->dap;
687 retval = mem_ap_setup_transfer(ap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
688 if (retval != ERROR_OK)
691 retval = dap_queue_ap_read(ap, MEM_AP_REG_CSW, &csw);
692 if (retval != ERROR_OK)
695 retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &cfg);
696 if (retval != ERROR_OK)
699 retval = dap_run(dap);
700 if (retval != ERROR_OK)
703 if (csw & CSW_ADDRINC_PACKED)
704 ap->packed_transfers = true;
706 ap->packed_transfers = false;
708 /* Packed transfers on TI BE-32 processors do not work correctly in
710 if (dap->ti_be_32_quirks)
711 ap->packed_transfers = false;
713 LOG_DEBUG("MEM_AP Packed Transfers: %s",
714 ap->packed_transfers ? "enabled" : "disabled");
716 /* The ARM ADI spec leaves implementation-defined whether unaligned
717 * memory accesses work, only work partially, or cause a sticky error.
718 * On TI BE-32 processors, reads seem to return garbage in some bytes
719 * and unaligned writes seem to cause a sticky error.
720 * TODO: it would be nice to have a way to detect whether unaligned
721 * operations are supported on other processors. */
722 ap->unaligned_access_bad = dap->ti_be_32_quirks;
724 LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
725 !!(cfg & 0x04), !!(cfg & 0x02), !!(cfg & 0x01));
730 /* CID interpretation -- see ARM IHI 0029B section 3
731 * and ARM IHI 0031A table 13-3.
733 static const char *class_description[16] = {
734 "Reserved", "ROM table", "Reserved", "Reserved",
735 "Reserved", "Reserved", "Reserved", "Reserved",
736 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
737 "Reserved", "OptimoDE DESS",
738 "Generic IP component", "PrimeCell or System component"
741 static bool is_dap_cid_ok(uint32_t cid)
743 return (cid & 0xffff0fff) == 0xb105000d;
747 * This function checks the ID for each access port to find the requested Access Port type
749 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out)
753 /* Maximum AP number is 255 since the SELECT register is 8 bits */
754 for (ap_num = 0; ap_num <= 255; ap_num++) {
756 /* read the IDR register of the Access Port */
759 int retval = dap_queue_ap_read(dap_ap(dap, ap_num), AP_REG_IDR, &id_val);
760 if (retval != ERROR_OK)
763 retval = dap_run(dap);
767 * 27-24 : JEDEC bank (0x4 for ARM)
768 * 23-17 : JEDEC code (0x3B for ARM)
769 * 16-13 : Class (0b1000=Mem-AP)
771 * 7-4 : AP Variant (non-zero for JTAG-AP)
772 * 3-0 : AP Type (0=JTAG-AP 1=AHB-AP 2=APB-AP 4=AXI-AP)
775 /* Reading register for a non-existant AP should not cause an error,
776 * but just to be sure, try to continue searching if an error does happen.
778 if ((retval == ERROR_OK) && /* Register read success */
779 ((id_val & IDR_JEP106) == IDR_JEP106_ARM) && /* Jedec codes match */
780 ((id_val & IDR_TYPE) == type_to_find)) { /* type matches*/
782 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
783 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
784 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
785 (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
786 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
789 *ap_out = &dap->ap[ap_num];
794 LOG_DEBUG("No %s found",
795 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
796 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
797 (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
798 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
802 int dap_get_debugbase(struct adiv5_ap *ap,
803 uint32_t *dbgbase, uint32_t *apid)
805 struct adiv5_dap *dap = ap->dap;
808 retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE, dbgbase);
809 if (retval != ERROR_OK)
811 retval = dap_queue_ap_read(ap, AP_REG_IDR, apid);
812 if (retval != ERROR_OK)
814 retval = dap_run(dap);
815 if (retval != ERROR_OK)
821 int dap_lookup_cs_component(struct adiv5_ap *ap,
822 uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx)
824 uint32_t romentry, entry_offset = 0, component_base, devtype;
830 retval = mem_ap_read_atomic_u32(ap, (dbgbase&0xFFFFF000) |
831 entry_offset, &romentry);
832 if (retval != ERROR_OK)
835 component_base = (dbgbase & 0xFFFFF000)
836 + (romentry & 0xFFFFF000);
838 if (romentry & 0x1) {
840 retval = mem_ap_read_atomic_u32(ap, component_base | 0xff4, &c_cid1);
841 if (retval != ERROR_OK) {
842 LOG_ERROR("Can't read component with base address 0x%" PRIx32
843 ", the corresponding core might be turned off", component_base);
846 if (((c_cid1 >> 4) & 0x0f) == 1) {
847 retval = dap_lookup_cs_component(ap, component_base,
849 if (retval == ERROR_OK)
851 if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
855 retval = mem_ap_read_atomic_u32(ap,
856 (component_base & 0xfffff000) | 0xfcc,
858 if (retval != ERROR_OK)
860 if ((devtype & 0xff) == type) {
862 *addr = component_base;
869 } while (romentry > 0);
872 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
877 static int dap_read_part_id(struct adiv5_ap *ap, uint32_t component_base, uint32_t *cid, uint64_t *pid)
879 assert((component_base & 0xFFF) == 0);
880 assert(ap != NULL && cid != NULL && pid != NULL);
882 uint32_t cid0, cid1, cid2, cid3;
883 uint32_t pid0, pid1, pid2, pid3, pid4;
886 /* IDs are in last 4K section */
887 retval = mem_ap_read_u32(ap, component_base + 0xFE0, &pid0);
888 if (retval != ERROR_OK)
890 retval = mem_ap_read_u32(ap, component_base + 0xFE4, &pid1);
891 if (retval != ERROR_OK)
893 retval = mem_ap_read_u32(ap, component_base + 0xFE8, &pid2);
894 if (retval != ERROR_OK)
896 retval = mem_ap_read_u32(ap, component_base + 0xFEC, &pid3);
897 if (retval != ERROR_OK)
899 retval = mem_ap_read_u32(ap, component_base + 0xFD0, &pid4);
900 if (retval != ERROR_OK)
902 retval = mem_ap_read_u32(ap, component_base + 0xFF0, &cid0);
903 if (retval != ERROR_OK)
905 retval = mem_ap_read_u32(ap, component_base + 0xFF4, &cid1);
906 if (retval != ERROR_OK)
908 retval = mem_ap_read_u32(ap, component_base + 0xFF8, &cid2);
909 if (retval != ERROR_OK)
911 retval = mem_ap_read_u32(ap, component_base + 0xFFC, &cid3);
912 if (retval != ERROR_OK)
915 retval = dap_run(ap->dap);
916 if (retval != ERROR_OK)
919 *cid = (cid3 & 0xff) << 24
920 | (cid2 & 0xff) << 16
923 *pid = (uint64_t)(pid4 & 0xff) << 32
924 | (pid3 & 0xff) << 24
925 | (pid2 & 0xff) << 16
932 /* The designer identity code is encoded as:
933 * bits 11:8 : JEP106 Bank (number of continuation codes), only valid when bit 7 is 1.
934 * bit 7 : Set when bits 6:0 represent a JEP106 ID and cleared when bits 6:0 represent
935 * a legacy ASCII Identity Code.
936 * bits 6:0 : JEP106 Identity Code (without parity) or legacy ASCII code according to bit 7.
937 * JEP106 is a standard available from jedec.org
940 /* Part number interpretations are from Cortex
941 * core specs, the CoreSight components TRM
942 * (ARM DDI 0314H), CoreSight System Design
943 * Guide (ARM DGI 0012D) and ETM specs; also
944 * from chip observation (e.g. TI SDTI).
947 /* The legacy code only used the part number field to identify CoreSight peripherals.
948 * This meant that the same part number from two different manufacturers looked the same.
949 * It is desirable for all future additions to identify with both part number and JEP106.
950 * "ANY_ID" is a wildcard (any JEP106) only to preserve legacy behavior for legacy entries.
953 #define ANY_ID 0x1000
957 static const struct {
958 uint16_t designer_id;
963 { ARM_ID, 0x000, "Cortex-M3 SCS", "(System Control Space)", },
964 { ARM_ID, 0x001, "Cortex-M3 ITM", "(Instrumentation Trace Module)", },
965 { ARM_ID, 0x002, "Cortex-M3 DWT", "(Data Watchpoint and Trace)", },
966 { ARM_ID, 0x003, "Cortex-M3 FPB", "(Flash Patch and Breakpoint)", },
967 { ARM_ID, 0x008, "Cortex-M0 SCS", "(System Control Space)", },
968 { ARM_ID, 0x00a, "Cortex-M0 DWT", "(Data Watchpoint and Trace)", },
969 { ARM_ID, 0x00b, "Cortex-M0 BPU", "(Breakpoint Unit)", },
970 { ARM_ID, 0x00c, "Cortex-M4 SCS", "(System Control Space)", },
971 { ARM_ID, 0x00d, "CoreSight ETM11", "(Embedded Trace)", },
972 { ARM_ID, 0x00e, "Cortex-M7 FPB", "(Flash Patch and Breakpoint)", },
973 { ARM_ID, 0x490, "Cortex-A15 GIC", "(Generic Interrupt Controller)", },
974 { ARM_ID, 0x4a1, "Cortex-A53 ROM", "(v8 Memory Map ROM Table)", },
975 { ARM_ID, 0x4a2, "Cortex-A57 ROM", "(ROM Table)", },
976 { ARM_ID, 0x4a3, "Cortex-A53 ROM", "(v7 Memory Map ROM Table)", },
977 { ARM_ID, 0x4a4, "Cortex-A72 ROM", "(ROM Table)", },
978 { ARM_ID, 0x4af, "Cortex-A15 ROM", "(ROM Table)", },
979 { ARM_ID, 0x4c0, "Cortex-M0+ ROM", "(ROM Table)", },
980 { ARM_ID, 0x4c3, "Cortex-M3 ROM", "(ROM Table)", },
981 { ARM_ID, 0x4c4, "Cortex-M4 ROM", "(ROM Table)", },
982 { ARM_ID, 0x4c7, "Cortex-M7 PPB ROM", "(Private Peripheral Bus ROM Table)", },
983 { ARM_ID, 0x4c8, "Cortex-M7 ROM", "(ROM Table)", },
984 { ARM_ID, 0x470, "Cortex-M1 ROM", "(ROM Table)", },
985 { ARM_ID, 0x471, "Cortex-M0 ROM", "(ROM Table)", },
986 { ARM_ID, 0x906, "CoreSight CTI", "(Cross Trigger)", },
987 { ARM_ID, 0x907, "CoreSight ETB", "(Trace Buffer)", },
988 { ARM_ID, 0x908, "CoreSight CSTF", "(Trace Funnel)", },
989 { ARM_ID, 0x909, "CoreSight ATBR", "(Advanced Trace Bus Replicator)", },
990 { ARM_ID, 0x910, "CoreSight ETM9", "(Embedded Trace)", },
991 { ARM_ID, 0x912, "CoreSight TPIU", "(Trace Port Interface Unit)", },
992 { ARM_ID, 0x913, "CoreSight ITM", "(Instrumentation Trace Macrocell)", },
993 { ARM_ID, 0x914, "CoreSight SWO", "(Single Wire Output)", },
994 { ARM_ID, 0x917, "CoreSight HTM", "(AHB Trace Macrocell)", },
995 { ARM_ID, 0x920, "CoreSight ETM11", "(Embedded Trace)", },
996 { ARM_ID, 0x921, "Cortex-A8 ETM", "(Embedded Trace)", },
997 { ARM_ID, 0x922, "Cortex-A8 CTI", "(Cross Trigger)", },
998 { ARM_ID, 0x923, "Cortex-M3 TPIU", "(Trace Port Interface Unit)", },
999 { ARM_ID, 0x924, "Cortex-M3 ETM", "(Embedded Trace)", },
1000 { ARM_ID, 0x925, "Cortex-M4 ETM", "(Embedded Trace)", },
1001 { ARM_ID, 0x930, "Cortex-R4 ETM", "(Embedded Trace)", },
1002 { ARM_ID, 0x931, "Cortex-R5 ETM", "(Embedded Trace)", },
1003 { ARM_ID, 0x932, "CoreSight MTB-M0+", "(Micro Trace Buffer)", },
1004 { ARM_ID, 0x941, "CoreSight TPIU-Lite", "(Trace Port Interface Unit)", },
1005 { ARM_ID, 0x950, "Cortex-A9 PTM", "(Program Trace Macrocell)", },
1006 { ARM_ID, 0x955, "Cortex-A5 ETM", "(Embedded Trace)", },
1007 { ARM_ID, 0x95a, "Cortex-A72 ETM", "(Embedded Trace)", },
1008 { ARM_ID, 0x95b, "Cortex-A17 PTM", "(Program Trace Macrocell)", },
1009 { ARM_ID, 0x95d, "Cortex-A53 ETM", "(Embedded Trace)", },
1010 { ARM_ID, 0x95e, "Cortex-A57 ETM", "(Embedded Trace)", },
1011 { ARM_ID, 0x95f, "Cortex-A15 PTM", "(Program Trace Macrocell)", },
1012 { ARM_ID, 0x961, "CoreSight TMC", "(Trace Memory Controller)", },
1013 { ARM_ID, 0x962, "CoreSight STM", "(System Trace Macrocell)", },
1014 { ARM_ID, 0x975, "Cortex-M7 ETM", "(Embedded Trace)", },
1015 { ARM_ID, 0x9a0, "CoreSight PMU", "(Performance Monitoring Unit)", },
1016 { ARM_ID, 0x9a1, "Cortex-M4 TPIU", "(Trace Port Interface Unit)", },
1017 { ARM_ID, 0x9a4, "CoreSight GPR", "(Granular Power Requester)", },
1018 { ARM_ID, 0x9a5, "Cortex-A5 PMU", "(Performance Monitor Unit)", },
1019 { ARM_ID, 0x9a7, "Cortex-A7 PMU", "(Performance Monitor Unit)", },
1020 { ARM_ID, 0x9a8, "Cortex-A53 CTI", "(Cross Trigger)", },
1021 { ARM_ID, 0x9a9, "Cortex-M7 TPIU", "(Trace Port Interface Unit)", },
1022 { ARM_ID, 0x9ae, "Cortex-A17 PMU", "(Performance Monitor Unit)", },
1023 { ARM_ID, 0x9af, "Cortex-A15 PMU", "(Performance Monitor Unit)", },
1024 { ARM_ID, 0x9b7, "Cortex-R7 PMU", "(Performance Monitoring Unit)", },
1025 { ARM_ID, 0x9d3, "Cortex-A53 PMU", "(Performance Monitor Unit)", },
1026 { ARM_ID, 0x9d7, "Cortex-A57 PMU", "(Performance Monitor Unit)", },
1027 { ARM_ID, 0x9d8, "Cortex-A72 PMU", "(Performance Monitor Unit)", },
1028 { ARM_ID, 0xc05, "Cortex-A5 Debug", "(Debug Unit)", },
1029 { ARM_ID, 0xc07, "Cortex-A7 Debug", "(Debug Unit)", },
1030 { ARM_ID, 0xc08, "Cortex-A8 Debug", "(Debug Unit)", },
1031 { ARM_ID, 0xc09, "Cortex-A9 Debug", "(Debug Unit)", },
1032 { ARM_ID, 0xc0e, "Cortex-A17 Debug", "(Debug Unit)", },
1033 { ARM_ID, 0xc0f, "Cortex-A15 Debug", "(Debug Unit)", },
1034 { ARM_ID, 0xc14, "Cortex-R4 Debug", "(Debug Unit)", },
1035 { ARM_ID, 0xc15, "Cortex-R5 Debug", "(Debug Unit)", },
1036 { ARM_ID, 0xc17, "Cortex-R7 Debug", "(Debug Unit)", },
1037 { ARM_ID, 0xd03, "Cortex-A53 Debug", "(Debug Unit)", },
1038 { ARM_ID, 0xd07, "Cortex-A57 Debug", "(Debug Unit)", },
1039 { ARM_ID, 0xd08, "Cortex-A72 Debug", "(Debug Unit)", },
1040 { 0x097, 0x9af, "MSP432 ROM", "(ROM Table)" },
1041 { 0x09f, 0xcd0, "Atmel CPU with DSU", "(CPU)" },
1042 { 0x0c1, 0x1db, "XMC4500 ROM", "(ROM Table)" },
1043 { 0x0c1, 0x1df, "XMC4700/4800 ROM", "(ROM Table)" },
1044 { 0x0c1, 0x1ed, "XMC1000 ROM", "(ROM Table)" },
1045 { 0x0E5, 0x000, "SHARC+/Blackfin+", "", },
1046 { 0x0F0, 0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", },
1047 /* legacy comment: 0x113: what? */
1048 { ANY_ID, 0x120, "TI SDTI", "(System Debug Trace Interface)", }, /* from OMAP3 memmap */
1049 { ANY_ID, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */
1052 static int dap_rom_display(struct command_context *cmd_ctx,
1053 struct adiv5_ap *ap, uint32_t dbgbase, int depth)
1061 command_print(cmd_ctx, "\tTables too deep");
1066 snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
1068 uint32_t base_addr = dbgbase & 0xFFFFF000;
1069 command_print(cmd_ctx, "\t\tComponent base address 0x%08" PRIx32, base_addr);
1071 retval = dap_read_part_id(ap, base_addr, &cid, &pid);
1072 if (retval != ERROR_OK) {
1073 command_print(cmd_ctx, "\t\tCan't read component, the corresponding core might be turned off");
1074 return ERROR_OK; /* Don't abort recursion */
1077 if (!is_dap_cid_ok(cid)) {
1078 command_print(cmd_ctx, "\t\tInvalid CID 0x%08" PRIx32, cid);
1079 return ERROR_OK; /* Don't abort recursion */
1082 /* component may take multiple 4K pages */
1083 uint32_t size = (pid >> 36) & 0xf;
1085 command_print(cmd_ctx, "\t\tStart address 0x%08" PRIx32, (uint32_t)(base_addr - 0x1000 * size));
1087 command_print(cmd_ctx, "\t\tPeripheral ID 0x%010" PRIx64, pid);
1089 uint8_t class = (cid >> 12) & 0xf;
1090 uint16_t part_num = pid & 0xfff;
1091 uint16_t designer_id = ((pid >> 32) & 0xf) << 8 | ((pid >> 12) & 0xff);
1093 if (designer_id & 0x80) {
1095 command_print(cmd_ctx, "\t\tDesigner is 0x%03" PRIx16 ", %s",
1096 designer_id, jep106_manufacturer(designer_id >> 8, designer_id & 0x7f));
1098 /* Legacy ASCII ID, clear invalid bits */
1099 designer_id &= 0x7f;
1100 command_print(cmd_ctx, "\t\tDesigner ASCII code 0x%02" PRIx16 ", %s",
1101 designer_id, designer_id == 0x41 ? "ARM" : "<unknown>");
1104 /* default values to be overwritten upon finding a match */
1105 const char *type = "Unrecognized";
1106 const char *full = "";
1108 /* search dap_partnums[] array for a match */
1109 for (unsigned entry = 0; entry < ARRAY_SIZE(dap_partnums); entry++) {
1111 if ((dap_partnums[entry].designer_id != designer_id) && (dap_partnums[entry].designer_id != ANY_ID))
1114 if (dap_partnums[entry].part_num != part_num)
1117 type = dap_partnums[entry].type;
1118 full = dap_partnums[entry].full;
1122 command_print(cmd_ctx, "\t\tPart is 0x%" PRIx16", %s %s", part_num, type, full);
1123 command_print(cmd_ctx, "\t\tComponent class is 0x%" PRIx8 ", %s", class, class_description[class]);
1125 if (class == 1) { /* ROM Table */
1127 retval = mem_ap_read_atomic_u32(ap, base_addr | 0xFCC, &memtype);
1128 if (retval != ERROR_OK)
1132 command_print(cmd_ctx, "\t\tMEMTYPE system memory present on bus");
1134 command_print(cmd_ctx, "\t\tMEMTYPE system memory not present: dedicated debug bus");
1136 /* Read ROM table entries from base address until we get 0x00000000 or reach the reserved area */
1137 for (uint16_t entry_offset = 0; entry_offset < 0xF00; entry_offset += 4) {
1139 retval = mem_ap_read_atomic_u32(ap, base_addr | entry_offset, &romentry);
1140 if (retval != ERROR_OK)
1142 command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
1143 tabs, entry_offset, romentry);
1144 if (romentry & 0x01) {
1146 retval = dap_rom_display(cmd_ctx, ap, base_addr + (romentry & 0xFFFFF000), depth + 1);
1147 if (retval != ERROR_OK)
1149 } else if (romentry != 0) {
1150 command_print(cmd_ctx, "\t\tComponent not present");
1152 command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs);
1156 } else if (class == 9) { /* CoreSight component */
1157 const char *major = "Reserved", *subtype = "Reserved";
1160 retval = mem_ap_read_atomic_u32(ap, base_addr | 0xFCC, &devtype);
1161 if (retval != ERROR_OK)
1163 unsigned minor = (devtype >> 4) & 0x0f;
1164 switch (devtype & 0x0f) {
1166 major = "Miscellaneous";
1172 subtype = "Validation component";
1177 major = "Trace Sink";
1194 major = "Trace Link";
1200 subtype = "Funnel, router";
1206 subtype = "FIFO, buffer";
1211 major = "Trace Source";
1217 subtype = "Processor";
1223 subtype = "Engine/Coprocessor";
1229 subtype = "Software";
1234 major = "Debug Control";
1240 subtype = "Trigger Matrix";
1243 subtype = "Debug Auth";
1246 subtype = "Power Requestor";
1251 major = "Debug Logic";
1257 subtype = "Processor";
1263 subtype = "Engine/Coprocessor";
1274 major = "Perfomance Monitor";
1280 subtype = "Processor";
1286 subtype = "Engine/Coprocessor";
1297 command_print(cmd_ctx, "\t\tType is 0x%02" PRIx8 ", %s, %s",
1298 (uint8_t)(devtype & 0xff),
1300 /* REVISIT also show 0xfc8 DevId */
1306 static int dap_info_command(struct command_context *cmd_ctx,
1307 struct adiv5_ap *ap)
1310 uint32_t dbgbase, apid;
1313 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1314 retval = dap_get_debugbase(ap, &dbgbase, &apid);
1315 if (retval != ERROR_OK)
1318 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1320 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap->ap_num);
1324 switch (apid & (IDR_JEP106 | IDR_TYPE)) {
1325 case IDR_JEP106_ARM | AP_TYPE_JTAG_AP:
1326 command_print(cmd_ctx, "\tType is JTAG-AP");
1328 case IDR_JEP106_ARM | AP_TYPE_AHB_AP:
1329 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1331 case IDR_JEP106_ARM | AP_TYPE_APB_AP:
1332 command_print(cmd_ctx, "\tType is MEM-AP APB");
1334 case IDR_JEP106_ARM | AP_TYPE_AXI_AP:
1335 command_print(cmd_ctx, "\tType is MEM-AP AXI");
1338 command_print(cmd_ctx, "\tUnknown AP type");
1342 /* NOTE: a MEM-AP may have a single CoreSight component that's
1343 * not a ROM table ... or have no such components at all.
1345 mem_ap = (apid & IDR_CLASS) == AP_CLASS_MEM_AP;
1347 command_print(cmd_ctx, "MEM-AP BASE 0x%8.8" PRIx32, dbgbase);
1349 if (dbgbase == 0xFFFFFFFF || (dbgbase & 0x3) == 0x2) {
1350 command_print(cmd_ctx, "\tNo ROM table present");
1353 command_print(cmd_ctx, "\tValid ROM table present");
1355 command_print(cmd_ctx, "\tROM table in legacy format");
1357 dap_rom_display(cmd_ctx, ap, dbgbase & 0xFFFFF000, 0);
1364 COMMAND_HANDLER(handle_dap_info_command)
1366 struct target *target = get_current_target(CMD_CTX);
1367 struct arm *arm = target_to_arm(target);
1368 struct adiv5_dap *dap = arm->dap;
1376 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1378 return ERROR_COMMAND_SYNTAX_ERROR;
1381 return ERROR_COMMAND_SYNTAX_ERROR;
1384 return dap_info_command(CMD_CTX, &dap->ap[apsel]);
1387 COMMAND_HANDLER(dap_baseaddr_command)
1389 struct target *target = get_current_target(CMD_CTX);
1390 struct arm *arm = target_to_arm(target);
1391 struct adiv5_dap *dap = arm->dap;
1393 uint32_t apsel, baseaddr;
1401 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1402 /* AP address is in bits 31:24 of DP_SELECT */
1404 return ERROR_COMMAND_SYNTAX_ERROR;
1407 return ERROR_COMMAND_SYNTAX_ERROR;
1410 /* NOTE: assumes we're talking to a MEM-AP, which
1411 * has a base address. There are other kinds of AP,
1412 * though they're not common for now. This should
1413 * use the ID register to verify it's a MEM-AP.
1415 retval = dap_queue_ap_read(dap_ap(dap, apsel), MEM_AP_REG_BASE, &baseaddr);
1416 if (retval != ERROR_OK)
1418 retval = dap_run(dap);
1419 if (retval != ERROR_OK)
1422 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1427 COMMAND_HANDLER(dap_memaccess_command)
1429 struct target *target = get_current_target(CMD_CTX);
1430 struct arm *arm = target_to_arm(target);
1431 struct adiv5_dap *dap = arm->dap;
1433 uint32_t memaccess_tck;
1437 memaccess_tck = dap->ap[dap->apsel].memaccess_tck;
1440 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1443 return ERROR_COMMAND_SYNTAX_ERROR;
1445 dap->ap[dap->apsel].memaccess_tck = memaccess_tck;
1447 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1448 dap->ap[dap->apsel].memaccess_tck);
1453 COMMAND_HANDLER(dap_apsel_command)
1455 struct target *target = get_current_target(CMD_CTX);
1456 struct arm *arm = target_to_arm(target);
1457 struct adiv5_dap *dap = arm->dap;
1459 uint32_t apsel, apid;
1467 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1468 /* AP address is in bits 31:24 of DP_SELECT */
1470 return ERROR_COMMAND_SYNTAX_ERROR;
1473 return ERROR_COMMAND_SYNTAX_ERROR;
1478 retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid);
1479 if (retval != ERROR_OK)
1481 retval = dap_run(dap);
1482 if (retval != ERROR_OK)
1485 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1491 COMMAND_HANDLER(dap_apcsw_command)
1493 struct target *target = get_current_target(CMD_CTX);
1494 struct arm *arm = target_to_arm(target);
1495 struct adiv5_dap *dap = arm->dap;
1497 uint32_t apcsw = dap->ap[dap->apsel].csw_default, sprot = 0;
1501 command_print(CMD_CTX, "apsel %" PRIi32 " selected, csw 0x%8.8" PRIx32,
1502 (dap->apsel), apcsw);
1505 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], sprot);
1506 /* AP address is in bits 31:24 of DP_SELECT */
1508 return ERROR_COMMAND_SYNTAX_ERROR;
1512 apcsw &= ~CSW_SPROT;
1515 return ERROR_COMMAND_SYNTAX_ERROR;
1517 dap->ap[dap->apsel].csw_default = apcsw;
1524 COMMAND_HANDLER(dap_apid_command)
1526 struct target *target = get_current_target(CMD_CTX);
1527 struct arm *arm = target_to_arm(target);
1528 struct adiv5_dap *dap = arm->dap;
1530 uint32_t apsel, apid;
1538 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1539 /* AP address is in bits 31:24 of DP_SELECT */
1541 return ERROR_COMMAND_SYNTAX_ERROR;
1544 return ERROR_COMMAND_SYNTAX_ERROR;
1547 retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid);
1548 if (retval != ERROR_OK)
1550 retval = dap_run(dap);
1551 if (retval != ERROR_OK)
1554 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1559 COMMAND_HANDLER(dap_ti_be_32_quirks_command)
1561 struct target *target = get_current_target(CMD_CTX);
1562 struct arm *arm = target_to_arm(target);
1563 struct adiv5_dap *dap = arm->dap;
1565 uint32_t enable = dap->ti_be_32_quirks;
1571 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], enable);
1573 return ERROR_COMMAND_SYNTAX_ERROR;
1576 return ERROR_COMMAND_SYNTAX_ERROR;
1578 dap->ti_be_32_quirks = enable;
1579 command_print(CMD_CTX, "TI BE-32 quirks mode %s",
1580 enable ? "enabled" : "disabled");
1585 static const struct command_registration dap_commands[] = {
1588 .handler = handle_dap_info_command,
1589 .mode = COMMAND_EXEC,
1590 .help = "display ROM table for MEM-AP "
1591 "(default currently selected AP)",
1592 .usage = "[ap_num]",
1596 .handler = dap_apsel_command,
1597 .mode = COMMAND_EXEC,
1598 .help = "Set the currently selected AP (default 0) "
1599 "and display the result",
1600 .usage = "[ap_num]",
1604 .handler = dap_apcsw_command,
1605 .mode = COMMAND_EXEC,
1606 .help = "Set csw access bit ",
1612 .handler = dap_apid_command,
1613 .mode = COMMAND_EXEC,
1614 .help = "return ID register from AP "
1615 "(default currently selected AP)",
1616 .usage = "[ap_num]",
1620 .handler = dap_baseaddr_command,
1621 .mode = COMMAND_EXEC,
1622 .help = "return debug base address from MEM-AP "
1623 "(default currently selected AP)",
1624 .usage = "[ap_num]",
1627 .name = "memaccess",
1628 .handler = dap_memaccess_command,
1629 .mode = COMMAND_EXEC,
1630 .help = "set/get number of extra tck for MEM-AP memory "
1631 "bus access [0-255]",
1632 .usage = "[cycles]",
1635 .name = "ti_be_32_quirks",
1636 .handler = dap_ti_be_32_quirks_command,
1637 .mode = COMMAND_CONFIG,
1638 .help = "set/get quirks mode for TI TMS450/TMS570 processors",
1639 .usage = "[enable]",
1641 COMMAND_REGISTRATION_DONE
1644 const struct command_registration dap_command_handlers[] = {
1647 .mode = COMMAND_EXEC,
1648 .help = "DAP command group",
1650 .chain = dap_commands,
1652 COMMAND_REGISTRATION_DONE