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   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2009-2010 by Oyvind Harboe                              *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   Copyright (C) 2009-2010 by David Brownell                             *
  12  *                                                                         *
  13  *   Copyright (C) 2013 by Andreas Fritiofson                              *
  14  *   andreas.fritiofson@gmail.com                                          *
  15  *                                                                         *
  16  *   This program is free software; you can redistribute it and/or modify  *
  17  *   it under the terms of the GNU General Public License as published by  *
  18  *   the Free Software Foundation; either version 2 of the License, or     *
  19  *   (at your option) any later version.                                   *
  20  *                                                                         *
  21  *   This program is distributed in the hope that it will be useful,       *
  22  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  23  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  24  *   GNU General Public License for more details.                          *
  25  *                                                                         *
  26  *   You should have received a copy of the GNU General Public License     *
  27  *   along with this program; if not, write to the                         *
  28  *   Free Software Foundation, Inc.,                                       *
  29  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  30  ***************************************************************************/
  31
  32 /**
  33  * @file
  34  * This file implements support for the ARM Debug Interface version 5 (ADIv5)
  35  * debugging architecture.  Compared with previous versions, this includes
  36  * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
  37  * transport, and focusses on memory mapped resources as defined by the
  38  * CoreSight architecture.
  39  *
  40  * A key concept in ADIv5 is the Debug Access Port, or DAP.  A DAP has two
  41  * basic components:  a Debug Port (DP) transporting messages to and from a
  42  * debugger, and an Access Port (AP) accessing resources.  Three types of DP
  43  * are defined.  One uses only JTAG for communication, and is called JTAG-DP.
  44  * One uses only SWD for communication, and is called SW-DP.  The third can
  45  * use either SWD or JTAG, and is called SWJ-DP.  The most common type of AP
  46  * is used to access memory mapped resources and is called a MEM-AP.  Also a
  47  * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
  48  *
  49  * This programming interface allows DAP pipelined operations through a
  50  * transaction queue.  This primarily affects AP operations (such as using
  51  * a MEM-AP to access memory or registers).  If the current transaction has
  52  * not finished by the time the next one must begin, and the ORUNDETECT bit
  53  * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
  54  * further AP operations will fail.  There are two basic methods to avoid
  55  * such overrun errors.  One involves polling for status instead of using
  56  * transaction piplining.  The other involves adding delays to ensure the
  57  * AP has enough time to complete one operation before starting the next
  58  * one.  (For JTAG these delays are controlled by memaccess_tck.)
  59  */
  60
  61 /*
  62  * Relevant specifications from ARM include:
  63  *
  64  * ARM(tm) Debug Interface v5 Architecture Specification    ARM IHI 0031A
  65  * CoreSight(tm) v1.0 Architecture Specification            ARM IHI 0029B
  66  *
  67  * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
  68  * Cortex-M3(tm) TRM, ARM DDI 0337G
  69  */
  70
  71 #ifdef HAVE_CONFIG_H
  72 #include "config.h"
  73 #endif
  74
  75 #include "jtag/interface.h"
  76 #include "arm.h"
  77 #include "arm_adi_v5.h"
  78 #include <helper/time_support.h>
  79
  80 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement  */
  81
  82 /*
  83         uint32_t tar_block_size(uint32_t address)
  84         Return the largest block starting at address that does not cross a tar block size alignment boundary
  85 */
  86 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
  87 {
  88         return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
  89 }
  90
  91 /***************************************************************************
  92  *                                                                         *
  93  * DP and MEM-AP  register access  through APACC and DPACC                 *
  94  *                                                                         *
  95 ***************************************************************************/
  96
  97 /**
  98  * Select one of the APs connected to the specified DAP.  The
  99  * selection is implicitly used with future AP transactions.
 100  * This is a NOP if the specified AP is already selected.
 101  *
 102  * @param dap The DAP
 103  * @param apsel Number of the AP to (implicitly) use with further
 104  *      transactions.  This normally identifies a MEM-AP.
 105  */
 106 void dap_ap_select(struct adiv5_dap *dap, uint8_t ap)
 107 {
 108         uint32_t new_ap = (ap << 24) & 0xFF000000;
 109
 110         if (new_ap != dap->ap_current) {
 111                 dap->ap_current = new_ap;
 112                 /* Switching AP invalidates cached values.
 113                  * Values MUST BE UPDATED BEFORE AP ACCESS.
 114                  */
 115                 dap->ap_bank_value = -1;
 116                 dap->ap_csw_value = -1;
 117                 dap->ap_tar_value = -1;
 118         }
 119 }
 120
 121 static int dap_setup_accessport_csw(struct adiv5_dap *dap, uint32_t csw)
 122 {
 123         csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT |
 124                 dap->apcsw[dap->ap_current >> 24];
 125
 126         if (csw != dap->ap_csw_value) {
 127                 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
 128                 int retval = dap_queue_ap_write(dap, AP_REG_CSW, csw);
 129                 if (retval != ERROR_OK)
 130                         return retval;
 131                 dap->ap_csw_value = csw;
 132         }
 133         return ERROR_OK;
 134 }
 135
 136 static int dap_setup_accessport_tar(struct adiv5_dap *dap, uint32_t tar)
 137 {
 138         if (tar != dap->ap_tar_value || dap->ap_csw_value & CSW_ADDRINC_MASK) {
 139                 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
 140                 int retval = dap_queue_ap_write(dap, AP_REG_TAR, tar);
 141                 if (retval != ERROR_OK)
 142                         return retval;
 143                 dap->ap_tar_value = tar;
 144         }
 145         return ERROR_OK;
 146 }
 147
 148 /**
 149  * Queue transactions setting up transfer parameters for the
 150  * currently selected MEM-AP.
 151  *
 152  * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
 153  * initiate data reads or writes using memory or peripheral addresses.
 154  * If the CSW is configured for it, the TAR may be automatically
 155  * incremented after each transfer.
 156  *
 157  * @todo Rename to reflect it being specifically a MEM-AP function.
 158  *
 159  * @param dap The DAP connected to the MEM-AP.
 160  * @param csw MEM-AP Control/Status Word (CSW) register to assign.  If this
 161  *      matches the cached value, the register is not changed.
 162  * @param tar MEM-AP Transfer Address Register (TAR) to assign.  If this
 163  *      matches the cached address, the register is not changed.
 164  *
 165  * @return ERROR_OK if the transaction was properly queued, else a fault code.
 166  */
 167 int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
 168 {
 169         int retval;
 170         retval = dap_setup_accessport_csw(dap, csw);
 171         if (retval != ERROR_OK)
 172                 return retval;
 173         retval = dap_setup_accessport_tar(dap, tar);
 174         if (retval != ERROR_OK)
 175                 return retval;
 176         return ERROR_OK;
 177 }
 178
 179 /**
 180  * Asynchronous (queued) read of a word from memory or a system register.
 181  *
 182  * @param dap The DAP connected to the MEM-AP performing the read.
 183  * @param address Address of the 32-bit word to read; it must be
 184  *      readable by the currently selected MEM-AP.
 185  * @param value points to where the word will be stored when the
 186  *      transaction queue is flushed (assuming no errors).
 187  *
 188  * @return ERROR_OK for success.  Otherwise a fault code.
 189  */
 190 int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
 191                 uint32_t *value)
 192 {
 193         int retval;
 194
 195         /* Use banked addressing (REG_BDx) to avoid some link traffic
 196          * (updating TAR) when reading several consecutive addresses.
 197          */
 198         retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
 199                         address & 0xFFFFFFF0);
 200         if (retval != ERROR_OK)
 201                 return retval;
 202
 203         return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value);
 204 }
 205
 206 /**
 207  * Synchronous read of a word from memory or a system register.
 208  * As a side effect, this flushes any queued transactions.
 209  *
 210  * @param dap The DAP connected to the MEM-AP performing the read.
 211  * @param address Address of the 32-bit word to read; it must be
 212  *      readable by the currently selected MEM-AP.
 213  * @param value points to where the result will be stored.
 214  *
 215  * @return ERROR_OK for success; *value holds the result.
 216  * Otherwise a fault code.
 217  */
 218 int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
 219                 uint32_t *value)
 220 {
 221         int retval;
 222
 223         retval = mem_ap_read_u32(dap, address, value);
 224         if (retval != ERROR_OK)
 225                 return retval;
 226
 227         return dap_run(dap);
 228 }
 229
 230 /**
 231  * Asynchronous (queued) write of a word to memory or a system register.
 232  *
 233  * @param dap The DAP connected to the MEM-AP.
 234  * @param address Address to be written; it must be writable by
 235  *      the currently selected MEM-AP.
 236  * @param value Word that will be written to the address when transaction
 237  *      queue is flushed (assuming no errors).
 238  *
 239  * @return ERROR_OK for success.  Otherwise a fault code.
 240  */
 241 int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
 242                 uint32_t value)
 243 {
 244         int retval;
 245
 246         /* Use banked addressing (REG_BDx) to avoid some link traffic
 247          * (updating TAR) when writing several consecutive addresses.
 248          */
 249         retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
 250                         address & 0xFFFFFFF0);
 251         if (retval != ERROR_OK)
 252                 return retval;
 253
 254         return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC),
 255                         value);
 256 }
 257
 258 /**
 259  * Synchronous write of a word to memory or a system register.
 260  * As a side effect, this flushes any queued transactions.
 261  *
 262  * @param dap The DAP connected to the MEM-AP.
 263  * @param address Address to be written; it must be writable by
 264  *      the currently selected MEM-AP.
 265  * @param value Word that will be written.
 266  *
 267  * @return ERROR_OK for success; the data was written.  Otherwise a fault code.
 268  */
 269 int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
 270                 uint32_t value)
 271 {
 272         int retval = mem_ap_write_u32(dap, address, value);
 273
 274         if (retval != ERROR_OK)
 275                 return retval;
 276
 277         return dap_run(dap);
 278 }
 279
 280 /**
 281  * Synchronous write of a block of memory, using a specific access size.
 282  *
 283  * @param dap The DAP connected to the MEM-AP.
 284  * @param buffer The data buffer to write. No particular alignment is assumed.
 285  * @param size Which access size to use, in bytes. 1, 2 or 4.
 286  * @param count The number of writes to do (in size units, not bytes).
 287  * @param address Address to be written; it must be writable by the currently selected MEM-AP.
 288  * @param addrinc Whether the target address should be increased for each write or not. This
 289  *  should normally be true, except when writing to e.g. a FIFO.
 290  * @return ERROR_OK on success, otherwise an error code.
 291  */
 292 int mem_ap_write(struct adiv5_dap *dap, const uint8_t *buffer, uint32_t size, uint32_t count,
 293                 uint32_t address, bool addrinc)
 294 {
 295         size_t nbytes = size * count;
 296         const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
 297         uint32_t csw_size;
 298         uint32_t addr_xor;
 299         int retval;
 300
 301         /* TI BE-32 Quirks mode:
 302          * Writes on big-endian TMS570 behave very strangely. Observed behavior:
 303          *   size   write address   bytes written in order
 304          *   4      TAR ^ 0         (val >> 24), (val >> 16), (val >> 8), (val)
 305          *   2      TAR ^ 2         (val >> 8), (val)
 306          *   1      TAR ^ 3         (val)
 307          * For example, if you attempt to write a single byte to address 0, the processor
 308          * will actually write a byte to address 3.
 309          *
 310          * To make writes of size < 4 work as expected, we xor a value with the address before
 311          * setting the TAP, and we set the TAP after every transfer rather then relying on
 312          * address increment. */
 313
 314         if (size == 4) {
 315                 csw_size = CSW_32BIT;
 316                 addr_xor = 0;
 317         } else if (size == 2) {
 318                 csw_size = CSW_16BIT;
 319                 addr_xor = dap->ti_be_32_quirks ? 2 : 0;
 320         } else if (size == 1) {
 321                 csw_size = CSW_8BIT;
 322                 addr_xor = dap->ti_be_32_quirks ? 3 : 0;
 323         } else {
 324                 return ERROR_TARGET_UNALIGNED_ACCESS;
 325         }
 326
 327         if (dap->unaligned_access_bad && (address % size != 0))
 328                 return ERROR_TARGET_UNALIGNED_ACCESS;
 329
 330         retval = dap_setup_accessport_tar(dap, address ^ addr_xor);
 331         if (retval != ERROR_OK)
 332                 return retval;
 333
 334         while (nbytes > 0) {
 335                 uint32_t this_size = size;
 336
 337                 /* Select packed transfer if possible */
 338                 if (addrinc && dap->packed_transfers && nbytes >= 4
 339                                 && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
 340                         this_size = 4;
 341                         retval = dap_setup_accessport_csw(dap, csw_size | CSW_ADDRINC_PACKED);
 342                 } else {
 343                         retval = dap_setup_accessport_csw(dap, csw_size | csw_addrincr);
 344                 }
 345
 346                 if (retval != ERROR_OK)
 347                         break;
 348
 349                 /* How many source bytes each transfer will consume, and their location in the DRW,
 350                  * depends on the type of transfer and alignment. See ARM document IHI0031C. */
 351                 uint32_t outvalue = 0;
 352                 if (dap->ti_be_32_quirks) {
 353                         switch (this_size) {
 354                         case 4:
 355                                 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
 356                                 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
 357                                 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
 358                                 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
 359                                 break;
 360                         case 2:
 361                                 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
 362                                 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
 363                                 break;
 364                         case 1:
 365                                 outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (address++ & 3) ^ addr_xor);
 366                                 break;
 367                         }
 368                 } else {
 369                         switch (this_size) {
 370                         case 4:
 371                                 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 372                                 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 373                         case 2:
 374                                 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 375                         case 1:
 376                                 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 377                         }
 378                 }
 379
 380                 nbytes -= this_size;
 381
 382                 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
 383                 if (retval != ERROR_OK)
 384                         break;
 385
 386                 /* Rewrite TAR if it wrapped or we're xoring addresses */
 387                 if (addrinc && (addr_xor || (address % dap->tar_autoincr_block < size && nbytes > 0))) {
 388                         retval = dap_setup_accessport_tar(dap, address ^ addr_xor);
 389                         if (retval != ERROR_OK)
 390                                 break;
 391                 }
 392         }
 393
 394         /* REVISIT: Might want to have a queued version of this function that does not run. */
 395         if (retval == ERROR_OK)
 396                 retval = dap_run(dap);
 397
 398         if (retval != ERROR_OK) {
 399                 uint32_t tar;
 400                 if (dap_queue_ap_read(dap, AP_REG_TAR, &tar) == ERROR_OK
 401                                 && dap_run(dap) == ERROR_OK)
 402                         LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
 403                 else
 404                         LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
 405         }
 406
 407         return retval;
 408 }
 409
 410 /**
 411  * Synchronous read of a block of memory, using a specific access size.
 412  *
 413  * @param dap The DAP connected to the MEM-AP.
 414  * @param buffer The data buffer to receive the data. No particular alignment is assumed.
 415  * @param size Which access size to use, in bytes. 1, 2 or 4.
 416  * @param count The number of reads to do (in size units, not bytes).
 417  * @param address Address to be read; it must be readable by the currently selected MEM-AP.
 418  * @param addrinc Whether the target address should be increased after each read or not. This
 419  *  should normally be true, except when reading from e.g. a FIFO.
 420  * @return ERROR_OK on success, otherwise an error code.
 421  */
 422 int mem_ap_read(struct adiv5_dap *dap, uint8_t *buffer, uint32_t size, uint32_t count,
 423                 uint32_t adr, bool addrinc)
 424 {
 425         size_t nbytes = size * count;
 426         const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
 427         uint32_t csw_size;
 428         uint32_t address = adr;
 429         int retval;
 430
 431         /* TI BE-32 Quirks mode:
 432          * Reads on big-endian TMS570 behave strangely differently than writes.
 433          * They read from the physical address requested, but with DRW byte-reversed.
 434          * For example, a byte read from address 0 will place the result in the high bytes of DRW.
 435          * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
 436          * so avoid them. */
 437
 438         if (size == 4)
 439                 csw_size = CSW_32BIT;
 440         else if (size == 2)
 441                 csw_size = CSW_16BIT;
 442         else if (size == 1)
 443                 csw_size = CSW_8BIT;
 444         else
 445                 return ERROR_TARGET_UNALIGNED_ACCESS;
 446
 447         if (dap->unaligned_access_bad && (adr % size != 0))
 448                 return ERROR_TARGET_UNALIGNED_ACCESS;
 449
 450         /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
 451          * over-allocation if packed transfers are going to be used, but determining the real need at
 452          * this point would be messy. */
 453         uint32_t *read_buf = malloc(count * sizeof(uint32_t));
 454         uint32_t *read_ptr = read_buf;
 455         if (read_buf == NULL) {
 456                 LOG_ERROR("Failed to allocate read buffer");
 457                 return ERROR_FAIL;
 458         }
 459
 460         retval = dap_setup_accessport_tar(dap, address);
 461         if (retval != ERROR_OK) {
 462                 free(read_buf);
 463                 return retval;
 464         }
 465
 466         /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
 467          * useful bytes it contains, and their location in the word, depends on the type of transfer
 468          * and alignment. */
 469         while (nbytes > 0) {
 470                 uint32_t this_size = size;
 471
 472                 /* Select packed transfer if possible */
 473                 if (addrinc && dap->packed_transfers && nbytes >= 4
 474                                 && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
 475                         this_size = 4;
 476                         retval = dap_setup_accessport_csw(dap, csw_size | CSW_ADDRINC_PACKED);
 477                 } else {
 478                         retval = dap_setup_accessport_csw(dap, csw_size | csw_addrincr);
 479                 }
 480                 if (retval != ERROR_OK)
 481                         break;
 482
 483                 retval = dap_queue_ap_read(dap, AP_REG_DRW, read_ptr++);
 484                 if (retval != ERROR_OK)
 485                         break;
 486
 487                 nbytes -= this_size;
 488                 address += this_size;
 489
 490                 /* Rewrite TAR if it wrapped */
 491                 if (addrinc && address % dap->tar_autoincr_block < size && nbytes > 0) {
 492                         retval = dap_setup_accessport_tar(dap, address);
 493                         if (retval != ERROR_OK)
 494                                 break;
 495                 }
 496         }
 497
 498         if (retval == ERROR_OK)
 499                 retval = dap_run(dap);
 500
 501         /* Restore state */
 502         address = adr;
 503         nbytes = size * count;
 504         read_ptr = read_buf;
 505
 506         /* If something failed, read TAR to find out how much data was successfully read, so we can
 507          * at least give the caller what we have. */
 508         if (retval != ERROR_OK) {
 509                 uint32_t tar;
 510                 if (dap_queue_ap_read(dap, AP_REG_TAR, &tar) == ERROR_OK
 511                                 && dap_run(dap) == ERROR_OK) {
 512                         LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
 513                         if (nbytes > tar - address)
 514                                 nbytes = tar - address;
 515                 } else {
 516                         LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
 517                         nbytes = 0;
 518                 }
 519         }
 520
 521         /* Replay loop to populate caller's buffer from the correct word and byte lane */
 522         while (nbytes > 0) {
 523                 uint32_t this_size = size;
 524
 525                 if (addrinc && dap->packed_transfers && nbytes >= 4
 526                                 && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
 527                         this_size = 4;
 528                 }
 529
 530                 if (dap->ti_be_32_quirks) {
 531                         switch (this_size) {
 532                         case 4:
 533                                 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
 534                                 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
 535                         case 2:
 536                                 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
 537                         case 1:
 538                                 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
 539                         }
 540                 } else {
 541                         switch (this_size) {
 542                         case 4:
 543                                 *buffer++ = *read_ptr >> 8 * (address++ & 3);
 544                                 *buffer++ = *read_ptr >> 8 * (address++ & 3);
 545                         case 2:
 546                                 *buffer++ = *read_ptr >> 8 * (address++ & 3);
 547                         case 1:
 548                                 *buffer++ = *read_ptr >> 8 * (address++ & 3);
 549                         }
 550                 }
 551
 552                 read_ptr++;
 553                 nbytes -= this_size;
 554         }
 555
 556         free(read_buf);
 557         return retval;
 558 }
 559
 560 /*--------------------------------------------------------------------*/
 561 /*          Wrapping function with selection of AP                    */
 562 /*--------------------------------------------------------------------*/
 563 int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
 564                 uint32_t address, uint32_t *value)
 565 {
 566         dap_ap_select(swjdp, ap);
 567         return mem_ap_read_u32(swjdp, address, value);
 568 }
 569
 570 int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap,
 571                 uint32_t address, uint32_t value)
 572 {
 573         dap_ap_select(swjdp, ap);
 574         return mem_ap_write_u32(swjdp, address, value);
 575 }
 576
 577 int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
 578                 uint32_t address, uint32_t *value)
 579 {
 580         dap_ap_select(swjdp, ap);
 581         return mem_ap_read_atomic_u32(swjdp, address, value);
 582 }
 583
 584 int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
 585                 uint32_t address, uint32_t value)
 586 {
 587         dap_ap_select(swjdp, ap);
 588         return mem_ap_write_atomic_u32(swjdp, address, value);
 589 }
 590
 591 int mem_ap_sel_read_buf(struct adiv5_dap *swjdp, uint8_t ap,
 592                 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 593 {
 594         dap_ap_select(swjdp, ap);
 595         return mem_ap_read(swjdp, buffer, size, count, address, true);
 596 }
 597
 598 int mem_ap_sel_write_buf(struct adiv5_dap *swjdp, uint8_t ap,
 599                 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 600 {
 601         dap_ap_select(swjdp, ap);
 602         return mem_ap_write(swjdp, buffer, size, count, address, true);
 603 }
 604
 605 int mem_ap_sel_read_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap,
 606                 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 607 {
 608         dap_ap_select(swjdp, ap);
 609         return mem_ap_read(swjdp, buffer, size, count, address, false);
 610 }
 611
 612 int mem_ap_sel_write_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap,
 613                 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 614 {
 615         dap_ap_select(swjdp, ap);
 616         return mem_ap_write(swjdp, buffer, size, count, address, false);
 617 }
 618
 619 /*--------------------------------------------------------------------------*/
 620
 621
 622 #define DAP_POWER_DOMAIN_TIMEOUT (10)
 623
 624 /* FIXME don't import ... just initialize as
 625  * part of DAP transport setup
 626 */
 627 extern const struct dap_ops jtag_dp_ops;
 628
 629 /*--------------------------------------------------------------------------*/
 630
 631 /**
 632  * Initialize a DAP.  This sets up the power domains, prepares the DP
 633  * for further use, and arranges to use AP #0 for all AP operations
 634  * until dap_ap-select() changes that policy.
 635  *
 636  * @param dap The DAP being initialized.
 637  *
 638  * @todo Rename this.  We also need an initialization scheme which account
 639  * for SWD transports not just JTAG; that will need to address differences
 640  * in layering.  (JTAG is useful without any debug target; but not SWD.)
 641  * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
 642  */
 643 int ahbap_debugport_init(struct adiv5_dap *dap)
 644 {
 645         int retval;
 646
 647         LOG_DEBUG(" ");
 648
 649         /* JTAG-DP or SWJ-DP, in JTAG mode
 650          * ... for SWD mode this is patched as part
 651          * of link switchover
 652          */
 653         if (!dap->ops)
 654                 dap->ops = &jtag_dp_ops;
 655
 656         /* Default MEM-AP setup.
 657          *
 658          * REVISIT AP #0 may be an inappropriate default for this.
 659          * Should we probe, or take a hint from the caller?
 660          * Presumably we can ignore the possibility of multiple APs.
 661          */
 662         dap->ap_current = !0;
 663         dap_ap_select(dap, 0);
 664
 665         /* DP initialization */
 666
 667         dap->dp_bank_value = 0;
 668
 669         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 670         if (retval != ERROR_OK)
 671                 return retval;
 672
 673         retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
 674         if (retval != ERROR_OK)
 675                 return retval;
 676
 677         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 678         if (retval != ERROR_OK)
 679                 return retval;
 680
 681         dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
 682         retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
 683         if (retval != ERROR_OK)
 684                 return retval;
 685
 686         /* Check that we have debug power domains activated */
 687         LOG_DEBUG("DAP: wait CDBGPWRUPACK");
 688         retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
 689                                       CDBGPWRUPACK, CDBGPWRUPACK,
 690                                       DAP_POWER_DOMAIN_TIMEOUT);
 691         if (retval != ERROR_OK)
 692                 return retval;
 693
 694         LOG_DEBUG("DAP: wait CSYSPWRUPACK");
 695         retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
 696                                       CSYSPWRUPACK, CSYSPWRUPACK,
 697                                       DAP_POWER_DOMAIN_TIMEOUT);
 698         if (retval != ERROR_OK)
 699                 return retval;
 700
 701         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 702         if (retval != ERROR_OK)
 703                 return retval;
 704         /* With debug power on we can activate OVERRUN checking */
 705         dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
 706         retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
 707         if (retval != ERROR_OK)
 708                 return retval;
 709         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 710         if (retval != ERROR_OK)
 711                 return retval;
 712
 713         /* check that we support packed transfers */
 714         uint32_t csw, cfg;
 715
 716         retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
 717         if (retval != ERROR_OK)
 718                 return retval;
 719
 720         retval = dap_queue_ap_read(dap, AP_REG_CSW, &csw);
 721         if (retval != ERROR_OK)
 722                 return retval;
 723
 724         retval = dap_queue_ap_read(dap, AP_REG_CFG, &cfg);
 725         if (retval != ERROR_OK)
 726                 return retval;
 727
 728         retval = dap_run(dap);
 729         if (retval != ERROR_OK)
 730                 return retval;
 731
 732         if (csw & CSW_ADDRINC_PACKED)
 733                 dap->packed_transfers = true;
 734         else
 735                 dap->packed_transfers = false;
 736
 737         /* Packed transfers on TI BE-32 processors do not work correctly in
 738          * many cases. */
 739         if (dap->ti_be_32_quirks)
 740                 dap->packed_transfers = false;
 741
 742         LOG_DEBUG("MEM_AP Packed Transfers: %s",
 743                         dap->packed_transfers ? "enabled" : "disabled");
 744
 745         /* The ARM ADI spec leaves implementation-defined whether unaligned
 746          * memory accesses work, only work partially, or cause a sticky error.
 747          * On TI BE-32 processors, reads seem to return garbage in some bytes
 748          * and unaligned writes seem to cause a sticky error.
 749          * TODO: it would be nice to have a way to detect whether unaligned
 750          * operations are supported on other processors. */
 751         dap->unaligned_access_bad = dap->ti_be_32_quirks;
 752
 753         LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
 754                         !!(cfg & 0x04), !!(cfg & 0x02), !!(cfg & 0x01));
 755
 756         return ERROR_OK;
 757 }
 758
 759 /* CID interpretation -- see ARM IHI 0029B section 3
 760  * and ARM IHI 0031A table 13-3.
 761  */
 762 static const char *class_description[16] = {
 763         "Reserved", "ROM table", "Reserved", "Reserved",
 764         "Reserved", "Reserved", "Reserved", "Reserved",
 765         "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
 766         "Reserved", "OptimoDE DESS",
 767         "Generic IP component", "PrimeCell or System component"
 768 };
 769
 770 static bool is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
 771 {
 772         return cid3 == 0xb1 && cid2 == 0x05
 773                         && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
 774 }
 775
 776 /*
 777  * This function checks the ID for each access port to find the requested Access Port type
 778  */
 779 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, uint8_t *ap_num_out)
 780 {
 781         int ap;
 782
 783         /* Maximum AP number is 255 since the SELECT register is 8 bits */
 784         for (ap = 0; ap <= 255; ap++) {
 785
 786                 /* read the IDR register of the Access Port */
 787                 uint32_t id_val = 0;
 788                 dap_ap_select(dap, ap);
 789
 790                 int retval = dap_queue_ap_read(dap, AP_REG_IDR, &id_val);
 791                 if (retval != ERROR_OK)
 792                         return retval;
 793
 794                 retval = dap_run(dap);
 795
 796                 /* IDR bits:
 797                  * 31-28 : Revision
 798                  * 27-24 : JEDEC bank (0x4 for ARM)
 799                  * 23-17 : JEDEC code (0x3B for ARM)
 800                  * 16    : Mem-AP
 801                  * 15-8  : Reserved
 802                  *  7-0  : AP Identity (1=AHB-AP 2=APB-AP 0x10=JTAG-AP)
 803                  */
 804
 805                 /* Reading register for a non-existant AP should not cause an error,
 806                  * but just to be sure, try to continue searching if an error does happen.
 807                  */
 808                 if ((retval == ERROR_OK) &&                  /* Register read success */
 809                         ((id_val & 0x0FFF0000) == 0x04770000) && /* Jedec codes match */
 810                         ((id_val & 0xFF) == type_to_find)) {     /* type matches*/
 811
 812                         LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
 813                                                 (type_to_find == AP_TYPE_AHB_AP)  ? "AHB-AP"  :
 814                                                 (type_to_find == AP_TYPE_APB_AP)  ? "APB-AP"  :
 815                                                 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
 816                                                 ap, id_val);
 817
 818                         *ap_num_out = ap;
 819                         return ERROR_OK;
 820                 }
 821         }
 822
 823         LOG_DEBUG("No %s found",
 824                                 (type_to_find == AP_TYPE_AHB_AP)  ? "AHB-AP"  :
 825                                 (type_to_find == AP_TYPE_APB_AP)  ? "APB-AP"  :
 826                                 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
 827         return ERROR_FAIL;
 828 }
 829
 830 int dap_get_debugbase(struct adiv5_dap *dap, int ap,
 831                         uint32_t *out_dbgbase, uint32_t *out_apid)
 832 {
 833         uint32_t ap_old;
 834         int retval;
 835         uint32_t dbgbase, apid;
 836
 837         /* AP address is in bits 31:24 of DP_SELECT */
 838         if (ap >= 256)
 839                 return ERROR_COMMAND_SYNTAX_ERROR;
 840
 841         ap_old = dap->ap_current;
 842         dap_ap_select(dap, ap);
 843
 844         retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase);
 845         if (retval != ERROR_OK)
 846                 return retval;
 847         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
 848         if (retval != ERROR_OK)
 849                 return retval;
 850         retval = dap_run(dap);
 851         if (retval != ERROR_OK)
 852                 return retval;
 853
 854         /* Excavate the device ID code */
 855         struct jtag_tap *tap = dap->jtag_info->tap;
 856         while (tap != NULL) {
 857                 if (tap->hasidcode)
 858                         break;
 859                 tap = tap->next_tap;
 860         }
 861         if (tap == NULL || !tap->hasidcode)
 862                 return ERROR_OK;
 863
 864         dap_ap_select(dap, ap_old);
 865
 866         /* The asignment happens only here to prevent modification of these
 867          * values before they are certain. */
 868         *out_dbgbase = dbgbase;
 869         *out_apid = apid;
 870
 871         return ERROR_OK;
 872 }
 873
 874 int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
 875                         uint32_t dbgbase, uint8_t type, uint32_t *addr)
 876 {
 877         uint32_t ap_old;
 878         uint32_t romentry, entry_offset = 0, component_base, devtype;
 879         int retval = ERROR_FAIL;
 880
 881         if (ap >= 256)
 882                 return ERROR_COMMAND_SYNTAX_ERROR;
 883
 884         ap_old = dap->ap_current;
 885         dap_ap_select(dap, ap);
 886
 887         do {
 888                 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) |
 889                                                 entry_offset, &romentry);
 890                 if (retval != ERROR_OK)
 891                         return retval;
 892
 893                 component_base = (dbgbase & 0xFFFFF000)
 894                         + (romentry & 0xFFFFF000);
 895
 896                 if (romentry & 0x1) {
 897                         retval = mem_ap_read_atomic_u32(dap,
 898                                         (component_base & 0xfffff000) | 0xfcc,
 899                                         &devtype);
 900                         if (retval != ERROR_OK)
 901                                 return retval;
 902                         if ((devtype & 0xff) == type) {
 903                                 *addr = component_base;
 904                                 retval = ERROR_OK;
 905                                 break;
 906                         }
 907                 }
 908                 entry_offset += 4;
 909         } while (romentry > 0);
 910
 911         dap_ap_select(dap, ap_old);
 912
 913         return retval;
 914 }
 915
 916 static int dap_rom_display(struct command_context *cmd_ctx,
 917                                 struct adiv5_dap *dap, int ap, uint32_t dbgbase, int depth)
 918 {
 919         int retval;
 920         uint32_t cid0, cid1, cid2, cid3, memtype, romentry;
 921         uint16_t entry_offset;
 922         char tabs[7] = "";
 923
 924         if (depth > 16) {
 925                 command_print(cmd_ctx, "\tTables too deep");
 926                 return ERROR_FAIL;
 927         }
 928
 929         if (depth)
 930                 snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
 931
 932         /* bit 16 of apid indicates a memory access port */
 933         if (dbgbase & 0x02)
 934                 command_print(cmd_ctx, "\t%sValid ROM table present", tabs);
 935         else
 936                 command_print(cmd_ctx, "\t%sROM table in legacy format", tabs);
 937
 938         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
 939         retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
 940         if (retval != ERROR_OK)
 941                 return retval;
 942         retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
 943         if (retval != ERROR_OK)
 944                 return retval;
 945         retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
 946         if (retval != ERROR_OK)
 947                 return retval;
 948         retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
 949         if (retval != ERROR_OK)
 950                 return retval;
 951         retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
 952         if (retval != ERROR_OK)
 953                 return retval;
 954         retval = dap_run(dap);
 955         if (retval != ERROR_OK)
 956                 return retval;
 957
 958         if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
 959                 command_print(cmd_ctx, "\t%sCID3 0x%02x"
 960                                 ", CID2 0x%02x"
 961                                 ", CID1 0x%02x"
 962                                 ", CID0 0x%02x",
 963                                 tabs,
 964                                 (unsigned)cid3, (unsigned)cid2,
 965                                 (unsigned)cid1, (unsigned)cid0);
 966         if (memtype & 0x01)
 967                 command_print(cmd_ctx, "\t%sMEMTYPE system memory present on bus", tabs);
 968         else
 969                 command_print(cmd_ctx, "\t%sMEMTYPE system memory not present: dedicated debug bus", tabs);
 970
 971         /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
 972         for (entry_offset = 0; ; entry_offset += 4) {
 973                 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
 974                 if (retval != ERROR_OK)
 975                         return retval;
 976                 command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
 977                                 tabs, entry_offset, romentry);
 978                 if (romentry & 0x01) {
 979                         uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
 980                         uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
 981                         uint32_t component_base;
 982                         unsigned part_num;
 983                         char *type, *full;
 984
 985                         component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000);
 986
 987                         /* IDs are in last 4K section */
 988                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE0, &c_pid0);
 989                         if (retval != ERROR_OK) {
 990                                 command_print(cmd_ctx, "\t%s\tCan't read component with base address 0x%" PRIx32
 991                                               ", the corresponding core might be turned off", tabs, component_base);
 992                                 continue;
 993                         }
 994                         c_pid0 &= 0xff;
 995                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE4, &c_pid1);
 996                         if (retval != ERROR_OK)
 997                                 return retval;
 998                         c_pid1 &= 0xff;
 999                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE8, &c_pid2);
1000                         if (retval != ERROR_OK)
1001                                 return retval;
1002                         c_pid2 &= 0xff;
1003                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFEC, &c_pid3);
1004                         if (retval != ERROR_OK)
1005                                 return retval;
1006                         c_pid3 &= 0xff;
1007                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFD0, &c_pid4);
1008                         if (retval != ERROR_OK)
1009                                 return retval;
1010                         c_pid4 &= 0xff;
1011
1012                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF0, &c_cid0);
1013                         if (retval != ERROR_OK)
1014                                 return retval;
1015                         c_cid0 &= 0xff;
1016                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF4, &c_cid1);
1017                         if (retval != ERROR_OK)
1018                                 return retval;
1019                         c_cid1 &= 0xff;
1020                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF8, &c_cid2);
1021                         if (retval != ERROR_OK)
1022                                 return retval;
1023                         c_cid2 &= 0xff;
1024                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFFC, &c_cid3);
1025                         if (retval != ERROR_OK)
1026                                 return retval;
1027                         c_cid3 &= 0xff;
1028
1029                         command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 ", "
1030                                       "start address 0x%" PRIx32, component_base,
1031                                       /* component may take multiple 4K pages */
1032                                       (uint32_t)(component_base - 0x1000*(c_pid4 >> 4)));
1033                         command_print(cmd_ctx, "\t\tComponent class is 0x%" PRIx8 ", %s",
1034                                         (uint8_t)((c_cid1 >> 4) & 0xf),
1035                                         /* See ARM IHI 0029B Table 3-3 */
1036                                         class_description[(c_cid1 >> 4) & 0xf]);
1037
1038                         /* CoreSight component? */
1039                         if (((c_cid1 >> 4) & 0x0f) == 9) {
1040                                 uint32_t devtype;
1041                                 unsigned minor;
1042                                 char *major = "Reserved", *subtype = "Reserved";
1043
1044                                 retval = mem_ap_read_atomic_u32(dap,
1045                                                 (component_base & 0xfffff000) | 0xfcc,
1046                                                 &devtype);
1047                                 if (retval != ERROR_OK)
1048                                         return retval;
1049                                 minor = (devtype >> 4) & 0x0f;
1050                                 switch (devtype & 0x0f) {
1051                                 case 0:
1052                                         major = "Miscellaneous";
1053                                         switch (minor) {
1054                                         case 0:
1055                                                 subtype = "other";
1056                                                 break;
1057                                         case 4:
1058                                                 subtype = "Validation component";
1059                                                 break;
1060                                         }
1061                                         break;
1062                                 case 1:
1063                                         major = "Trace Sink";
1064                                         switch (minor) {
1065                                         case 0:
1066                                                 subtype = "other";
1067                                                 break;
1068                                         case 1:
1069                                                 subtype = "Port";
1070                                                 break;
1071                                         case 2:
1072                                                 subtype = "Buffer";
1073                                                 break;
1074                                         case 3:
1075                                                 subtype = "Router";
1076                                                 break;
1077                                         }
1078                                         break;
1079                                 case 2:
1080                                         major = "Trace Link";
1081                                         switch (minor) {
1082                                         case 0:
1083                                                 subtype = "other";
1084                                                 break;
1085                                         case 1:
1086                                                 subtype = "Funnel, router";
1087                                                 break;
1088                                         case 2:
1089                                                 subtype = "Filter";
1090                                                 break;
1091                                         case 3:
1092                                                 subtype = "FIFO, buffer";
1093                                                 break;
1094                                         }
1095                                         break;
1096                                 case 3:
1097                                         major = "Trace Source";
1098                                         switch (minor) {
1099                                         case 0:
1100                                                 subtype = "other";
1101                                                 break;
1102                                         case 1:
1103                                                 subtype = "Processor";
1104                                                 break;
1105                                         case 2:
1106                                                 subtype = "DSP";
1107                                                 break;
1108                                         case 3:
1109                                                 subtype = "Engine/Coprocessor";
1110                                                 break;
1111                                         case 4:
1112                                                 subtype = "Bus";
1113                                                 break;
1114                                         case 6:
1115                                                 subtype = "Software";
1116                                                 break;
1117                                         }
1118                                         break;
1119                                 case 4:
1120                                         major = "Debug Control";
1121                                         switch (minor) {
1122                                         case 0:
1123                                                 subtype = "other";
1124                                                 break;
1125                                         case 1:
1126                                                 subtype = "Trigger Matrix";
1127                                                 break;
1128                                         case 2:
1129                                                 subtype = "Debug Auth";
1130                                                 break;
1131                                         case 3:
1132                                                 subtype = "Power Requestor";
1133                                                 break;
1134                                         }
1135                                         break;
1136                                 case 5:
1137                                         major = "Debug Logic";
1138                                         switch (minor) {
1139                                         case 0:
1140                                                 subtype = "other";
1141                                                 break;
1142                                         case 1:
1143                                                 subtype = "Processor";
1144                                                 break;
1145                                         case 2:
1146                                                 subtype = "DSP";
1147                                                 break;
1148                                         case 3:
1149                                                 subtype = "Engine/Coprocessor";
1150                                                 break;
1151                                         case 4:
1152                                                 subtype = "Bus";
1153                                                 break;
1154                                         case 5:
1155                                                 subtype = "Memory";
1156                                                 break;
1157                                         }
1158                                         break;
1159                                 case 6:
1160                                         major = "Perfomance Monitor";
1161                                         switch (minor) {
1162                                         case 0:
1163                                                 subtype = "other";
1164                                                 break;
1165                                         case 1:
1166                                                 subtype = "Processor";
1167                                                 break;
1168                                         case 2:
1169                                                 subtype = "DSP";
1170                                                 break;
1171                                         case 3:
1172                                                 subtype = "Engine/Coprocessor";
1173                                                 break;
1174                                         case 4:
1175                                                 subtype = "Bus";
1176                                                 break;
1177                                         case 5:
1178                                                 subtype = "Memory";
1179                                                 break;
1180                                         }
1181                                         break;
1182                                 }
1183                                 command_print(cmd_ctx, "\t\tType is 0x%02" PRIx8 ", %s, %s",
1184                                                 (uint8_t)(devtype & 0xff),
1185                                                 major, subtype);
1186                                 /* REVISIT also show 0xfc8 DevId */
1187                         }
1188
1189                         if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1190                                 command_print(cmd_ctx,
1191                                                 "\t\tCID3 0%02x"
1192                                                 ", CID2 0%02x"
1193                                                 ", CID1 0%02x"
1194                                                 ", CID0 0%02x",
1195                                                 (int)c_cid3,
1196                                                 (int)c_cid2,
1197                                                 (int)c_cid1,
1198                                                 (int)c_cid0);
1199                         command_print(cmd_ctx,
1200                                 "\t\tPeripheral ID[4..0] = hex "
1201                                 "%02x %02x %02x %02x %02x",
1202                                 (int)c_pid4, (int)c_pid3, (int)c_pid2,
1203                                 (int)c_pid1, (int)c_pid0);
1204
1205                         /* Part number interpretations are from Cortex
1206                          * core specs, the CoreSight components TRM
1207                          * (ARM DDI 0314H), CoreSight System Design
1208                          * Guide (ARM DGI 0012D) and ETM specs; also
1209                          * from chip observation (e.g. TI SDTI).
1210                          */
1211                         part_num = (c_pid0 & 0xff);
1212                         part_num |= (c_pid1 & 0x0f) << 8;
1213                         switch (part_num) {
1214                         case 0x000:
1215                                 type = "Cortex-M3 NVIC";
1216                                 full = "(Interrupt Controller)";
1217                                 break;
1218                         case 0x001:
1219                                 type = "Cortex-M3 ITM";
1220                                 full = "(Instrumentation Trace Module)";
1221                                 break;
1222                         case 0x002:
1223                                 type = "Cortex-M3 DWT";
1224                                 full = "(Data Watchpoint and Trace)";
1225                                 break;
1226                         case 0x003:
1227                                 type = "Cortex-M3 FBP";
1228                                 full = "(Flash Patch and Breakpoint)";
1229                                 break;
1230                         case 0x00c:
1231                                 type = "Cortex-M4 SCS";
1232                                 full = "(System Control Space)";
1233                                 break;
1234                         case 0x00d:
1235                                 type = "CoreSight ETM11";
1236                                 full = "(Embedded Trace)";
1237                                 break;
1238                         /* case 0x113: what? */
1239                         case 0x120:             /* from OMAP3 memmap */
1240                                 type = "TI SDTI";
1241                                 full = "(System Debug Trace Interface)";
1242                                 break;
1243                         case 0x343:             /* from OMAP3 memmap */
1244                                 type = "TI DAPCTL";
1245                                 full = "";
1246                                 break;
1247                         case 0x906:
1248                                 type = "Coresight CTI";
1249                                 full = "(Cross Trigger)";
1250                                 break;
1251                         case 0x907:
1252                                 type = "Coresight ETB";
1253                                 full = "(Trace Buffer)";
1254                                 break;
1255                         case 0x908:
1256                                 type = "Coresight CSTF";
1257                                 full = "(Trace Funnel)";
1258                                 break;
1259                         case 0x910:
1260                                 type = "CoreSight ETM9";
1261                                 full = "(Embedded Trace)";
1262                                 break;
1263                         case 0x912:
1264                                 type = "Coresight TPIU";
1265                                 full = "(Trace Port Interface Unit)";
1266                                 break;
1267                         case 0x913:
1268                                 type = "Coresight ITM";
1269                                 full = "(Instrumentation Trace Macrocell)";
1270                                 break;
1271                         case 0x917:
1272                                 type = "Coresight HTM";
1273                                 full = "(AHB Trace Macrocell)";
1274                                 break;
1275                         case 0x920:
1276                                 type = "CoreSight ETM11";
1277                                 full = "(Embedded Trace)";
1278                                 break;
1279                         case 0x921:
1280                                 type = "Cortex-A8 ETM";
1281                                 full = "(Embedded Trace)";
1282                                 break;
1283                         case 0x922:
1284                                 type = "Cortex-A8 CTI";
1285                                 full = "(Cross Trigger)";
1286                                 break;
1287                         case 0x923:
1288                                 type = "Cortex-M3 TPIU";
1289                                 full = "(Trace Port Interface Unit)";
1290                                 break;
1291                         case 0x924:
1292                                 type = "Cortex-M3 ETM";
1293                                 full = "(Embedded Trace)";
1294                                 break;
1295                         case 0x925:
1296                                 type = "Cortex-M4 ETM";
1297                                 full = "(Embedded Trace)";
1298                                 break;
1299                         case 0x930:
1300                                 type = "Cortex-R4 ETM";
1301                                 full = "(Embedded Trace)";
1302                                 break;
1303                         case 0x950:
1304                                 type = "CoreSight Component";
1305                                 full = "(unidentified Cortex-A9 component)";
1306                                 break;
1307                         case 0x962:
1308                                 type = "CoreSight STM";
1309                                 full = "(System Trace Macrocell)";
1310                                 break;
1311                         case 0x9a0:
1312                                 type = "CoreSight PMU";
1313                                 full = "(Performance Monitoring Unit)";
1314                                 break;
1315                         case 0x9a1:
1316                                 type = "Cortex-M4 TPUI";
1317                                 full = "(Trace Port Interface Unit)";
1318                                 break;
1319                         case 0xc08:
1320                                 type = "Cortex-A8 Debug";
1321                                 full = "(Debug Unit)";
1322                                 break;
1323                         case 0xc09:
1324                                 type = "Cortex-A9 Debug";
1325                                 full = "(Debug Unit)";
1326                                 break;
1327                         default:
1328                                 type = "-*- unrecognized -*-";
1329                                 full = "";
1330                                 break;
1331                         }
1332                         command_print(cmd_ctx, "\t\tPart is %s %s",
1333                                         type, full);
1334
1335                         /* ROM Table? */
1336                         if (((c_cid1 >> 4) & 0x0f) == 1) {
1337                                 retval = dap_rom_display(cmd_ctx, dap, ap, component_base, depth + 1);
1338                                 if (retval != ERROR_OK)
1339                                         return retval;
1340                         }
1341                 } else {
1342                         if (romentry)
1343                                 command_print(cmd_ctx, "\t\tComponent not present");
1344                         else
1345                                 break;
1346                 }
1347         }
1348         command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs);
1349         return ERROR_OK;
1350 }
1351
1352 static int dap_info_command(struct command_context *cmd_ctx,
1353                 struct adiv5_dap *dap, int ap)
1354 {
1355         int retval;
1356         uint32_t dbgbase = 0, apid = 0; /* Silence gcc by initializing */
1357         int romtable_present = 0;
1358         uint8_t mem_ap;
1359         uint32_t ap_old;
1360
1361         retval = dap_get_debugbase(dap, ap, &dbgbase, &apid);
1362         if (retval != ERROR_OK)
1363                 return retval;
1364
1365         ap_old = dap->ap_current;
1366         dap_ap_select(dap, ap);
1367
1368         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1369         mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1370         command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1371         if (apid) {
1372                 switch (apid&0x0F) {
1373                         case 0:
1374                                 command_print(cmd_ctx, "\tType is JTAG-AP");
1375                                 break;
1376                         case 1:
1377                                 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1378                                 break;
1379                         case 2:
1380                                 command_print(cmd_ctx, "\tType is MEM-AP APB");
1381                                 break;
1382                         default:
1383                                 command_print(cmd_ctx, "\tUnknown AP type");
1384                                 break;
1385                 }
1386
1387                 /* NOTE: a MEM-AP may have a single CoreSight component that's
1388                  * not a ROM table ... or have no such components at all.
1389                  */
1390                 if (mem_ap)
1391                         command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32, dbgbase);
1392         } else
1393                 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap);
1394
1395         romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1396         if (romtable_present) {
1397                 dap_rom_display(cmd_ctx, dap, ap, dbgbase, 0);
1398         } else
1399                 command_print(cmd_ctx, "\tNo ROM table present");
1400         dap_ap_select(dap, ap_old);
1401
1402         return ERROR_OK;
1403 }
1404
1405 COMMAND_HANDLER(handle_dap_info_command)
1406 {
1407         struct target *target = get_current_target(CMD_CTX);
1408         struct arm *arm = target_to_arm(target);
1409         struct adiv5_dap *dap = arm->dap;
1410         uint32_t apsel;
1411
1412         switch (CMD_ARGC) {
1413         case 0:
1414                 apsel = dap->apsel;
1415                 break;
1416         case 1:
1417                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1418                 break;
1419         default:
1420                 return ERROR_COMMAND_SYNTAX_ERROR;
1421         }
1422
1423         return dap_info_command(CMD_CTX, dap, apsel);
1424 }
1425
1426 COMMAND_HANDLER(dap_baseaddr_command)
1427 {
1428         struct target *target = get_current_target(CMD_CTX);
1429         struct arm *arm = target_to_arm(target);
1430         struct adiv5_dap *dap = arm->dap;
1431
1432         uint32_t apsel, baseaddr;
1433         int retval;
1434
1435         switch (CMD_ARGC) {
1436         case 0:
1437                 apsel = dap->apsel;
1438                 break;
1439         case 1:
1440                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1441                 /* AP address is in bits 31:24 of DP_SELECT */
1442                 if (apsel >= 256)
1443                         return ERROR_COMMAND_SYNTAX_ERROR;
1444                 break;
1445         default:
1446                 return ERROR_COMMAND_SYNTAX_ERROR;
1447         }
1448
1449         dap_ap_select(dap, apsel);
1450
1451         /* NOTE:  assumes we're talking to a MEM-AP, which
1452          * has a base address.  There are other kinds of AP,
1453          * though they're not common for now.  This should
1454          * use the ID register to verify it's a MEM-AP.
1455          */
1456         retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
1457         if (retval != ERROR_OK)
1458                 return retval;
1459         retval = dap_run(dap);
1460         if (retval != ERROR_OK)
1461                 return retval;
1462
1463         command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1464
1465         return retval;
1466 }
1467
1468 COMMAND_HANDLER(dap_memaccess_command)
1469 {
1470         struct target *target = get_current_target(CMD_CTX);
1471         struct arm *arm = target_to_arm(target);
1472         struct adiv5_dap *dap = arm->dap;
1473
1474         uint32_t memaccess_tck;
1475
1476         switch (CMD_ARGC) {
1477         case 0:
1478                 memaccess_tck = dap->memaccess_tck;
1479                 break;
1480         case 1:
1481                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1482                 break;
1483         default:
1484                 return ERROR_COMMAND_SYNTAX_ERROR;
1485         }
1486         dap->memaccess_tck = memaccess_tck;
1487
1488         command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1489                         dap->memaccess_tck);
1490
1491         return ERROR_OK;
1492 }
1493
1494 COMMAND_HANDLER(dap_apsel_command)
1495 {
1496         struct target *target = get_current_target(CMD_CTX);
1497         struct arm *arm = target_to_arm(target);
1498         struct adiv5_dap *dap = arm->dap;
1499
1500         uint32_t apsel, apid;
1501         int retval;
1502
1503         switch (CMD_ARGC) {
1504         case 0:
1505                 apsel = 0;
1506                 break;
1507         case 1:
1508                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1509                 /* AP address is in bits 31:24 of DP_SELECT */
1510                 if (apsel >= 256)
1511                         return ERROR_COMMAND_SYNTAX_ERROR;
1512                 break;
1513         default:
1514                 return ERROR_COMMAND_SYNTAX_ERROR;
1515         }
1516
1517         dap->apsel = apsel;
1518         dap_ap_select(dap, apsel);
1519
1520         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1521         if (retval != ERROR_OK)
1522                 return retval;
1523         retval = dap_run(dap);
1524         if (retval != ERROR_OK)
1525                 return retval;
1526
1527         command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1528                         apsel, apid);
1529
1530         return retval;
1531 }
1532
1533 COMMAND_HANDLER(dap_apcsw_command)
1534 {
1535         struct target *target = get_current_target(CMD_CTX);
1536         struct arm *arm = target_to_arm(target);
1537         struct adiv5_dap *dap = arm->dap;
1538
1539         uint32_t apcsw = dap->apcsw[dap->apsel], sprot = 0;
1540
1541         switch (CMD_ARGC) {
1542         case 0:
1543                 command_print(CMD_CTX, "apsel %" PRIi32 " selected, csw 0x%8.8" PRIx32,
1544                         (dap->apsel), apcsw);
1545                 break;
1546         case 1:
1547                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], sprot);
1548                 /* AP address is in bits 31:24 of DP_SELECT */
1549                 if (sprot > 1)
1550                         return ERROR_COMMAND_SYNTAX_ERROR;
1551                 if (sprot)
1552                         apcsw |= CSW_SPROT;
1553                 else
1554                         apcsw &= ~CSW_SPROT;
1555                 break;
1556         default:
1557                 return ERROR_COMMAND_SYNTAX_ERROR;
1558         }
1559         dap->apcsw[dap->apsel] = apcsw;
1560
1561         return 0;
1562 }
1563
1564
1565
1566 COMMAND_HANDLER(dap_apid_command)
1567 {
1568         struct target *target = get_current_target(CMD_CTX);
1569         struct arm *arm = target_to_arm(target);
1570         struct adiv5_dap *dap = arm->dap;
1571
1572         uint32_t apsel, apid;
1573         int retval;
1574
1575         switch (CMD_ARGC) {
1576         case 0:
1577                 apsel = dap->apsel;
1578                 break;
1579         case 1:
1580                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1581                 /* AP address is in bits 31:24 of DP_SELECT */
1582                 if (apsel >= 256)
1583                         return ERROR_COMMAND_SYNTAX_ERROR;
1584                 break;
1585         default:
1586                 return ERROR_COMMAND_SYNTAX_ERROR;
1587         }
1588
1589         dap_ap_select(dap, apsel);
1590
1591         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1592         if (retval != ERROR_OK)
1593                 return retval;
1594         retval = dap_run(dap);
1595         if (retval != ERROR_OK)
1596                 return retval;
1597
1598         command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1599
1600         return retval;
1601 }
1602
1603 COMMAND_HANDLER(dap_ti_be_32_quirks_command)
1604 {
1605         struct target *target = get_current_target(CMD_CTX);
1606         struct arm *arm = target_to_arm(target);
1607         struct adiv5_dap *dap = arm->dap;
1608
1609         uint32_t enable = dap->ti_be_32_quirks;
1610
1611         switch (CMD_ARGC) {
1612         case 0:
1613                 break;
1614         case 1:
1615                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], enable);
1616                 if (enable > 1)
1617                         return ERROR_COMMAND_SYNTAX_ERROR;
1618                 break;
1619         default:
1620                 return ERROR_COMMAND_SYNTAX_ERROR;
1621         }
1622         dap->ti_be_32_quirks = enable;
1623         command_print(CMD_CTX, "TI BE-32 quirks mode %s",
1624                 enable ? "enabled" : "disabled");
1625
1626         return 0;
1627 }
1628
1629 static const struct command_registration dap_commands[] = {
1630         {
1631                 .name = "info",
1632                 .handler = handle_dap_info_command,
1633                 .mode = COMMAND_EXEC,
1634                 .help = "display ROM table for MEM-AP "
1635                         "(default currently selected AP)",
1636                 .usage = "[ap_num]",
1637         },
1638         {
1639                 .name = "apsel",
1640                 .handler = dap_apsel_command,
1641                 .mode = COMMAND_EXEC,
1642                 .help = "Set the currently selected AP (default 0) "
1643                         "and display the result",
1644                 .usage = "[ap_num]",
1645         },
1646         {
1647                 .name = "apcsw",
1648                 .handler = dap_apcsw_command,
1649                 .mode = COMMAND_EXEC,
1650                 .help = "Set csw access bit ",
1651                 .usage = "[sprot]",
1652         },
1653
1654         {
1655                 .name = "apid",
1656                 .handler = dap_apid_command,
1657                 .mode = COMMAND_EXEC,
1658                 .help = "return ID register from AP "
1659                         "(default currently selected AP)",
1660                 .usage = "[ap_num]",
1661         },
1662         {
1663                 .name = "baseaddr",
1664                 .handler = dap_baseaddr_command,
1665                 .mode = COMMAND_EXEC,
1666                 .help = "return debug base address from MEM-AP "
1667                         "(default currently selected AP)",
1668                 .usage = "[ap_num]",
1669         },
1670         {
1671                 .name = "memaccess",
1672                 .handler = dap_memaccess_command,
1673                 .mode = COMMAND_EXEC,
1674                 .help = "set/get number of extra tck for MEM-AP memory "
1675                         "bus access [0-255]",
1676                 .usage = "[cycles]",
1677         },
1678         {
1679                 .name = "ti_be_32_quirks",
1680                 .handler = dap_ti_be_32_quirks_command,
1681                 .mode = COMMAND_CONFIG,
1682                 .help = "set/get quirks mode for TI TMS450/TMS570 processors",
1683                 .usage = "[enable]",
1684         },
1685         COMMAND_REGISTRATION_DONE
1686 };
1687
1688 const struct command_registration dap_command_handlers[] = {
1689         {
1690                 .name = "dap",
1691                 .mode = COMMAND_EXEC,
1692                 .help = "DAP command group",
1693                 .usage = "",
1694                 .chain = dap_commands,
1695         },
1696         COMMAND_REGISTRATION_DONE
1697 };