1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * Copyright (C) 2009-2010 by David Brownell *
13 * This program is free software; you can redistribute it and/or modify *
14 * it under the terms of the GNU General Public License as published by *
15 * the Free Software Foundation; either version 2 of the License, or *
16 * (at your option) any later version. *
18 * This program is distributed in the hope that it will be useful, *
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
21 * GNU General Public License for more details. *
23 * You should have received a copy of the GNU General Public License *
24 * along with this program; if not, write to the *
25 * Free Software Foundation, Inc., *
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 ***************************************************************************/
31 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
32 * debugging architecture. Compared with previous versions, this includes
33 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
34 * transport, and focusses on memory mapped resources as defined by the
35 * CoreSight architecture.
37 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
38 * basic components: a Debug Port (DP) transporting messages to and from a
39 * debugger, and an Access Port (AP) accessing resources. Three types of DP
40 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
41 * One uses only SWD for communication, and is called SW-DP. The third can
42 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
43 * is used to access memory mapped resources and is called a MEM-AP. Also a
44 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
46 * This programming interface allows DAP pipelined operations through a
47 * transaction queue. This primarily affects AP operations (such as using
48 * a MEM-AP to access memory or registers). If the current transaction has
49 * not finished by the time the next one must begin, and the ORUNDETECT bit
50 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
51 * further AP operations will fail. There are two basic methods to avoid
52 * such overrun errors. One involves polling for status instead of using
53 * transaction piplining. The other involves adding delays to ensure the
54 * AP has enough time to complete one operation before starting the next
55 * one. (For JTAG these delays are controlled by memaccess_tck.)
59 * Relevant specifications from ARM include:
61 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
62 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
64 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
65 * Cortex-M3(tm) TRM, ARM DDI 0337G
72 #include "jtag/interface.h"
74 #include "arm_adi_v5.h"
75 #include <helper/time_support.h>
77 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
80 uint32_t tar_block_size(uint32_t address)
81 Return the largest block starting at address that does not cross a tar block size alignment boundary
83 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
85 return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
88 /***************************************************************************
90 * DP and MEM-AP register access through APACC and DPACC *
92 ***************************************************************************/
95 * Select one of the APs connected to the specified DAP. The
96 * selection is implicitly used with future AP transactions.
97 * This is a NOP if the specified AP is already selected.
100 * @param apsel Number of the AP to (implicitly) use with further
101 * transactions. This normally identifies a MEM-AP.
103 void dap_ap_select(struct adiv5_dap *dap, uint8_t ap)
105 uint32_t new_ap = (ap << 24) & 0xFF000000;
107 if (new_ap != dap->ap_current) {
108 dap->ap_current = new_ap;
109 /* Switching AP invalidates cached values.
110 * Values MUST BE UPDATED BEFORE AP ACCESS.
112 dap->ap_bank_value = -1;
113 dap->ap_csw_value = -1;
114 dap->ap_tar_value = -1;
119 * Queue transactions setting up transfer parameters for the
120 * currently selected MEM-AP.
122 * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
123 * initiate data reads or writes using memory or peripheral addresses.
124 * If the CSW is configured for it, the TAR may be automatically
125 * incremented after each transfer.
127 * @todo Rename to reflect it being specifically a MEM-AP function.
129 * @param dap The DAP connected to the MEM-AP.
130 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
131 * matches the cached value, the register is not changed.
132 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
133 * matches the cached address, the register is not changed.
135 * @return ERROR_OK if the transaction was properly queued, else a fault code.
137 int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
141 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
142 if (csw != dap->ap_csw_value) {
143 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
144 retval = dap_queue_ap_write(dap, AP_REG_CSW, csw);
145 if (retval != ERROR_OK)
147 dap->ap_csw_value = csw;
149 if (tar != dap->ap_tar_value) {
150 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
151 retval = dap_queue_ap_write(dap, AP_REG_TAR, tar);
152 if (retval != ERROR_OK)
154 dap->ap_tar_value = tar;
156 /* Disable TAR cache when autoincrementing */
157 if (csw & CSW_ADDRINC_MASK)
158 dap->ap_tar_value = -1;
163 * Asynchronous (queued) read of a word from memory or a system register.
165 * @param dap The DAP connected to the MEM-AP performing the read.
166 * @param address Address of the 32-bit word to read; it must be
167 * readable by the currently selected MEM-AP.
168 * @param value points to where the word will be stored when the
169 * transaction queue is flushed (assuming no errors).
171 * @return ERROR_OK for success. Otherwise a fault code.
173 int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
178 /* Use banked addressing (REG_BDx) to avoid some link traffic
179 * (updating TAR) when reading several consecutive addresses.
181 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
182 address & 0xFFFFFFF0);
183 if (retval != ERROR_OK)
186 return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value);
190 * Synchronous read of a word from memory or a system register.
191 * As a side effect, this flushes any queued transactions.
193 * @param dap The DAP connected to the MEM-AP performing the read.
194 * @param address Address of the 32-bit word to read; it must be
195 * readable by the currently selected MEM-AP.
196 * @param value points to where the result will be stored.
198 * @return ERROR_OK for success; *value holds the result.
199 * Otherwise a fault code.
201 int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
206 retval = mem_ap_read_u32(dap, address, value);
207 if (retval != ERROR_OK)
214 * Asynchronous (queued) write of a word to memory or a system register.
216 * @param dap The DAP connected to the MEM-AP.
217 * @param address Address to be written; it must be writable by
218 * the currently selected MEM-AP.
219 * @param value Word that will be written to the address when transaction
220 * queue is flushed (assuming no errors).
222 * @return ERROR_OK for success. Otherwise a fault code.
224 int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
229 /* Use banked addressing (REG_BDx) to avoid some link traffic
230 * (updating TAR) when writing several consecutive addresses.
232 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
233 address & 0xFFFFFFF0);
234 if (retval != ERROR_OK)
237 return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC),
242 * Synchronous write of a word to memory or a system register.
243 * As a side effect, this flushes any queued transactions.
245 * @param dap The DAP connected to the MEM-AP.
246 * @param address Address to be written; it must be writable by
247 * the currently selected MEM-AP.
248 * @param value Word that will be written.
250 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
252 int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
255 int retval = mem_ap_write_u32(dap, address, value);
257 if (retval != ERROR_OK)
263 /*****************************************************************************
265 * mem_ap_write_buf(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address) *
267 * Write a buffer in target order (little endian) *
269 *****************************************************************************/
270 int mem_ap_write_buf_u32(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
272 int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
273 uint32_t adr = address;
274 const uint8_t *pBuffer = buffer;
279 /* if we have an unaligned access - reorder data */
281 for (writecount = 0; writecount < count; writecount++) {
284 memcpy(&outvalue, pBuffer, sizeof(uint32_t));
286 for (i = 0; i < 4; i++) {
287 *((uint8_t *)pBuffer + (adr & 0x3)) = outvalue;
291 pBuffer += sizeof(uint32_t);
296 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
297 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
298 if (wcount < blocksize)
301 /* handle unaligned data at 4k boundary */
305 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
306 if (retval != ERROR_OK)
309 for (writecount = 0; writecount < blocksize; writecount++) {
310 retval = dap_queue_ap_write(dap, AP_REG_DRW,
311 *(uint32_t *) ((void *) (buffer + 4 * writecount)));
312 if (retval != ERROR_OK)
316 retval = dap_run(dap);
317 if (retval == ERROR_OK) {
318 wcount = wcount - blocksize;
319 address = address + 4 * blocksize;
320 buffer = buffer + 4 * blocksize;
324 if (errorcount > 1) {
325 LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
333 static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap,
334 const uint8_t *buffer, int count, uint32_t address)
336 int retval = ERROR_OK;
337 int wcount, blocksize, writecount, i;
344 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
345 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
347 if (wcount < blocksize)
350 /* handle unaligned data at 4k boundary */
354 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
355 if (retval != ERROR_OK)
357 writecount = blocksize;
360 nbytes = MIN((writecount << 1), 4);
363 retval = mem_ap_write_buf_u16(dap, buffer,
365 if (retval != ERROR_OK) {
366 LOG_WARNING("Block write error address "
367 "0x%" PRIx32 ", count 0x%x",
372 address += nbytes >> 1;
375 memcpy(&outvalue, buffer, sizeof(uint32_t));
377 for (i = 0; i < nbytes; i++) {
378 *((uint8_t *)buffer + (address & 0x3)) = outvalue;
383 memcpy(&outvalue, buffer, sizeof(uint32_t));
384 retval = dap_queue_ap_write(dap,
385 AP_REG_DRW, outvalue);
386 if (retval != ERROR_OK)
389 retval = dap_run(dap);
390 if (retval != ERROR_OK) {
391 LOG_WARNING("Block write error address "
392 "0x%" PRIx32 ", count 0x%x",
398 buffer += nbytes >> 1;
399 writecount -= nbytes >> 1;
401 } while (writecount);
408 int mem_ap_write_buf_u16(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
410 int retval = ERROR_OK;
413 return mem_ap_write_buf_packed_u16(dap, buffer, count, address);
416 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
417 if (retval != ERROR_OK)
420 memcpy(&svalue, buffer, sizeof(uint16_t));
421 uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
422 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
423 if (retval != ERROR_OK)
426 retval = dap_run(dap);
427 if (retval != ERROR_OK)
438 static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap,
439 const uint8_t *buffer, int count, uint32_t address)
441 int retval = ERROR_OK;
442 int wcount, blocksize, writecount, i;
449 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
450 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
452 if (wcount < blocksize)
455 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
456 if (retval != ERROR_OK)
458 writecount = blocksize;
461 nbytes = MIN(writecount, 4);
464 retval = mem_ap_write_buf_u8(dap, buffer, nbytes, address);
465 if (retval != ERROR_OK) {
466 LOG_WARNING("Block write error address "
467 "0x%" PRIx32 ", count 0x%x",
475 memcpy(&outvalue, buffer, sizeof(uint32_t));
477 for (i = 0; i < nbytes; i++) {
478 *((uint8_t *)buffer + (address & 0x3)) = outvalue;
483 memcpy(&outvalue, buffer, sizeof(uint32_t));
484 retval = dap_queue_ap_write(dap,
485 AP_REG_DRW, outvalue);
486 if (retval != ERROR_OK)
489 retval = dap_run(dap);
490 if (retval != ERROR_OK) {
491 LOG_WARNING("Block write error address "
492 "0x%" PRIx32 ", count 0x%x",
499 writecount -= nbytes;
501 } while (writecount);
508 int mem_ap_write_buf_u8(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
510 int retval = ERROR_OK;
513 return mem_ap_write_buf_packed_u8(dap, buffer, count, address);
516 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
517 if (retval != ERROR_OK)
519 uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
520 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
521 if (retval != ERROR_OK)
524 retval = dap_run(dap);
525 if (retval != ERROR_OK)
536 /* FIXME don't import ... this is a temporary workaround for the
537 * mem_ap_read_buf_u32() mess, until it's no longer JTAG-specific.
539 extern int adi_jtag_dp_scan(struct adiv5_dap *dap,
540 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
541 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack);
544 * Synchronously read a block of 32-bit words into a buffer
545 * @param dap The DAP connected to the MEM-AP.
546 * @param buffer where the words will be stored (in host byte order).
547 * @param count How many words to read.
548 * @param address Memory address from which to read words; all the
549 * words must be readable by the currently selected MEM-AP.
551 int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer,
552 int count, uint32_t address)
554 int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
555 uint32_t adr = address;
556 uint8_t *pBuffer = buffer;
562 /* Adjust to read blocks within boundaries aligned to the
563 * TAR autoincrement size (at least 2^10). Autoincrement
564 * mode avoids an extra per-word roundtrip to update TAR.
566 blocksize = max_tar_block_size(dap->tar_autoincr_block,
568 if (wcount < blocksize)
571 /* handle unaligned data at 4k boundary */
575 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE,
577 if (retval != ERROR_OK)
580 /* FIXME remove these three calls to adi_jtag_dp_scan(),
581 * so this routine becomes transport-neutral. Be careful
582 * not to cause performance problems with JTAG; would it
583 * suffice to loop over dap_queue_ap_read(), or would that
584 * be slower when JTAG is the chosen transport?
587 /* Scan out first read */
588 retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
589 DPAP_READ, 0, NULL, NULL);
590 if (retval != ERROR_OK)
592 for (readcount = 0; readcount < blocksize - 1; readcount++) {
593 /* Scan out next read; scan in posted value for the
594 * previous one. Assumes read is acked "OK/FAULT",
595 * and CTRL_STAT says that meant "OK".
597 retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
598 DPAP_READ, 0, buffer + 4 * readcount,
600 if (retval != ERROR_OK)
604 /* Scan in last posted value; RDBUFF has no other effect,
605 * assuming ack is OK/FAULT and CTRL_STAT says "OK".
607 retval = adi_jtag_dp_scan(dap, JTAG_DP_DPACC, DP_RDBUFF,
608 DPAP_READ, 0, buffer + 4 * readcount,
610 if (retval != ERROR_OK)
613 retval = dap_run(dap);
614 if (retval != ERROR_OK) {
616 if (errorcount <= 1) {
620 LOG_WARNING("Block read error address 0x%" PRIx32, address);
623 wcount = wcount - blocksize;
624 address += 4 * blocksize;
625 buffer += 4 * blocksize;
628 /* if we have an unaligned access - reorder data */
630 for (readcount = 0; readcount < count; readcount++) {
633 memcpy(&data, pBuffer, sizeof(uint32_t));
635 for (i = 0; i < 4; i++) {
636 *((uint8_t *)pBuffer) =
637 (data >> 8 * (adr & 0x3));
647 static int mem_ap_read_buf_packed_u16(struct adiv5_dap *dap,
648 uint8_t *buffer, int count, uint32_t address)
651 int retval = ERROR_OK;
652 int wcount, blocksize, readcount, i;
659 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
660 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
661 if (wcount < blocksize)
664 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
665 if (retval != ERROR_OK)
668 /* handle unaligned data at 4k boundary */
671 readcount = blocksize;
674 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
675 if (retval != ERROR_OK)
677 retval = dap_run(dap);
678 if (retval != ERROR_OK) {
679 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
683 nbytes = MIN((readcount << 1), 4);
685 for (i = 0; i < nbytes; i++) {
686 *((uint8_t *)buffer) = (invalue >> 8 * (address & 0x3));
691 readcount -= (nbytes >> 1);
700 * Synchronously read a block of 16-bit halfwords into a buffer
701 * @param dap The DAP connected to the MEM-AP.
702 * @param buffer where the halfwords will be stored (in host byte order).
703 * @param count How many halfwords to read.
704 * @param address Memory address from which to read words; all the
705 * words must be readable by the currently selected MEM-AP.
707 int mem_ap_read_buf_u16(struct adiv5_dap *dap, uint8_t *buffer,
708 int count, uint32_t address)
711 int retval = ERROR_OK;
714 return mem_ap_read_buf_packed_u16(dap, buffer, count, address);
717 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
718 if (retval != ERROR_OK)
720 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
721 if (retval != ERROR_OK)
724 retval = dap_run(dap);
725 if (retval != ERROR_OK)
729 for (i = 0; i < 2; i++) {
730 *((uint8_t *)buffer) = (invalue >> 8 * (address & 0x3));
735 uint16_t svalue = (invalue >> 8 * (address & 0x3));
736 memcpy(buffer, &svalue, sizeof(uint16_t));
746 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
747 * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
749 * The solution is to arrange for a large out/in scan in this loop and
750 * and convert data afterwards.
752 static int mem_ap_read_buf_packed_u8(struct adiv5_dap *dap,
753 uint8_t *buffer, int count, uint32_t address)
756 int retval = ERROR_OK;
757 int wcount, blocksize, readcount, i;
764 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
765 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
767 if (wcount < blocksize)
770 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
771 if (retval != ERROR_OK)
773 readcount = blocksize;
776 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
777 if (retval != ERROR_OK)
779 retval = dap_run(dap);
780 if (retval != ERROR_OK) {
781 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
785 nbytes = MIN(readcount, 4);
787 for (i = 0; i < nbytes; i++) {
788 *((uint8_t *)buffer) = (invalue >> 8 * (address & 0x3));
802 * Synchronously read a block of bytes into a buffer
803 * @param dap The DAP connected to the MEM-AP.
804 * @param buffer where the bytes will be stored.
805 * @param count How many bytes to read.
806 * @param address Memory address from which to read data; all the
807 * data must be readable by the currently selected MEM-AP.
809 int mem_ap_read_buf_u8(struct adiv5_dap *dap, uint8_t *buffer,
810 int count, uint32_t address)
813 int retval = ERROR_OK;
816 return mem_ap_read_buf_packed_u8(dap, buffer, count, address);
819 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
820 if (retval != ERROR_OK)
822 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
823 if (retval != ERROR_OK)
825 retval = dap_run(dap);
826 if (retval != ERROR_OK)
829 *((uint8_t *)buffer) = (invalue >> 8 * (address & 0x3));
838 /*--------------------------------------------------------------------*/
839 /* Wrapping function with selection of AP */
840 /*--------------------------------------------------------------------*/
841 int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
842 uint32_t address, uint32_t *value)
844 dap_ap_select(swjdp, ap);
845 return mem_ap_read_u32(swjdp, address, value);
848 int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap,
849 uint32_t address, uint32_t value)
851 dap_ap_select(swjdp, ap);
852 return mem_ap_write_u32(swjdp, address, value);
855 int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
856 uint32_t address, uint32_t *value)
858 dap_ap_select(swjdp, ap);
859 return mem_ap_read_atomic_u32(swjdp, address, value);
862 int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
863 uint32_t address, uint32_t value)
865 dap_ap_select(swjdp, ap);
866 return mem_ap_write_atomic_u32(swjdp, address, value);
869 int mem_ap_sel_read_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
870 uint8_t *buffer, int count, uint32_t address)
872 dap_ap_select(swjdp, ap);
873 return mem_ap_read_buf_u8(swjdp, buffer, count, address);
876 int mem_ap_sel_read_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
877 uint8_t *buffer, int count, uint32_t address)
879 dap_ap_select(swjdp, ap);
880 return mem_ap_read_buf_u16(swjdp, buffer, count, address);
883 int mem_ap_sel_read_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
884 uint8_t *buffer, int count, uint32_t address)
886 dap_ap_select(swjdp, ap);
887 return mem_ap_read_buf_u32(swjdp, buffer, count, address);
890 int mem_ap_sel_write_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
891 const uint8_t *buffer, int count, uint32_t address)
893 dap_ap_select(swjdp, ap);
894 return mem_ap_write_buf_u8(swjdp, buffer, count, address);
897 int mem_ap_sel_write_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
898 const uint8_t *buffer, int count, uint32_t address)
900 dap_ap_select(swjdp, ap);
901 return mem_ap_write_buf_u16(swjdp, buffer, count, address);
904 int mem_ap_sel_write_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
905 const uint8_t *buffer, int count, uint32_t address)
907 dap_ap_select(swjdp, ap);
908 return mem_ap_write_buf_u32(swjdp, buffer, count, address);
911 #define MDM_REG_STAT 0x00
912 #define MDM_REG_CTRL 0x04
913 #define MDM_REG_ID 0xfc
915 #define MDM_STAT_FMEACK (1<<0)
916 #define MDM_STAT_FREADY (1<<1)
917 #define MDM_STAT_SYSSEC (1<<2)
918 #define MDM_STAT_SYSRES (1<<3)
919 #define MDM_STAT_FMEEN (1<<5)
920 #define MDM_STAT_BACKDOOREN (1<<6)
921 #define MDM_STAT_LPEN (1<<7)
922 #define MDM_STAT_VLPEN (1<<8)
923 #define MDM_STAT_LLSMODEXIT (1<<9)
924 #define MDM_STAT_VLLSXMODEXIT (1<<10)
925 #define MDM_STAT_CORE_HALTED (1<<16)
926 #define MDM_STAT_CORE_SLEEPDEEP (1<<17)
927 #define MDM_STAT_CORESLEEPING (1<<18)
929 #define MEM_CTRL_FMEIP (1<<0)
930 #define MEM_CTRL_DBG_DIS (1<<1)
931 #define MEM_CTRL_DBG_REQ (1<<2)
932 #define MEM_CTRL_SYS_RES_REQ (1<<3)
933 #define MEM_CTRL_CORE_HOLD_RES (1<<4)
934 #define MEM_CTRL_VLLSX_DBG_REQ (1<<5)
935 #define MEM_CTRL_VLLSX_DBG_ACK (1<<6)
936 #define MEM_CTRL_VLLSX_STAT_ACK (1<<7)
941 int dap_syssec_kinetis_mdmap(struct adiv5_dap *dap)
945 enum reset_types jtag_reset_config = jtag_get_reset_config();
947 dap_ap_select(dap, 1);
949 /* first check mdm-ap id register */
950 retval = dap_queue_ap_read(dap, MDM_REG_ID, &val);
951 if (retval != ERROR_OK)
955 if (val != 0x001C0000) {
956 LOG_DEBUG("id doesn't match %08X != 0x001C0000", val);
957 dap_ap_select(dap, 0);
961 /* read and parse status register
962 * it's important that the device is out of
965 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
966 if (retval != ERROR_OK)
970 LOG_DEBUG("MDM_REG_STAT %08X", val);
972 if ((val & (MDM_STAT_SYSSEC|MDM_STAT_FREADY)) != (MDM_STAT_FREADY)) {
973 LOG_DEBUG("MDMAP: system is secured, masserase needed");
975 if (!(val & MDM_STAT_FMEEN))
976 LOG_DEBUG("MDMAP: masserase is disabled");
978 /* we need to assert reset */
979 if (jtag_reset_config & RESET_HAS_SRST) {
980 /* default to asserting srst */
981 adapter_assert_reset();
983 LOG_DEBUG("SRST not configured");
984 dap_ap_select(dap, 0);
989 retval = dap_queue_ap_write(dap, MDM_REG_CTRL, MEM_CTRL_FMEIP);
990 if (retval != ERROR_OK)
993 /* read status register and wait for ready */
994 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
995 if (retval != ERROR_OK)
998 LOG_DEBUG("MDM_REG_STAT %08X", val);
1005 retval = dap_queue_ap_write(dap, MDM_REG_CTRL, 0);
1006 if (retval != ERROR_OK)
1009 /* read status register */
1010 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
1011 if (retval != ERROR_OK)
1014 LOG_DEBUG("MDM_REG_STAT %08X", val);
1015 /* read control register and wait for ready */
1016 retval = dap_queue_ap_read(dap, MDM_REG_CTRL, &val);
1017 if (retval != ERROR_OK)
1020 LOG_DEBUG("MDM_REG_CTRL %08X", val);
1028 dap_ap_select(dap, 0);
1034 struct dap_syssec_filter {
1038 int (*dap_init)(struct adiv5_dap *dap);
1042 static struct dap_syssec_filter dap_syssec_filter_data[] = {
1043 { 0x4BA00477, dap_syssec_kinetis_mdmap }
1049 int dap_syssec(struct adiv5_dap *dap)
1052 struct jtag_tap *tap;
1054 for (i = 0; i < sizeof(dap_syssec_filter_data); i++) {
1055 tap = dap->jtag_info->tap;
1057 while (tap != NULL) {
1058 if (tap->hasidcode && (dap_syssec_filter_data[i].idcode == tap->idcode)) {
1059 LOG_DEBUG("DAP: mdmap_init for idcode: %08x", tap->idcode);
1060 dap_syssec_filter_data[i].dap_init(dap);
1062 tap = tap->next_tap;
1069 /*--------------------------------------------------------------------------*/
1072 /* FIXME don't import ... just initialize as
1073 * part of DAP transport setup
1075 extern const struct dap_ops jtag_dp_ops;
1077 /*--------------------------------------------------------------------------*/
1080 * Initialize a DAP. This sets up the power domains, prepares the DP
1081 * for further use, and arranges to use AP #0 for all AP operations
1082 * until dap_ap-select() changes that policy.
1084 * @param dap The DAP being initialized.
1086 * @todo Rename this. We also need an initialization scheme which account
1087 * for SWD transports not just JTAG; that will need to address differences
1088 * in layering. (JTAG is useful without any debug target; but not SWD.)
1089 * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
1091 int ahbap_debugport_init(struct adiv5_dap *dap)
1099 /* JTAG-DP or SWJ-DP, in JTAG mode
1100 * ... for SWD mode this is patched as part
1101 * of link switchover
1104 dap->ops = &jtag_dp_ops;
1106 /* Default MEM-AP setup.
1108 * REVISIT AP #0 may be an inappropriate default for this.
1109 * Should we probe, or take a hint from the caller?
1110 * Presumably we can ignore the possibility of multiple APs.
1112 dap->ap_current = !0;
1113 dap_ap_select(dap, 0);
1115 /* DP initialization */
1117 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1118 if (retval != ERROR_OK)
1121 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
1122 if (retval != ERROR_OK)
1125 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1126 if (retval != ERROR_OK)
1129 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
1130 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
1131 if (retval != ERROR_OK)
1134 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
1135 if (retval != ERROR_OK)
1137 retval = dap_run(dap);
1138 if (retval != ERROR_OK)
1141 /* Check that we have debug power domains activated */
1142 while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10)) {
1143 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
1144 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
1145 if (retval != ERROR_OK)
1147 retval = dap_run(dap);
1148 if (retval != ERROR_OK)
1153 while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10)) {
1154 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
1155 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
1156 if (retval != ERROR_OK)
1158 retval = dap_run(dap);
1159 if (retval != ERROR_OK)
1164 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1165 if (retval != ERROR_OK)
1167 /* With debug power on we can activate OVERRUN checking */
1168 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
1169 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
1170 if (retval != ERROR_OK)
1172 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1173 if (retval != ERROR_OK)
1181 /* CID interpretation -- see ARM IHI 0029B section 3
1182 * and ARM IHI 0031A table 13-3.
1184 static const char *class_description[16] = {
1185 "Reserved", "ROM table", "Reserved", "Reserved",
1186 "Reserved", "Reserved", "Reserved", "Reserved",
1187 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1188 "Reserved", "OptimoDE DESS",
1189 "Generic IP component", "PrimeCell or System component"
1192 static bool is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
1194 return cid3 == 0xb1 && cid2 == 0x05
1195 && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1198 int dap_get_debugbase(struct adiv5_dap *dap, int ap,
1199 uint32_t *out_dbgbase, uint32_t *out_apid)
1203 uint32_t dbgbase, apid;
1205 /* AP address is in bits 31:24 of DP_SELECT */
1207 return ERROR_COMMAND_SYNTAX_ERROR;
1209 ap_old = dap->ap_current;
1210 dap_ap_select(dap, ap);
1212 retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase);
1213 if (retval != ERROR_OK)
1215 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1216 if (retval != ERROR_OK)
1218 retval = dap_run(dap);
1219 if (retval != ERROR_OK)
1222 /* Excavate the device ID code */
1223 struct jtag_tap *tap = dap->jtag_info->tap;
1224 while (tap != NULL) {
1227 tap = tap->next_tap;
1229 if (tap == NULL || !tap->hasidcode)
1232 dap_ap_select(dap, ap_old);
1234 /* The asignment happens only here to prevent modification of these
1235 * values before they are certain. */
1236 *out_dbgbase = dbgbase;
1242 int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
1243 uint32_t dbgbase, uint8_t type, uint32_t *addr)
1246 uint32_t romentry, entry_offset = 0, component_base, devtype;
1247 int retval = ERROR_FAIL;
1250 return ERROR_COMMAND_SYNTAX_ERROR;
1252 ap_old = dap->ap_current;
1253 dap_ap_select(dap, ap);
1256 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) |
1257 entry_offset, &romentry);
1258 if (retval != ERROR_OK)
1261 component_base = (dbgbase & 0xFFFFF000)
1262 + (romentry & 0xFFFFF000);
1264 if (romentry & 0x1) {
1265 retval = mem_ap_read_atomic_u32(dap,
1266 (component_base & 0xfffff000) | 0xfcc,
1268 if ((devtype & 0xff) == type) {
1269 *addr = component_base;
1275 } while (romentry > 0);
1277 dap_ap_select(dap, ap_old);
1282 static int dap_info_command(struct command_context *cmd_ctx,
1283 struct adiv5_dap *dap, int ap)
1286 uint32_t dbgbase = 0, apid = 0; /* Silence gcc by initializing */
1287 int romtable_present = 0;
1291 retval = dap_get_debugbase(dap, ap, &dbgbase, &apid);
1292 if (retval != ERROR_OK)
1295 ap_old = dap->ap_current;
1296 dap_ap_select(dap, ap);
1298 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1299 mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1300 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1302 switch (apid&0x0F) {
1304 command_print(cmd_ctx, "\tType is JTAG-AP");
1307 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1310 command_print(cmd_ctx, "\tType is MEM-AP APB");
1313 command_print(cmd_ctx, "\tUnknown AP type");
1317 /* NOTE: a MEM-AP may have a single CoreSight component that's
1318 * not a ROM table ... or have no such components at all.
1321 command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32, dbgbase);
1323 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap);
1325 romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1326 if (romtable_present) {
1327 uint32_t cid0, cid1, cid2, cid3, memtype, romentry;
1328 uint16_t entry_offset;
1330 /* bit 16 of apid indicates a memory access port */
1332 command_print(cmd_ctx, "\tValid ROM table present");
1334 command_print(cmd_ctx, "\tROM table in legacy format");
1336 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1337 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1338 if (retval != ERROR_OK)
1340 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1341 if (retval != ERROR_OK)
1343 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1344 if (retval != ERROR_OK)
1346 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1347 if (retval != ERROR_OK)
1349 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1350 if (retval != ERROR_OK)
1352 retval = dap_run(dap);
1353 if (retval != ERROR_OK)
1356 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1357 command_print(cmd_ctx, "\tCID3 0x%2.2x"
1361 (unsigned) cid3, (unsigned)cid2,
1362 (unsigned) cid1, (unsigned) cid0);
1364 command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1366 command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1367 "Dedicated debug bus.");
1369 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1372 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1373 if (retval != ERROR_OK)
1375 command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "", entry_offset, romentry);
1376 if (romentry & 0x01) {
1377 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1378 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1379 uint32_t component_base;
1383 component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000);
1385 /* IDs are in last 4K section */
1386 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE0, &c_pid0);
1387 if (retval != ERROR_OK)
1390 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE4, &c_pid1);
1391 if (retval != ERROR_OK)
1394 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE8, &c_pid2);
1395 if (retval != ERROR_OK)
1398 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFEC, &c_pid3);
1399 if (retval != ERROR_OK)
1402 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFD0, &c_pid4);
1403 if (retval != ERROR_OK)
1407 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF0, &c_cid0);
1408 if (retval != ERROR_OK)
1411 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF4, &c_cid1);
1412 if (retval != ERROR_OK)
1415 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF8, &c_cid2);
1416 if (retval != ERROR_OK)
1419 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFFC, &c_cid3);
1420 if (retval != ERROR_OK)
1424 command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 ","
1425 "start address 0x%" PRIx32, component_base,
1426 /* component may take multiple 4K pages */
1427 component_base - 0x1000*(c_pid4 >> 4));
1428 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1429 (int) (c_cid1 >> 4) & 0xf,
1430 /* See ARM IHI 0029B Table 3-3 */
1431 class_description[(c_cid1 >> 4) & 0xf]);
1433 /* CoreSight component? */
1434 if (((c_cid1 >> 4) & 0x0f) == 9) {
1437 char *major = "Reserved", *subtype = "Reserved";
1439 retval = mem_ap_read_atomic_u32(dap,
1440 (component_base & 0xfffff000) | 0xfcc,
1442 if (retval != ERROR_OK)
1444 minor = (devtype >> 4) & 0x0f;
1445 switch (devtype & 0x0f) {
1447 major = "Miscellaneous";
1453 subtype = "Validation component";
1458 major = "Trace Sink";
1472 major = "Trace Link";
1478 subtype = "Funnel, router";
1484 subtype = "FIFO, buffer";
1489 major = "Trace Source";
1495 subtype = "Processor";
1501 subtype = "Engine/Coprocessor";
1509 major = "Debug Control";
1515 subtype = "Trigger Matrix";
1518 subtype = "Debug Auth";
1523 major = "Debug Logic";
1529 subtype = "Processor";
1535 subtype = "Engine/Coprocessor";
1540 command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1541 (unsigned) (devtype & 0xff),
1543 /* REVISIT also show 0xfc8 DevId */
1546 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1547 command_print(cmd_ctx,
1556 command_print(cmd_ctx,
1557 "\t\tPeripheral ID[4..0] = hex "
1558 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1559 (int) c_pid4, (int) c_pid3, (int) c_pid2,
1560 (int) c_pid1, (int) c_pid0);
1562 /* Part number interpretations are from Cortex
1563 * core specs, the CoreSight components TRM
1564 * (ARM DDI 0314H), CoreSight System Design
1565 * Guide (ARM DGI 0012D) and ETM specs; also
1566 * from chip observation (e.g. TI SDTI).
1568 part_num = (c_pid0 & 0xff);
1569 part_num |= (c_pid1 & 0x0f) << 8;
1572 type = "Cortex-M3 NVIC";
1573 full = "(Interrupt Controller)";
1576 type = "Cortex-M3 ITM";
1577 full = "(Instrumentation Trace Module)";
1580 type = "Cortex-M3 DWT";
1581 full = "(Data Watchpoint and Trace)";
1584 type = "Cortex-M3 FBP";
1585 full = "(Flash Patch and Breakpoint)";
1588 type = "CoreSight ETM11";
1589 full = "(Embedded Trace)";
1591 /* case 0x113: what? */
1592 case 0x120: /* from OMAP3 memmap */
1594 full = "(System Debug Trace Interface)";
1596 case 0x343: /* from OMAP3 memmap */
1601 type = "Coresight CTI";
1602 full = "(Cross Trigger)";
1605 type = "Coresight ETB";
1606 full = "(Trace Buffer)";
1609 type = "Coresight CSTF";
1610 full = "(Trace Funnel)";
1613 type = "CoreSight ETM9";
1614 full = "(Embedded Trace)";
1617 type = "Coresight TPIU";
1618 full = "(Trace Port Interface Unit)";
1621 type = "Cortex-A8 ETM";
1622 full = "(Embedded Trace)";
1625 type = "Cortex-A8 CTI";
1626 full = "(Cross Trigger)";
1629 type = "Cortex-M3 TPIU";
1630 full = "(Trace Port Interface Unit)";
1633 type = "Cortex-M3 ETM";
1634 full = "(Embedded Trace)";
1637 type = "Cortex-R4 ETM";
1638 full = "(Embedded Trace)";
1641 type = "Cortex-A8 Debug";
1642 full = "(Debug Unit)";
1645 type = "-*- unrecognized -*-";
1649 command_print(cmd_ctx, "\t\tPart is %s %s",
1653 command_print(cmd_ctx, "\t\tComponent not present");
1655 command_print(cmd_ctx, "\t\tEnd of ROM table");
1658 } while (romentry > 0);
1660 command_print(cmd_ctx, "\tNo ROM table present");
1661 dap_ap_select(dap, ap_old);
1666 COMMAND_HANDLER(handle_dap_info_command)
1668 struct target *target = get_current_target(CMD_CTX);
1669 struct arm *arm = target_to_arm(target);
1670 struct adiv5_dap *dap = arm->dap;
1678 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1681 return ERROR_COMMAND_SYNTAX_ERROR;
1684 return dap_info_command(CMD_CTX, dap, apsel);
1687 COMMAND_HANDLER(dap_baseaddr_command)
1689 struct target *target = get_current_target(CMD_CTX);
1690 struct arm *arm = target_to_arm(target);
1691 struct adiv5_dap *dap = arm->dap;
1693 uint32_t apsel, baseaddr;
1701 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1702 /* AP address is in bits 31:24 of DP_SELECT */
1704 return ERROR_COMMAND_SYNTAX_ERROR;
1707 return ERROR_COMMAND_SYNTAX_ERROR;
1710 dap_ap_select(dap, apsel);
1712 /* NOTE: assumes we're talking to a MEM-AP, which
1713 * has a base address. There are other kinds of AP,
1714 * though they're not common for now. This should
1715 * use the ID register to verify it's a MEM-AP.
1717 retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
1718 if (retval != ERROR_OK)
1720 retval = dap_run(dap);
1721 if (retval != ERROR_OK)
1724 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1729 COMMAND_HANDLER(dap_memaccess_command)
1731 struct target *target = get_current_target(CMD_CTX);
1732 struct arm *arm = target_to_arm(target);
1733 struct adiv5_dap *dap = arm->dap;
1735 uint32_t memaccess_tck;
1739 memaccess_tck = dap->memaccess_tck;
1742 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1745 return ERROR_COMMAND_SYNTAX_ERROR;
1747 dap->memaccess_tck = memaccess_tck;
1749 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1750 dap->memaccess_tck);
1755 COMMAND_HANDLER(dap_apsel_command)
1757 struct target *target = get_current_target(CMD_CTX);
1758 struct arm *arm = target_to_arm(target);
1759 struct adiv5_dap *dap = arm->dap;
1761 uint32_t apsel, apid;
1769 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1770 /* AP address is in bits 31:24 of DP_SELECT */
1772 return ERROR_COMMAND_SYNTAX_ERROR;
1775 return ERROR_COMMAND_SYNTAX_ERROR;
1779 dap_ap_select(dap, apsel);
1781 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1782 if (retval != ERROR_OK)
1784 retval = dap_run(dap);
1785 if (retval != ERROR_OK)
1788 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1794 COMMAND_HANDLER(dap_apid_command)
1796 struct target *target = get_current_target(CMD_CTX);
1797 struct arm *arm = target_to_arm(target);
1798 struct adiv5_dap *dap = arm->dap;
1800 uint32_t apsel, apid;
1808 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1809 /* AP address is in bits 31:24 of DP_SELECT */
1811 return ERROR_COMMAND_SYNTAX_ERROR;
1814 return ERROR_COMMAND_SYNTAX_ERROR;
1817 dap_ap_select(dap, apsel);
1819 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1820 if (retval != ERROR_OK)
1822 retval = dap_run(dap);
1823 if (retval != ERROR_OK)
1826 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1831 static const struct command_registration dap_commands[] = {
1834 .handler = handle_dap_info_command,
1835 .mode = COMMAND_EXEC,
1836 .help = "display ROM table for MEM-AP "
1837 "(default currently selected AP)",
1838 .usage = "[ap_num]",
1842 .handler = dap_apsel_command,
1843 .mode = COMMAND_EXEC,
1844 .help = "Set the currently selected AP (default 0) "
1845 "and display the result",
1846 .usage = "[ap_num]",
1850 .handler = dap_apid_command,
1851 .mode = COMMAND_EXEC,
1852 .help = "return ID register from AP "
1853 "(default currently selected AP)",
1854 .usage = "[ap_num]",
1858 .handler = dap_baseaddr_command,
1859 .mode = COMMAND_EXEC,
1860 .help = "return debug base address from MEM-AP "
1861 "(default currently selected AP)",
1862 .usage = "[ap_num]",
1865 .name = "memaccess",
1866 .handler = dap_memaccess_command,
1867 .mode = COMMAND_EXEC,
1868 .help = "set/get number of extra tck for MEM-AP memory "
1869 "bus access [0-255]",
1870 .usage = "[cycles]",
1872 COMMAND_REGISTRATION_DONE
1875 const struct command_registration dap_command_handlers[] = {
1878 .mode = COMMAND_EXEC,
1879 .help = "DAP command group",
1881 .chain = dap_commands,
1883 COMMAND_REGISTRATION_DONE