1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
20 ***************************************************************************/
22 #ifndef OPENOCD_TARGET_ARM_ADI_V5_H
23 #define OPENOCD_TARGET_ARM_ADI_V5_H
27 * This defines formats and data structures used to talk to ADIv5 entities.
28 * Those include a DAP, different types of Debug Port (DP), and memory mapped
29 * resources accessed through a MEM-AP.
32 #include <helper/list.h>
35 /* three-bit ACK values for SWD access (sent LSB first) */
36 #define SWD_ACK_OK 0x1
37 #define SWD_ACK_WAIT 0x2
38 #define SWD_ACK_FAULT 0x4
43 #define BANK_REG(bank, reg) (((bank) << 4) | (reg))
45 /* A[3:0] for DP registers; A[1:0] are always zero.
46 * - JTAG accesses all of these via JTAG_DP_DPACC, except for
47 * IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT).
48 * - SWD accesses these directly, sometimes needing SELECT.DPBANKSEL
50 #define DP_DPIDR BANK_REG(0x0, 0x0) /* DPv1+: ro */
51 #define DP_ABORT BANK_REG(0x0, 0x0) /* DPv1+: SWD: wo */
52 #define DP_CTRL_STAT BANK_REG(0x0, 0x4) /* DPv0+: rw */
53 #define DP_DLCR BANK_REG(0x1, 0x4) /* DPv1+: SWD: rw */
54 #define DP_TARGETID BANK_REG(0x2, 0x4) /* DPv2: ro */
55 #define DP_DLPIDR BANK_REG(0x3, 0x4) /* DPv2: ro */
56 #define DP_EVENTSTAT BANK_REG(0x4, 0x4) /* DPv2: ro */
57 #define DP_RESEND BANK_REG(0x0, 0x8) /* DPv1+: SWD: ro */
58 #define DP_SELECT BANK_REG(0x0, 0x8) /* DPv0+: JTAG: rw; SWD: wo */
59 #define DP_RDBUFF BANK_REG(0x0, 0xC) /* DPv0+: ro */
60 #define DP_TARGETSEL BANK_REG(0x0, 0xC) /* DPv2: SWD: wo */
62 #define DLCR_TO_TRN(dlcr) ((uint32_t)(1 + ((3 & (dlcr)) >> 8))) /* 1..4 clocks */
64 /* Fields of the DP's AP ABORT register */
65 #define DAPABORT (1UL << 0)
66 #define STKCMPCLR (1UL << 1) /* SWD-only */
67 #define STKERRCLR (1UL << 2) /* SWD-only */
68 #define WDERRCLR (1UL << 3) /* SWD-only */
69 #define ORUNERRCLR (1UL << 4) /* SWD-only */
71 /* Fields of the DP's CTRL/STAT register */
72 #define CORUNDETECT (1UL << 0)
73 #define SSTICKYORUN (1UL << 1)
74 /* 3:2 - transaction mode (e.g. pushed compare) */
75 #define SSTICKYCMP (1UL << 4)
76 #define SSTICKYERR (1UL << 5)
77 #define READOK (1UL << 6) /* SWD-only */
78 #define WDATAERR (1UL << 7) /* SWD-only */
79 /* 11:8 - mask lanes for pushed compare or verify ops */
80 /* 21:12 - transaction counter */
81 #define CDBGRSTREQ (1UL << 26)
82 #define CDBGRSTACK (1UL << 27)
83 #define CDBGPWRUPREQ (1UL << 28)
84 #define CDBGPWRUPACK (1UL << 29)
85 #define CSYSPWRUPREQ (1UL << 30)
86 #define CSYSPWRUPACK (1UL << 31)
88 /* MEM-AP register addresses */
89 #define MEM_AP_REG_CSW 0x00
90 #define MEM_AP_REG_TAR 0x04
91 #define MEM_AP_REG_TAR64 0x08 /* RW: Large Physical Address Extension */
92 #define MEM_AP_REG_DRW 0x0C /* RW: Data Read/Write register */
93 #define MEM_AP_REG_BD0 0x10 /* RW: Banked Data register 0-3 */
94 #define MEM_AP_REG_BD1 0x14
95 #define MEM_AP_REG_BD2 0x18
96 #define MEM_AP_REG_BD3 0x1C
97 #define MEM_AP_REG_MBT 0x20 /* --: Memory Barrier Transfer register */
98 #define MEM_AP_REG_BASE64 0xF0 /* RO: Debug Base Address (LA) register */
99 #define MEM_AP_REG_CFG 0xF4 /* RO: Configuration register */
100 #define MEM_AP_REG_BASE 0xF8 /* RO: Debug Base Address register */
101 /* Generic AP register address */
102 #define AP_REG_IDR 0xFC /* RO: Identification Register */
104 /* Fields of the MEM-AP's CSW register */
105 #define CSW_SIZE_MASK 7
109 #define CSW_ADDRINC_MASK (3UL << 4)
110 #define CSW_ADDRINC_OFF 0UL
111 #define CSW_ADDRINC_SINGLE (1UL << 4)
112 #define CSW_ADDRINC_PACKED (2UL << 4)
113 #define CSW_DEVICE_EN (1UL << 6)
114 #define CSW_TRIN_PROG (1UL << 7)
115 #define CSW_SPIDEN (1UL << 23)
116 /* 30:24 - implementation-defined! */
117 #define CSW_HPROT (1UL << 25) /* ? */
118 #define CSW_MASTER_DEBUG (1UL << 29) /* ? */
119 #define CSW_SPROT (1UL << 30)
120 #define CSW_DBGSWENABLE (1UL << 31)
122 /* Fields of the MEM-AP's IDR register */
123 #define IDR_REV (0xFUL << 28)
124 #define IDR_JEP106 (0x7FFUL << 17)
125 #define IDR_CLASS (0xFUL << 13)
126 #define IDR_VARIANT (0xFUL << 4)
127 #define IDR_TYPE (0xFUL << 0)
129 #define IDR_JEP106_ARM 0x04760000
131 #define DP_SELECT_APSEL 0xFF000000
132 #define DP_SELECT_APBANK 0x000000F0
133 #define DP_SELECT_DPBANK 0x0000000F
134 #define DP_SELECT_INVALID 0x00FFFF00 /* Reserved bits one */
137 * This represents an ARM Debug Interface (v5) Access Port (AP).
138 * Most common is a MEM-AP, for memory access.
142 * DAP this AP belongs to.
144 struct adiv5_dap *dap;
152 * Default value for (MEM-AP) AP_REG_CSW register.
154 uint32_t csw_default;
157 * Cache for (MEM-AP) AP_REG_CSW register value. This is written to
158 * configure an access mode, such as autoincrementing AP_REG_TAR during
159 * word access. "-1" indicates no cached value.
164 * Cache for (MEM-AP) AP_REG_TAR register value This is written to
165 * configure the address being read or written
166 * "-1" indicates no cached value.
171 * Configures how many extra tck clocks are added after starting a
172 * MEM-AP access before we try to read its status (and/or result).
174 uint32_t memaccess_tck;
176 /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
177 uint32_t tar_autoincr_block;
179 /* true if packed transfers are supported by the MEM-AP */
180 bool packed_transfers;
182 /* true if unaligned memory access is not supported by the MEM-AP */
183 bool unaligned_access_bad;
185 /* true if tar_value is in sync with TAR register */
191 * This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
192 * A DAP has two types of component: one Debug Port (DP), which is a
193 * transport agent; and at least one Access Port (AP), controlling
196 * There are two basic DP transports: JTAG, and ARM's low pin-count SWD.
197 * Accordingly, this interface is responsible for hiding the transport
198 * differences so upper layer code can largely ignore them.
200 * When the chip is implemented with JTAG-DP or SW-DP, the transport is
201 * fixed as JTAG or SWD, respectively. Chips incorporating SWJ-DP permit
202 * a choice made at board design time (by only using the SWD pins), or
203 * as part of setting up a debug session (if all the dual-role JTAG/SWD
204 * signals are available).
207 const struct dap_ops *ops;
209 /* dap transaction list for WAIT support */
210 struct list_head cmd_journal;
212 struct jtag_tap *tap;
214 uint32_t dp_ctrl_stat;
216 struct adiv5_ap ap[256];
218 /* The current manually selected AP by the "dap apsel" command */
222 * Cache for DP_SELECT register. A value of DP_SELECT_INVALID
223 * indicates no cached value and forces rewrite of the register.
227 /* information about current pending SWjDP-AHBAP transaction */
231 * Holds the pointer to the destination word for the last queued read,
232 * for use with posted AP read sequence optimization.
236 /* The TI TMS470 and TMS570 series processors use a BE-32 memory ordering
237 * despite lack of support in the ARMv7 architecture. Memory access through
238 * the AHB-AP has strange byte ordering these processors, and we need to
239 * swizzle appropriately. */
240 bool ti_be_32_quirks;
243 * Signals that an attempt to reestablish communication afresh
244 * should be performed before the next access.
250 * Transport-neutral representation of queued DAP transactions, supporting
251 * both JTAG and SWD transports. All submitted transactions are logically
252 * queued, until the queue is executed by run(). Some implementations might
253 * execute transactions as soon as they're submitted, but no status is made
254 * available until run().
257 /** DP register read. */
258 int (*queue_dp_read)(struct adiv5_dap *dap, unsigned reg,
260 /** DP register write. */
261 int (*queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
264 /** AP register read. */
265 int (*queue_ap_read)(struct adiv5_ap *ap, unsigned reg,
267 /** AP register write. */
268 int (*queue_ap_write)(struct adiv5_ap *ap, unsigned reg,
271 /** AP operation abort. */
272 int (*queue_ap_abort)(struct adiv5_dap *dap, uint8_t *ack);
274 /** Executes all queued DAP operations. */
275 int (*run)(struct adiv5_dap *dap);
277 /** Executes all queued DAP operations but doesn't check
278 * sticky error conditions */
279 int (*sync)(struct adiv5_dap *dap);
283 * Access Port classes
286 AP_CLASS_NONE = 0x00000, /* No class defined */
287 AP_CLASS_MEM_AP = 0x10000, /* MEM-AP */
294 AP_TYPE_JTAG_AP = 0x0, /* JTAG-AP - JTAG master for controlling other JTAG devices */
295 AP_TYPE_AHB_AP = 0x1, /* AHB Memory-AP */
296 AP_TYPE_APB_AP = 0x2, /* APB Memory-AP */
297 AP_TYPE_AXI_AP = 0x4, /* AXI Memory-AP */
301 * Queue a DP register read.
302 * Note that not all DP registers are readable; also, that JTAG and SWD
303 * have slight differences in DP register support.
305 * @param dap The DAP used for reading.
306 * @param reg The two-bit number of the DP register being read.
307 * @param data Pointer saying where to store the register's value
308 * (in host endianness).
310 * @return ERROR_OK for success, else a fault code.
312 static inline int dap_queue_dp_read(struct adiv5_dap *dap,
313 unsigned reg, uint32_t *data)
315 assert(dap->ops != NULL);
316 return dap->ops->queue_dp_read(dap, reg, data);
320 * Queue a DP register write.
321 * Note that not all DP registers are writable; also, that JTAG and SWD
322 * have slight differences in DP register support.
324 * @param dap The DAP used for writing.
325 * @param reg The two-bit number of the DP register being written.
326 * @param data Value being written (host endianness)
328 * @return ERROR_OK for success, else a fault code.
330 static inline int dap_queue_dp_write(struct adiv5_dap *dap,
331 unsigned reg, uint32_t data)
333 assert(dap->ops != NULL);
334 return dap->ops->queue_dp_write(dap, reg, data);
338 * Queue an AP register read.
340 * @param ap The AP used for reading.
341 * @param reg The number of the AP register being read.
342 * @param data Pointer saying where to store the register's value
343 * (in host endianness).
345 * @return ERROR_OK for success, else a fault code.
347 static inline int dap_queue_ap_read(struct adiv5_ap *ap,
348 unsigned reg, uint32_t *data)
350 assert(ap->dap->ops != NULL);
351 return ap->dap->ops->queue_ap_read(ap, reg, data);
355 * Queue an AP register write.
357 * @param ap The AP used for writing.
358 * @param reg The number of the AP register being written.
359 * @param data Value being written (host endianness)
361 * @return ERROR_OK for success, else a fault code.
363 static inline int dap_queue_ap_write(struct adiv5_ap *ap,
364 unsigned reg, uint32_t data)
366 assert(ap->dap->ops != NULL);
367 return ap->dap->ops->queue_ap_write(ap, reg, data);
371 * Queue an AP abort operation. The current AP transaction is aborted,
372 * including any update of the transaction counter. The AP is left in
373 * an unknown state (so it must be re-initialized). For use only after
374 * the AP has reported WAIT status for an extended period.
376 * @param dap The DAP used for writing.
377 * @param ack Pointer to where transaction status will be stored.
379 * @return ERROR_OK for success, else a fault code.
381 static inline int dap_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
383 assert(dap->ops != NULL);
384 return dap->ops->queue_ap_abort(dap, ack);
388 * Perform all queued DAP operations, and clear any errors posted in the
389 * CTRL_STAT register when they are done. Note that if more than one AP
390 * operation will be queued, one of the first operations in the queue
391 * should probably enable CORUNDETECT in the CTRL/STAT register.
393 * @param dap The DAP used.
395 * @return ERROR_OK for success, else a fault code.
397 static inline int dap_run(struct adiv5_dap *dap)
399 assert(dap->ops != NULL);
400 return dap->ops->run(dap);
403 static inline int dap_sync(struct adiv5_dap *dap)
405 assert(dap->ops != NULL);
407 return dap->ops->sync(dap);
411 static inline int dap_dp_read_atomic(struct adiv5_dap *dap, unsigned reg,
416 retval = dap_queue_dp_read(dap, reg, value);
417 if (retval != ERROR_OK)
423 static inline int dap_dp_poll_register(struct adiv5_dap *dap, unsigned reg,
424 uint32_t mask, uint32_t value, int timeout)
427 assert((value & mask) == value);
431 LOG_DEBUG("DAP: poll %x, mask 0x%08" PRIx32 ", value 0x%08" PRIx32,
434 ret = dap_dp_read_atomic(dap, reg, ®val);
438 if ((regval & mask) == value)
445 LOG_DEBUG("DAP: poll %x timeout", reg);
452 /* Queued MEM-AP memory mapped single word transfers. */
453 int mem_ap_read_u32(struct adiv5_ap *ap,
454 uint32_t address, uint32_t *value);
455 int mem_ap_write_u32(struct adiv5_ap *ap,
456 uint32_t address, uint32_t value);
458 /* Synchronous MEM-AP memory mapped single word transfers. */
459 int mem_ap_read_atomic_u32(struct adiv5_ap *ap,
460 uint32_t address, uint32_t *value);
461 int mem_ap_write_atomic_u32(struct adiv5_ap *ap,
462 uint32_t address, uint32_t value);
464 /* Synchronous MEM-AP memory mapped bus block transfers. */
465 int mem_ap_read_buf(struct adiv5_ap *ap,
466 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
467 int mem_ap_write_buf(struct adiv5_ap *ap,
468 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
470 /* Synchronous, non-incrementing buffer functions for accessing fifos. */
471 int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
472 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
473 int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
474 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
476 /* Create DAP struct */
477 struct adiv5_dap *dap_init(void);
479 /* Initialisation of the debug system, power domains and registers */
480 int dap_dp_init(struct adiv5_dap *dap);
481 int mem_ap_init(struct adiv5_ap *ap);
483 /* Invalidate cached DP select and cached TAR and CSW of all APs */
484 void dap_invalidate_cache(struct adiv5_dap *dap);
486 /* Probe the AP for ROM Table location */
487 int dap_get_debugbase(struct adiv5_ap *ap,
488 uint32_t *dbgbase, uint32_t *apid);
490 /* Probe Access Ports to find a particular type */
491 int dap_find_ap(struct adiv5_dap *dap,
492 enum ap_type type_to_find,
493 struct adiv5_ap **ap_out);
495 static inline struct adiv5_ap *dap_ap(struct adiv5_dap *dap, uint8_t ap_num)
497 return &dap->ap[ap_num];
500 /* Lookup CoreSight component */
501 int dap_lookup_cs_component(struct adiv5_ap *ap,
502 uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx);
506 /* Put debug link into SWD mode */
507 int dap_to_swd(struct target *target);
509 /* Put debug link into JTAG mode */
510 int dap_to_jtag(struct target *target);
512 extern const struct command_registration dap_command_handlers[];
514 struct adiv5_private_config {
518 extern int adiv5_jim_configure(struct target *target, Jim_GetOptInfo *goi);
520 #endif /* OPENOCD_TARGET_ARM_ADI_V5_H */