2 * Copyright (C) 2005 by Dominic Rath
5 * Copyright (C) 2006 by Magnus Lundin
8 * Copyright (C) 2008 by Spencer Oliver
11 * Copyright (C) 2009 by Øyvind Harboe
12 * oyvind.harboe@zylin.com
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program. If not, see <http://www.gnu.org/licenses/>.
28 #ifndef OPENOCD_TARGET_ARM_OPCODES_H
29 #define OPENOCD_TARGET_ARM_OPCODES_H
33 * Macros used to generate various ARM or Thumb opcodes.
36 /* ARM mode instructions */
38 /* Store multiple increment after
40 * List: for each bit in list: store register
41 * S: in priviledged mode: store user-mode registers
42 * W = 1: update the base register. W = 0: leave the base register untouched
44 #define ARMV4_5_STMIA(Rn, List, S, W) \
45 (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
47 /* Load multiple increment after
49 * List: for each bit in list: store register
50 * S: in priviledged mode: store user-mode registers
51 * W = 1: update the base register. W = 0: leave the base register untouched
53 #define ARMV4_5_LDMIA(Rn, List, S, W) \
54 (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
57 #define ARMV4_5_NOP (0xe1a08008)
59 /* Move PSR to general purpose register
60 * R = 1: SPSR R = 0: CPSR
63 #define ARMV4_5_MRS(Rn, R) (0xe10f0000 | ((R) << 22) | ((Rn) << 12))
66 * Rd: register to store
69 #define ARMV4_5_STR(Rd, Rn) (0xe5800000 | ((Rd) << 12) | ((Rn) << 16))
72 * Rd: register to load
75 #define ARMV4_5_LDR(Rd, Rn) (0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
77 /* Move general purpose register to PSR
78 * R = 1: SPSR R = 0: CPSR
80 * 1: control field 2: extension field 4: status field 8: flags field
83 #define ARMV4_5_MSR_GP(Rm, Field, R) \
84 (0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22))
85 #define ARMV4_5_MSR_IM(Im, Rotate, Field, R) \
86 (0xe320f000 | (Im) | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
88 /* Load Register Word Immediate Post-Index
89 * Rd: register to load
92 #define ARMV4_5_LDRW_IP(Rd, Rn) (0xe4900004 | ((Rd) << 12) | ((Rn) << 16))
94 /* Load Register Halfword Immediate Post-Index
95 * Rd: register to load
98 #define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16))
100 /* Load Register Byte Immediate Post-Index
101 * Rd: register to load
104 #define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
106 /* Store register Word Immediate Post-Index
107 * Rd: register to store
110 #define ARMV4_5_STRW_IP(Rd, Rn) (0xe4800004 | ((Rd) << 12) | ((Rn) << 16))
112 /* Store register Halfword Immediate Post-Index
113 * Rd: register to store
116 #define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16))
118 /* Store register Byte Immediate Post-Index
119 * Rd: register to store
122 #define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | ((Rd) << 12) | ((Rn) << 16))
125 * Im: Branch target (left-shifted by 2 bits, added to PC)
126 * L: 1: branch and link 0: branch only
128 #define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24))
130 /* Branch and exchange (ARM state)
131 * Rm: register holding branch target address
133 #define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
135 /* Store data from coprocessor to consecutive memory
136 * See Armv7-A arch doc section A8.6.187
137 * P: 1=index mode (offset from Rn)
138 * U: 1=add, 0=subtract Rn address with imm
139 * D: Opcode D encoding
140 * W: write back the offset start address to the Rn register
141 * CP: Coprocessor number (4 bits)
142 * CRd: Coprocessor source register (4 bits)
143 * Rn: Base register for memory address (4 bits)
144 * imm: Immediate value (0 - 1020, must be divisible by 4)
146 #define ARMV4_5_STC(P, U, D, W, CP, CRd, Rn, imm) \
147 (0xec000000 | ((P) << 24) | ((U) << 23) | ((D) << 22) | \
148 ((W) << 21) | ((Rn) << 16) | ((CRd) << 12) | ((CP) << 8) | ((imm)>>2))
150 /* Loads data from consecutive memory to coprocessor
151 * See Armv7-A arch doc section A8.6.51
152 * P: 1=index mode (offset from Rn)
153 * U: 1=add, 0=subtract Rn address with imm
154 * D: Opcode D encoding
155 * W: write back the offset start address to the Rn register
156 * CP: Coprocessor number (4 bits)
157 * CRd: Coprocessor dest register (4 bits)
158 * Rn: Base register for memory address (4 bits)
159 * imm: Immediate value (0 - 1020, must be divisible by 4)
161 #define ARMV4_5_LDC(P, U, D, W, CP, CRd, Rn, imm) \
162 (0xec100000 | ((P) << 24) | ((U) << 23) | ((D) << 22) | \
163 ((W) << 21) | ((Rn) << 16) | ((CRd) << 12) | ((CP) << 8) | ((imm) >> 2))
165 /* Move to ARM register from coprocessor
166 * CP: Coprocessor number
167 * op1: Coprocessor opcode
168 * Rd: destination register
169 * CRn: first coprocessor operand
170 * CRm: second coprocessor operand
171 * op2: Second coprocessor opcode
173 #define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) \
174 (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) \
175 | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
177 /* Move to coprocessor from ARM register
178 * CP: Coprocessor number
179 * op1: Coprocessor opcode
180 * Rd: destination register
181 * CRn: first coprocessor operand
182 * CRm: second coprocessor operand
183 * op2: Second coprocessor opcode
185 #define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) \
186 (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) \
187 | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
189 /* Breakpoint instruction (ARMv5)
190 * Im: 16-bit immediate
192 #define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf))
195 /* Thumb mode instructions
197 * NOTE: these 16-bit opcodes fill both halves of a word with the same
198 * value. The reason for this is that when we need to execute Thumb
199 * opcodes on ARM7/ARM9 cores (to switch to ARM state on debug entry),
200 * we must shift 32 bits to the bus using scan chain 1 ... if we write
201 * both halves, we don't need to track which half matters. On ARMv6 and
202 * ARMv7 we don't execute Thumb instructions in debug mode; the ITR
203 * register does not accept Thumb (or Thumb2) opcodes.
206 /* Store register (Thumb mode)
207 * Rd: source register
210 #define ARMV4_5_T_STR(Rd, Rn) \
211 ((0x6000 | (Rd) | ((Rn) << 3)) | \
212 ((0x6000 | (Rd) | ((Rn) << 3)) << 16))
214 /* Load register (Thumb state)
215 * Rd: destination register
218 #define ARMV4_5_T_LDR(Rd, Rn) \
219 ((0x6800 | ((Rn) << 3) | (Rd)) \
220 | ((0x6800 | ((Rn) << 3) | (Rd)) << 16))
222 /* Load multiple (Thumb state)
224 * List: for each bit in list: store register
226 #define ARMV4_5_T_LDMIA(Rn, List) \
227 ((0xc800 | ((Rn) << 8) | (List)) \
228 | ((0xc800 | ((Rn) << 8) | (List)) << 16))
230 /* Load register with PC relative addressing
231 * Rd: register to load
233 #define ARMV4_5_T_LDR_PCREL(Rd) \
234 ((0x4800 | ((Rd) << 8)) \
235 | ((0x4800 | ((Rd) << 8)) << 16))
237 /* Move hi register (Thumb mode)
238 * Rd: destination register
239 * Rm: source register
241 #define ARMV4_5_T_MOV(Rd, Rm) \
242 ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | \
243 (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) \
244 | ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | \
245 (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16))
247 /* No operation (Thumb mode)
248 * NOTE: this is "MOV r8, r8" ... Thumb2 adds two
249 * architected NOPs, 16-bit and 32-bit.
251 #define ARMV4_5_T_NOP (0x46c0 | (0x46c0 << 16))
253 /* Move immediate to register (Thumb state)
254 * Rd: destination register
255 * Im: 8-bit immediate value
257 #define ARMV4_5_T_MOV_IM(Rd, Im) \
258 ((0x2000 | ((Rd) << 8) | (Im)) \
259 | ((0x2000 | ((Rd) << 8) | (Im)) << 16))
261 /* Branch and Exchange
262 * Rm: register containing branch target
264 #define ARMV4_5_T_BX(Rm) \
265 ((0x4700 | ((Rm) << 3)) \
266 | ((0x4700 | ((Rm) << 3)) << 16))
268 /* Branch (Thumb state)
271 #define ARMV4_5_T_B(Imm) \
273 | ((0xe000 | (Imm)) << 16))
275 /* Breakpoint instruction (ARMv5) (Thumb state)
276 * Im: 8-bit immediate
278 #define ARMV5_T_BKPT(Im) \
280 | ((0xbe00 | (Im)) << 16))
282 /* Move to Register from Special Register
283 * 32 bit Thumb2 instruction
284 * Rd: destination register
285 * SYSm: source special register
287 #define ARM_T2_MRS(Rd, SYSm) \
288 ((0xF3EF) | ((0x8000 | (Rd << 8) | SYSm) << 16))
290 /* Move from Register from Special Register
291 * 32 bit Thumb2 instruction
292 * Rd: source register
293 * SYSm: destination special register
295 #define ARM_T2_MSR(SYSm, Rn) \
296 ((0xF380 | (Rn << 8)) | ((0x8800 | SYSm) << 16))
298 /* Change Processor State.
299 * 16 bit Thumb2 instruction
300 * Rd: source register
301 * IF: A_FLAG and/or I_FLAG and/or F_FLAG
306 #define ARM_T2_CPSID(IF) \
307 ((0xB660 | (1 << 8) | ((IF)&0x3)) \
308 | ((0xB660 | (1 << 8) | ((IF)&0x3)) << 16))
309 #define ARM_T2_CPSIE(IF) \
310 ((0xB660 | (0 << 8) | ((IF)&0x3)) \
311 | ((0xB660 | (0 << 8) | ((IF)&0x3)) << 16))
313 #endif /* OPENOCD_TARGET_ARM_OPCODES_H */