1 /***************************************************************************
2 * Copyright (C) 2009 by Marvell Technology Group Ltd. *
3 * Written by Nicolas Pitre <nico@marvell.com> *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
23 * Hold ARM semihosting support.
25 * Semihosting enables code running on an ARM target to use the I/O
26 * facilities on the host computer. The target application must be linked
27 * against a library that forwards operation requests by using the SVC
28 * instruction trapped at the Supervisor Call vector by the debugger.
29 * Details can be found in chapter 8 of DUI0203I_rvct_developer_guide.pdf
39 #include "arm_semihosting.h"
40 #include <helper/binarybuffer.h>
41 #include <helper/log.h>
44 static int do_semihosting(struct target *target)
46 struct arm *armv4_5 = target_to_armv4_5(target);
47 uint32_t r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
48 uint32_t r1 = buf_get_u32(armv4_5->core_cache->reg_list[1].value, 0, 32);
49 uint32_t lr = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, ARMV4_5_MODE_SVC, 14).value, 0, 32);
50 uint32_t spsr = buf_get_u32(armv4_5->spsr->value, 0, 32);;
55 * TODO: lots of security issues are not considered yet, such as:
56 * - no validation on target provided file descriptors
57 * - no safety checks on opened/deleted/renamed file paths
58 * Beware the target app you use this support with.
60 * TODO: explore mapping requests to GDB's "File-I/O Remote
61 * Protocol Extension" ... when GDB is active.
64 case 0x01: /* SYS_OPEN */
65 retval = target_read_memory(target, r1, 4, 3, params);
66 if (retval != ERROR_OK)
69 uint32_t a = target_buffer_get_u32(target, params+0);
70 uint32_t m = target_buffer_get_u32(target, params+4);
71 uint32_t l = target_buffer_get_u32(target, params+8);
72 if (l <= 255 && m <= 11) {
75 retval = target_read_memory(target, a, 1, l, fn);
76 if (retval != ERROR_OK)
86 mode |= O_CREAT|O_APPEND;
88 mode |= O_CREAT|O_TRUNC;
89 if (strcmp((char *)fn, ":tt") == 0) {
95 result = open((char *)fn, mode);
96 armv4_5->semihosting_errno = errno;
99 armv4_5->semihosting_errno = EINVAL;
104 case 0x02: /* SYS_CLOSE */
105 retval = target_read_memory(target, r1, 4, 1, params);
106 if (retval != ERROR_OK)
109 int fd = target_buffer_get_u32(target, params+0);
111 armv4_5->semihosting_errno = errno;
115 case 0x03: /* SYS_WRITEC */
118 retval = target_read_memory(target, r1, 1, 1, &c);
119 if (retval != ERROR_OK)
126 case 0x04: /* SYS_WRITE0 */
129 retval = target_read_memory(target, r1, 1, 1, &c);
130 if (retval != ERROR_OK)
139 case 0x05: /* SYS_WRITE */
140 retval = target_read_memory(target, r1, 4, 3, params);
141 if (retval != ERROR_OK)
144 int fd = target_buffer_get_u32(target, params+0);
145 uint32_t a = target_buffer_get_u32(target, params+4);
146 size_t l = target_buffer_get_u32(target, params+8);
147 uint8_t *buf = malloc(l);
150 armv4_5->semihosting_errno = ENOMEM;
152 retval = target_read_buffer(target, a, l, buf);
153 if (retval != ERROR_OK) {
157 result = write(fd, buf, l);
158 armv4_5->semihosting_errno = errno;
166 case 0x06: /* SYS_READ */
167 retval = target_read_memory(target, r1, 4, 3, params);
168 if (retval != ERROR_OK)
171 int fd = target_buffer_get_u32(target, params+0);
172 uint32_t a = target_buffer_get_u32(target, params+4);
173 ssize_t l = target_buffer_get_u32(target, params+8);
174 uint8_t *buf = malloc(l);
177 armv4_5->semihosting_errno = ENOMEM;
179 result = read(fd, buf, l);
180 armv4_5->semihosting_errno = errno;
182 retval = target_write_buffer(target, a, result, buf);
183 if (retval != ERROR_OK) {
194 case 0x07: /* SYS_READC */
198 case 0x08: /* SYS_ISERROR */
199 retval = target_read_memory(target, r1, 4, 1, params);
200 if (retval != ERROR_OK)
202 result = (target_buffer_get_u32(target, params+0) != 0);
205 case 0x09: /* SYS_ISTTY */
206 retval = target_read_memory(target, r1, 4, 1, params);
207 if (retval != ERROR_OK)
209 result = isatty(target_buffer_get_u32(target, params+0));
212 case 0x0a: /* SYS_SEEK */
213 retval = target_read_memory(target, r1, 4, 2, params);
214 if (retval != ERROR_OK)
217 int fd = target_buffer_get_u32(target, params+0);
218 off_t pos = target_buffer_get_u32(target, params+4);
219 result = lseek(fd, pos, SEEK_SET);
220 armv4_5->semihosting_errno = errno;
226 case 0x0c: /* SYS_FLEN */
227 retval = target_read_memory(target, r1, 4, 1, params);
228 if (retval != ERROR_OK)
231 int fd = target_buffer_get_u32(target, params+0);
232 off_t cur = lseek(fd, 0, SEEK_CUR);
233 if (cur == (off_t)-1) {
234 armv4_5->semihosting_errno = errno;
238 result = lseek(fd, 0, SEEK_END);
239 armv4_5->semihosting_errno = errno;
240 if (lseek(fd, cur, SEEK_SET) == (off_t)-1) {
241 armv4_5->semihosting_errno = errno;
247 case 0x0e: /* SYS_REMOVE */
248 retval = target_read_memory(target, r1, 4, 2, params);
249 if (retval != ERROR_OK)
252 uint32_t a = target_buffer_get_u32(target, params+0);
253 uint32_t l = target_buffer_get_u32(target, params+4);
256 retval = target_read_memory(target, a, 1, l, fn);
257 if (retval != ERROR_OK)
260 result = remove((char *)fn);
261 armv4_5->semihosting_errno = errno;
264 armv4_5->semihosting_errno = EINVAL;
269 case 0x0f: /* SYS_RENAME */
270 retval = target_read_memory(target, r1, 4, 4, params);
271 if (retval != ERROR_OK)
274 uint32_t a1 = target_buffer_get_u32(target, params+0);
275 uint32_t l1 = target_buffer_get_u32(target, params+4);
276 uint32_t a2 = target_buffer_get_u32(target, params+8);
277 uint32_t l2 = target_buffer_get_u32(target, params+12);
278 if (l1 <= 255 && l2 <= 255) {
279 uint8_t fn1[256], fn2[256];
280 retval = target_read_memory(target, a1, 1, l1, fn1);
281 if (retval != ERROR_OK)
283 retval = target_read_memory(target, a2, 1, l2, fn2);
284 if (retval != ERROR_OK)
288 result = rename((char *)fn1, (char *)fn2);
289 armv4_5->semihosting_errno = errno;
292 armv4_5->semihosting_errno = EINVAL;
297 case 0x11: /* SYS_TIME */
301 case 0x13: /* SYS_ERRNO */
302 result = armv4_5->semihosting_errno;
305 case 0x15: /* SYS_GET_CMDLINE */
306 retval = target_read_memory(target, r1, 4, 2, params);
307 if (retval != ERROR_OK)
310 uint32_t a = target_buffer_get_u32(target, params+0);
311 uint32_t l = target_buffer_get_u32(target, params+4);
312 char *arg = "foobar";
313 uint32_t s = strlen(arg) + 1;
317 retval = target_write_buffer(target, a, s, (void*)arg);
318 if (retval != ERROR_OK)
325 case 0x16: /* SYS_HEAPINFO */
326 retval = target_read_memory(target, r1, 4, 1, params);
327 if (retval != ERROR_OK)
330 uint32_t a = target_buffer_get_u32(target, params+0);
331 /* tell the remote we have no idea */
332 memset(params, 0, 4*4);
333 retval = target_write_memory(target, a, 4, 4, params);
334 if (retval != ERROR_OK)
340 case 0x18: /* angel_SWIreason_ReportException */
342 case 0x20026: /* ADP_Stopped_ApplicationExit */
343 fprintf(stderr, "semihosting: *** application exited ***\n");
345 case 0x20000: /* ADP_Stopped_BranchThroughZero */
346 case 0x20001: /* ADP_Stopped_UndefinedInstr */
347 case 0x20002: /* ADP_Stopped_SoftwareInterrupt */
348 case 0x20003: /* ADP_Stopped_PrefetchAbort */
349 case 0x20004: /* ADP_Stopped_DataAbort */
350 case 0x20005: /* ADP_Stopped_AddressException */
351 case 0x20006: /* ADP_Stopped_IRQ */
352 case 0x20007: /* ADP_Stopped_FIQ */
353 case 0x20020: /* ADP_Stopped_BreakPoint */
354 case 0x20021: /* ADP_Stopped_WatchPoint */
355 case 0x20022: /* ADP_Stopped_StepComplete */
356 case 0x20023: /* ADP_Stopped_RunTimeErrorUnknown */
357 case 0x20024: /* ADP_Stopped_InternalError */
358 case 0x20025: /* ADP_Stopped_UserInterruption */
359 case 0x20027: /* ADP_Stopped_StackOverflow */
360 case 0x20028: /* ADP_Stopped_DivisionByZero */
361 case 0x20029: /* ADP_Stopped_OSSpecific */
363 fprintf(stderr, "semihosting: exception %#x\n",
366 return target_call_event_callbacks(target, TARGET_EVENT_HALTED);
368 case 0x0d: /* SYS_TMPNAM */
369 case 0x10: /* SYS_CLOCK */
370 case 0x12: /* SYS_SYSTEM */
371 case 0x17: /* angel_SWIreason_EnterSVC */
372 case 0x30: /* SYS_ELAPSED */
373 case 0x31: /* SYS_TICKFREQ */
375 fprintf(stderr, "semihosting: unsupported call %#x\n",
378 armv4_5->semihosting_errno = ENOTSUP;
381 /* resume execution to the original mode */
382 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, result);
383 armv4_5->core_cache->reg_list[0].dirty = 1;
384 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, lr);
385 armv4_5->core_cache->reg_list[15].dirty = 1;
386 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, spsr);
387 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
388 armv4_5->core_mode = spsr & 0x1f;
390 armv4_5->core_state = ARM_STATE_THUMB;
391 return target_resume(target, 1, 0, 0, 0);
395 * Checks for and processes an ARM semihosting request. This is meant
396 * to be called when the target is stopped due to a debug mode entry.
397 * If the value 0 is returned then there was nothing to process. A non-zero
398 * return value signifies that a request was processed and the target resumed,
399 * or an error was encountered, in which case the caller must return
402 * @param target Pointer to the ARM target to process. This target must
403 * not represent an ARMv6-M or ARMv7-M processor.
404 * @param retval Pointer to a location where the return code will be stored
405 * @return non-zero value if a request was processed or an error encountered
407 int arm_semihosting(struct target *target, int *retval)
409 struct arm *arm = target_to_armv4_5(target);
413 if (!arm->is_semihosting || arm->core_mode != ARMV4_5_MODE_SVC)
416 /* Check for PC == 8: Supervisor Call vector
417 * REVISIT: assumes low exception vectors, not hivecs...
418 * safer to test "was this entry from a vector catch".
420 r = arm->core_cache->reg_list + 15;
421 if (buf_get_u32(r->value, 0, 32) != 0x08)
424 r = arm_reg_current(arm, 14);
425 lr = buf_get_u32(r->value, 0, 32);
427 /* Core-specific code should make sure SPSR is retrieved
428 * when the above checks pass...
430 if (!arm->spsr->valid) {
431 LOG_ERROR("SPSR not valid!");
432 *retval = ERROR_FAIL;
436 spsr = buf_get_u32(arm->spsr->value, 0, 32);
438 /* check instruction that triggered this trap */
439 if (spsr & (1 << 5)) {
440 /* was in Thumb (or ThumbEE) mode */
444 *retval = target_read_memory(target, lr-2, 2, 1, insn_buf);
445 if (*retval != ERROR_OK)
447 insn = target_buffer_get_u16(target, insn_buf);
452 } else if (spsr & (1 << 24)) {
453 /* was in Jazelle mode */
456 /* was in ARM mode */
460 *retval = target_read_memory(target, lr-4, 4, 1, insn_buf);
461 if (*retval != ERROR_OK)
463 insn = target_buffer_get_u32(target, insn_buf);
466 if (insn != 0xEF123456)
470 *retval = do_semihosting(target);