1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2008 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * Copyright (C) 2018 by Liviu Ionescu *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
26 ***************************************************************************/
35 #include "breakpoints.h"
36 #include "arm_disassembler.h"
37 #include <helper/binarybuffer.h>
38 #include "algorithm.h"
40 #include "semihosting_common.h"
42 /* offsets into armv4_5 core register cache */
44 /* ARMV4_5_CPSR = 31, */
45 ARMV4_5_SPSR_FIQ = 32,
46 ARMV4_5_SPSR_IRQ = 33,
47 ARMV4_5_SPSR_SVC = 34,
48 ARMV4_5_SPSR_ABT = 35,
49 ARMV4_5_SPSR_UND = 36,
53 static const uint8_t arm_usr_indices[17] = {
54 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, ARMV4_5_CPSR,
57 static const uint8_t arm_fiq_indices[8] = {
58 16, 17, 18, 19, 20, 21, 22, ARMV4_5_SPSR_FIQ,
61 static const uint8_t arm_irq_indices[3] = {
62 23, 24, ARMV4_5_SPSR_IRQ,
65 static const uint8_t arm_svc_indices[3] = {
66 25, 26, ARMV4_5_SPSR_SVC,
69 static const uint8_t arm_abt_indices[3] = {
70 27, 28, ARMV4_5_SPSR_ABT,
73 static const uint8_t arm_und_indices[3] = {
74 29, 30, ARMV4_5_SPSR_UND,
77 static const uint8_t arm_mon_indices[3] = {
84 /* For user and system modes, these list indices for all registers.
85 * otherwise they're just indices for the shadow registers and SPSR.
87 unsigned short n_indices;
88 const uint8_t *indices;
90 /* Seven modes are standard from ARM7 on. "System" and "User" share
91 * the same registers; other modes shadow from 3 to 8 registers.
96 .n_indices = ARRAY_SIZE(arm_usr_indices),
97 .indices = arm_usr_indices,
102 .n_indices = ARRAY_SIZE(arm_fiq_indices),
103 .indices = arm_fiq_indices,
106 .name = "Supervisor",
108 .n_indices = ARRAY_SIZE(arm_svc_indices),
109 .indices = arm_svc_indices,
114 .n_indices = ARRAY_SIZE(arm_abt_indices),
115 .indices = arm_abt_indices,
120 .n_indices = ARRAY_SIZE(arm_irq_indices),
121 .indices = arm_irq_indices,
124 .name = "Undefined instruction",
126 .n_indices = ARRAY_SIZE(arm_und_indices),
127 .indices = arm_und_indices,
132 .n_indices = ARRAY_SIZE(arm_usr_indices),
133 .indices = arm_usr_indices,
135 /* TrustZone "Security Extensions" add a secure monitor mode.
136 * This is distinct from a "debug monitor" which can support
137 * non-halting debug, in conjunction with some debuggers.
140 .name = "Secure Monitor",
142 .n_indices = ARRAY_SIZE(arm_mon_indices),
143 .indices = arm_mon_indices,
146 .name = "Secure Monitor ARM1176JZF-S",
147 .psr = ARM_MODE_1176_MON,
148 .n_indices = ARRAY_SIZE(arm_mon_indices),
149 .indices = arm_mon_indices,
152 /* These special modes are currently only supported
153 * by ARMv6M and ARMv7M profiles */
156 .psr = ARM_MODE_THREAD,
159 .name = "Thread (User)",
160 .psr = ARM_MODE_USER_THREAD,
164 .psr = ARM_MODE_HANDLER,
168 /** Map PSR mode bits to the name of an ARM processor operating mode. */
169 const char *arm_mode_name(unsigned psr_mode)
171 for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
172 if (arm_mode_data[i].psr == psr_mode)
173 return arm_mode_data[i].name;
175 LOG_ERROR("unrecognized psr mode: %#02x", psr_mode);
176 return "UNRECOGNIZED";
179 /** Return true iff the parameter denotes a valid ARM processor mode. */
180 bool is_arm_mode(unsigned psr_mode)
182 for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
183 if (arm_mode_data[i].psr == psr_mode)
189 /** Map PSR mode bits to linear number indexing armv4_5_core_reg_map */
190 int arm_mode_to_number(enum arm_mode mode)
194 /* map MODE_ANY to user mode */
210 case ARM_MODE_1176_MON:
213 LOG_ERROR("invalid mode value encountered %d", mode);
218 /** Map linear number indexing armv4_5_core_reg_map to PSR mode bits. */
219 enum arm_mode armv4_5_number_to_mode(int number)
239 LOG_ERROR("mode index out of bounds %d", number);
244 static const char *arm_state_strings[] = {
245 "ARM", "Thumb", "Jazelle", "ThumbEE",
248 /* Templates for ARM core registers.
250 * NOTE: offsets in this table are coupled to the arm_mode_data
251 * table above, the armv4_5_core_reg_map array below, and also to
252 * the ARMV4_5_CPSR symbol (which should vanish after ARM11 updates).
254 static const struct {
255 /* The name is used for e.g. the "regs" command. */
258 /* The {cookie, mode} tuple uniquely identifies one register.
259 * In a given mode, cookies 0..15 map to registers R0..R15,
260 * with R13..R15 usually called SP, LR, PC.
262 * MODE_ANY is used as *input* to the mapping, and indicates
263 * various special cases (sigh) and errors.
265 * Cookie 16 is (currently) confusing, since it indicates
266 * CPSR -or- SPSR depending on whether 'mode' is MODE_ANY.
267 * (Exception modes have both CPSR and SPSR registers ...)
272 } arm_core_regs[] = {
273 /* IMPORTANT: we guarantee that the first eight cached registers
274 * correspond to r0..r7, and the fifteenth to PC, so that callers
275 * don't need to map them.
277 { .name = "r0", .cookie = 0, .mode = ARM_MODE_ANY, .gdb_index = 0, },
278 { .name = "r1", .cookie = 1, .mode = ARM_MODE_ANY, .gdb_index = 1, },
279 { .name = "r2", .cookie = 2, .mode = ARM_MODE_ANY, .gdb_index = 2, },
280 { .name = "r3", .cookie = 3, .mode = ARM_MODE_ANY, .gdb_index = 3, },
281 { .name = "r4", .cookie = 4, .mode = ARM_MODE_ANY, .gdb_index = 4, },
282 { .name = "r5", .cookie = 5, .mode = ARM_MODE_ANY, .gdb_index = 5, },
283 { .name = "r6", .cookie = 6, .mode = ARM_MODE_ANY, .gdb_index = 6, },
284 { .name = "r7", .cookie = 7, .mode = ARM_MODE_ANY, .gdb_index = 7, },
286 /* NOTE: regs 8..12 might be shadowed by FIQ ... flagging
287 * them as MODE_ANY creates special cases. (ANY means
288 * "not mapped" elsewhere; here it's "everything but FIQ".)
290 { .name = "r8", .cookie = 8, .mode = ARM_MODE_ANY, .gdb_index = 8, },
291 { .name = "r9", .cookie = 9, .mode = ARM_MODE_ANY, .gdb_index = 9, },
292 { .name = "r10", .cookie = 10, .mode = ARM_MODE_ANY, .gdb_index = 10, },
293 { .name = "r11", .cookie = 11, .mode = ARM_MODE_ANY, .gdb_index = 11, },
294 { .name = "r12", .cookie = 12, .mode = ARM_MODE_ANY, .gdb_index = 12, },
296 /* Historical GDB mapping of indices:
297 * - 13-14 are sp and lr, but banked counterparts are used
298 * - 16-24 are left for deprecated 8 FPA + 1 FPS
302 /* NOTE all MODE_USR registers are equivalent to MODE_SYS ones */
303 { .name = "sp_usr", .cookie = 13, .mode = ARM_MODE_USR, .gdb_index = 26, },
304 { .name = "lr_usr", .cookie = 14, .mode = ARM_MODE_USR, .gdb_index = 27, },
306 /* guaranteed to be at index 15 */
307 { .name = "pc", .cookie = 15, .mode = ARM_MODE_ANY, .gdb_index = 15, },
308 { .name = "r8_fiq", .cookie = 8, .mode = ARM_MODE_FIQ, .gdb_index = 28, },
309 { .name = "r9_fiq", .cookie = 9, .mode = ARM_MODE_FIQ, .gdb_index = 29, },
310 { .name = "r10_fiq", .cookie = 10, .mode = ARM_MODE_FIQ, .gdb_index = 30, },
311 { .name = "r11_fiq", .cookie = 11, .mode = ARM_MODE_FIQ, .gdb_index = 31, },
312 { .name = "r12_fiq", .cookie = 12, .mode = ARM_MODE_FIQ, .gdb_index = 32, },
314 { .name = "sp_fiq", .cookie = 13, .mode = ARM_MODE_FIQ, .gdb_index = 33, },
315 { .name = "lr_fiq", .cookie = 14, .mode = ARM_MODE_FIQ, .gdb_index = 34, },
317 { .name = "sp_irq", .cookie = 13, .mode = ARM_MODE_IRQ, .gdb_index = 35, },
318 { .name = "lr_irq", .cookie = 14, .mode = ARM_MODE_IRQ, .gdb_index = 36, },
320 { .name = "sp_svc", .cookie = 13, .mode = ARM_MODE_SVC, .gdb_index = 37, },
321 { .name = "lr_svc", .cookie = 14, .mode = ARM_MODE_SVC, .gdb_index = 38, },
323 { .name = "sp_abt", .cookie = 13, .mode = ARM_MODE_ABT, .gdb_index = 39, },
324 { .name = "lr_abt", .cookie = 14, .mode = ARM_MODE_ABT, .gdb_index = 40, },
326 { .name = "sp_und", .cookie = 13, .mode = ARM_MODE_UND, .gdb_index = 41, },
327 { .name = "lr_und", .cookie = 14, .mode = ARM_MODE_UND, .gdb_index = 42, },
329 { .name = "cpsr", .cookie = 16, .mode = ARM_MODE_ANY, .gdb_index = 25, },
330 { .name = "spsr_fiq", .cookie = 16, .mode = ARM_MODE_FIQ, .gdb_index = 43, },
331 { .name = "spsr_irq", .cookie = 16, .mode = ARM_MODE_IRQ, .gdb_index = 44, },
332 { .name = "spsr_svc", .cookie = 16, .mode = ARM_MODE_SVC, .gdb_index = 45, },
333 { .name = "spsr_abt", .cookie = 16, .mode = ARM_MODE_ABT, .gdb_index = 46, },
334 { .name = "spsr_und", .cookie = 16, .mode = ARM_MODE_UND, .gdb_index = 47, },
336 /* These are only used for GDB target description, banked registers are accessed instead */
337 { .name = "sp", .cookie = 13, .mode = ARM_MODE_ANY, .gdb_index = 13, },
338 { .name = "lr", .cookie = 14, .mode = ARM_MODE_ANY, .gdb_index = 14, },
340 /* These exist only when the Security Extension (TrustZone) is present */
341 { .name = "sp_mon", .cookie = 13, .mode = ARM_MODE_MON, .gdb_index = 48, },
342 { .name = "lr_mon", .cookie = 14, .mode = ARM_MODE_MON, .gdb_index = 49, },
343 { .name = "spsr_mon", .cookie = 16, .mode = ARM_MODE_MON, .gdb_index = 50, },
347 static const struct {
355 } arm_vfp_v3_regs[] = {
356 { ARM_VFP_V3_D0, "d0", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
357 { ARM_VFP_V3_D1, "d1", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
358 { ARM_VFP_V3_D2, "d2", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
359 { ARM_VFP_V3_D3, "d3", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
360 { ARM_VFP_V3_D4, "d4", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
361 { ARM_VFP_V3_D5, "d5", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
362 { ARM_VFP_V3_D6, "d6", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
363 { ARM_VFP_V3_D7, "d7", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
364 { ARM_VFP_V3_D8, "d8", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
365 { ARM_VFP_V3_D9, "d9", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
366 { ARM_VFP_V3_D10, "d10", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
367 { ARM_VFP_V3_D11, "d11", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
368 { ARM_VFP_V3_D12, "d12", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
369 { ARM_VFP_V3_D13, "d13", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
370 { ARM_VFP_V3_D14, "d14", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
371 { ARM_VFP_V3_D15, "d15", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
372 { ARM_VFP_V3_D16, "d16", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
373 { ARM_VFP_V3_D17, "d17", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
374 { ARM_VFP_V3_D18, "d18", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
375 { ARM_VFP_V3_D19, "d19", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
376 { ARM_VFP_V3_D20, "d20", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
377 { ARM_VFP_V3_D21, "d21", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
378 { ARM_VFP_V3_D22, "d22", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
379 { ARM_VFP_V3_D23, "d23", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
380 { ARM_VFP_V3_D24, "d24", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
381 { ARM_VFP_V3_D25, "d25", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
382 { ARM_VFP_V3_D26, "d26", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
383 { ARM_VFP_V3_D27, "d27", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
384 { ARM_VFP_V3_D28, "d28", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
385 { ARM_VFP_V3_D29, "d29", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
386 { ARM_VFP_V3_D30, "d30", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
387 { ARM_VFP_V3_D31, "d31", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
388 { ARM_VFP_V3_FPSCR, "fpscr", 32, ARM_MODE_ANY, REG_TYPE_INT, "float", "org.gnu.gdb.arm.vfp"},
391 /* map core mode (USR, FIQ, ...) and register number to
392 * indices into the register cache
394 const int armv4_5_core_reg_map[8][17] = {
396 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
398 { /* FIQ (8 shadows of USR, vs normal 3) */
399 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 15, 32
402 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 23, 24, 15, 33
405 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 25, 26, 15, 34
408 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 28, 15, 35
411 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 29, 30, 15, 36
413 { /* SYS (same registers as USR) */
414 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
417 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 37, 38, 15, 39,
422 * Configures host-side ARM records to reflect the specified CPSR.
423 * Later, code can use arm_reg_current() to map register numbers
424 * according to how they are exposed by this mode.
426 void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
428 enum arm_mode mode = cpsr & 0x1f;
431 /* NOTE: this may be called very early, before the register
432 * cache is set up. We can't defend against many errors, in
433 * particular against CPSRs that aren't valid *here* ...
436 buf_set_u32(arm->cpsr->value, 0, 32, cpsr);
437 arm->cpsr->valid = 1;
438 arm->cpsr->dirty = 0;
441 arm->core_mode = mode;
443 /* mode_to_number() warned; set up a somewhat-sane mapping */
444 num = arm_mode_to_number(mode);
450 arm->map = &armv4_5_core_reg_map[num][0];
451 arm->spsr = (mode == ARM_MODE_USR || mode == ARM_MODE_SYS)
453 : arm->core_cache->reg_list + arm->map[16];
455 /* Older ARMs won't have the J bit */
456 enum arm_state state;
458 if (cpsr & (1 << 5)) { /* T */
459 if (cpsr & (1 << 24)) { /* J */
460 LOG_WARNING("ThumbEE -- incomplete support");
461 state = ARM_STATE_THUMB_EE;
463 state = ARM_STATE_THUMB;
465 if (cpsr & (1 << 24)) { /* J */
466 LOG_ERROR("Jazelle state handling is BROKEN!");
467 state = ARM_STATE_JAZELLE;
469 state = ARM_STATE_ARM;
471 arm->core_state = state;
473 LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr,
475 arm_state_strings[arm->core_state]);
479 * Returns handle to the register currently mapped to a given number.
480 * Someone must have called arm_set_cpsr() before.
482 * \param arm This core's state and registers are used.
483 * \param regnum From 0..15 corresponding to R0..R14 and PC.
484 * Note that R0..R7 don't require mapping; you may access those
485 * as the first eight entries in the register cache. Likewise
486 * R15 (PC) doesn't need mapping; you may also access it directly.
487 * However, R8..R14, and SPSR (arm->spsr) *must* be mapped.
488 * CPSR (arm->cpsr) is also not mapped.
490 struct reg *arm_reg_current(struct arm *arm, unsigned regnum)
498 LOG_ERROR("Register map is not available yet, the target is not fully initialised");
499 r = arm->core_cache->reg_list + regnum;
501 r = arm->core_cache->reg_list + arm->map[regnum];
503 /* e.g. invalid CPSR said "secure monitor" mode on a core
504 * that doesn't support it...
507 LOG_ERROR("Invalid CPSR mode");
508 r = arm->core_cache->reg_list + regnum;
514 static const uint8_t arm_gdb_dummy_fp_value[12];
516 static struct reg_feature arm_gdb_dummy_fp_features = {
517 .name = "net.sourceforge.openocd.fake_fpa"
521 * Dummy FPA registers are required to support GDB on ARM.
522 * Register packets require eight obsolete FPA register values.
523 * Modern ARM cores use Vector Floating Point (VFP), if they
524 * have any floating point support. VFP is not FPA-compatible.
526 struct reg arm_gdb_dummy_fp_reg = {
527 .name = "GDB dummy FPA register",
528 .value = (uint8_t *) arm_gdb_dummy_fp_value,
533 .feature = &arm_gdb_dummy_fp_features,
537 static const uint8_t arm_gdb_dummy_fps_value[4];
540 * Dummy FPA status registers are required to support GDB on ARM.
541 * Register packets require an obsolete FPA status register.
543 struct reg arm_gdb_dummy_fps_reg = {
544 .name = "GDB dummy FPA status register",
545 .value = (uint8_t *) arm_gdb_dummy_fps_value,
550 .feature = &arm_gdb_dummy_fp_features,
554 static void arm_gdb_dummy_init(void) __attribute__ ((constructor));
556 static void arm_gdb_dummy_init(void)
558 register_init_dummy(&arm_gdb_dummy_fp_reg);
559 register_init_dummy(&arm_gdb_dummy_fps_reg);
562 static int armv4_5_get_core_reg(struct reg *reg)
565 struct arm_reg *reg_arch_info = reg->arch_info;
566 struct target *target = reg_arch_info->target;
568 if (target->state != TARGET_HALTED) {
569 LOG_ERROR("Target not halted");
570 return ERROR_TARGET_NOT_HALTED;
573 retval = reg_arch_info->arm->read_core_reg(target, reg,
574 reg_arch_info->num, reg_arch_info->mode);
575 if (retval == ERROR_OK) {
583 static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
585 struct arm_reg *reg_arch_info = reg->arch_info;
586 struct target *target = reg_arch_info->target;
587 struct arm *armv4_5_target = target_to_arm(target);
588 uint32_t value = buf_get_u32(buf, 0, 32);
590 if (target->state != TARGET_HALTED) {
591 LOG_ERROR("Target not halted");
592 return ERROR_TARGET_NOT_HALTED;
595 /* Except for CPSR, the "reg" command exposes a writeback model
596 * for the register cache.
598 if (reg == armv4_5_target->cpsr) {
599 arm_set_cpsr(armv4_5_target, value);
601 /* Older cores need help to be in ARM mode during halt
602 * mode debug, so we clear the J and T bits if we flush.
603 * For newer cores (v6/v7a/v7r) we don't need that, but
604 * it won't hurt since CPSR is always flushed anyway.
606 if (armv4_5_target->core_mode !=
607 (enum arm_mode)(value & 0x1f)) {
608 LOG_DEBUG("changing ARM core mode to '%s'",
609 arm_mode_name(value & 0x1f));
610 value &= ~((1 << 24) | (1 << 5));
612 buf_set_u32(t, 0, 32, value);
613 armv4_5_target->write_core_reg(target, reg,
614 16, ARM_MODE_ANY, t);
617 buf_set_u32(reg->value, 0, 32, value);
618 if (reg->size == 64) {
619 value = buf_get_u32(buf + 4, 0, 32);
620 buf_set_u32(reg->value + 4, 0, 32, value);
629 static const struct reg_arch_type arm_reg_type = {
630 .get = armv4_5_get_core_reg,
631 .set = armv4_5_set_core_reg,
634 struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm)
636 int num_regs = ARRAY_SIZE(arm_core_regs);
637 int num_core_regs = num_regs;
638 if (arm->arm_vfp_version == ARM_VFP_V3)
639 num_regs += ARRAY_SIZE(arm_vfp_v3_regs);
641 struct reg_cache *cache = malloc(sizeof(struct reg_cache));
642 struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
643 struct arm_reg *reg_arch_info = calloc(num_regs, sizeof(struct arm_reg));
646 if (!cache || !reg_list || !reg_arch_info) {
653 cache->name = "ARM registers";
655 cache->reg_list = reg_list;
658 for (i = 0; i < num_core_regs; i++) {
659 /* Skip registers this core doesn't expose */
660 if (arm_core_regs[i].mode == ARM_MODE_MON
661 && arm->core_type != ARM_MODE_MON)
664 /* REVISIT handle Cortex-M, which only shadows R13/SP */
666 reg_arch_info[i].num = arm_core_regs[i].cookie;
667 reg_arch_info[i].mode = arm_core_regs[i].mode;
668 reg_arch_info[i].target = target;
669 reg_arch_info[i].arm = arm;
671 reg_list[i].name = arm_core_regs[i].name;
672 reg_list[i].number = arm_core_regs[i].gdb_index;
673 reg_list[i].size = 32;
674 reg_list[i].value = reg_arch_info[i].value;
675 reg_list[i].type = &arm_reg_type;
676 reg_list[i].arch_info = ®_arch_info[i];
677 reg_list[i].exist = true;
679 /* This really depends on the calling convention in use */
680 reg_list[i].caller_save = false;
682 /* Registers data type, as used by GDB target description */
683 reg_list[i].reg_data_type = malloc(sizeof(struct reg_data_type));
684 switch (arm_core_regs[i].cookie) {
686 reg_list[i].reg_data_type->type = REG_TYPE_DATA_PTR;
690 reg_list[i].reg_data_type->type = REG_TYPE_CODE_PTR;
693 reg_list[i].reg_data_type->type = REG_TYPE_UINT32;
697 /* let GDB shows banked registers only in "info all-reg" */
698 reg_list[i].feature = malloc(sizeof(struct reg_feature));
699 if (reg_list[i].number <= 15 || reg_list[i].number == 25) {
700 reg_list[i].feature->name = "org.gnu.gdb.arm.core";
701 reg_list[i].group = "general";
703 reg_list[i].feature->name = "net.sourceforge.openocd.banked";
704 reg_list[i].group = "banked";
711 for (i = num_core_regs, j = 0; i < num_regs; i++, j++) {
712 reg_arch_info[i].num = arm_vfp_v3_regs[j].id;
713 reg_arch_info[i].mode = arm_vfp_v3_regs[j].mode;
714 reg_arch_info[i].target = target;
715 reg_arch_info[i].arm = arm;
717 reg_list[i].name = arm_vfp_v3_regs[j].name;
718 reg_list[i].number = arm_vfp_v3_regs[j].id;
719 reg_list[i].size = arm_vfp_v3_regs[j].bits;
720 reg_list[i].value = reg_arch_info[i].value;
721 reg_list[i].type = &arm_reg_type;
722 reg_list[i].arch_info = ®_arch_info[i];
723 reg_list[i].exist = true;
725 reg_list[i].caller_save = false;
727 reg_list[i].reg_data_type = malloc(sizeof(struct reg_data_type));
728 reg_list[i].reg_data_type->type = arm_vfp_v3_regs[j].type;
730 reg_list[i].feature = malloc(sizeof(struct reg_feature));
731 reg_list[i].feature->name = arm_vfp_v3_regs[j].feature;
733 reg_list[i].group = arm_vfp_v3_regs[j].group;
738 arm->pc = reg_list + 15;
739 arm->cpsr = reg_list + ARMV4_5_CPSR;
740 arm->core_cache = cache;
745 int arm_arch_state(struct target *target)
747 struct arm *arm = target_to_arm(target);
749 if (arm->common_magic != ARM_COMMON_MAGIC) {
750 LOG_ERROR("BUG: called for a non-ARM target");
754 /* avoid filling log waiting for fileio reply */
755 if (target->semihosting->hit_fileio)
758 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
759 "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s%s",
760 arm_state_strings[arm->core_state],
761 debug_reason_name(target),
762 arm_mode_name(arm->core_mode),
763 buf_get_u32(arm->cpsr->value, 0, 32),
764 buf_get_u32(arm->pc->value, 0, 32),
765 target->semihosting->is_active ? ", semihosting" : "",
766 target->semihosting->is_fileio ? " fileio" : "");
771 #define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \
772 (cache->reg_list[armv4_5_core_reg_map[mode][num]])
774 COMMAND_HANDLER(handle_armv4_5_reg_command)
776 struct target *target = get_current_target(CMD_CTX);
777 struct arm *arm = target_to_arm(target);
781 command_print(CMD_CTX, "current target isn't an ARM");
785 if (target->state != TARGET_HALTED) {
786 command_print(CMD_CTX, "error: target must be halted for register accesses");
790 if (arm->core_type != ARM_MODE_ANY) {
791 command_print(CMD_CTX,
792 "Microcontroller Profile not supported - use standard reg cmd");
796 if (!is_arm_mode(arm->core_mode)) {
797 LOG_ERROR("not a valid arm core mode - communication failure?");
801 if (!arm->full_context) {
802 command_print(CMD_CTX, "error: target doesn't support %s",
807 regs = arm->core_cache->reg_list;
809 for (unsigned mode = 0; mode < ARRAY_SIZE(arm_mode_data); mode++) {
814 /* label this bank of registers (or shadows) */
815 switch (arm_mode_data[mode].psr) {
819 name = "System and User";
823 if (arm->core_type != ARM_MODE_MON)
827 name = arm_mode_data[mode].name;
831 command_print(CMD_CTX, "%s%s mode %sregisters",
834 /* display N rows of up to 4 registers each */
835 for (unsigned i = 0; i < arm_mode_data[mode].n_indices; ) {
839 for (unsigned j = 0; j < 4; j++, i++) {
841 struct reg *reg = regs;
843 if (i >= arm_mode_data[mode].n_indices)
846 reg += arm_mode_data[mode].indices[i];
848 /* REVISIT be smarter about faults... */
850 arm->full_context(target);
852 value = buf_get_u32(reg->value, 0, 32);
853 output_len += snprintf(output + output_len,
854 sizeof(output) - output_len,
855 "%8s: %8.8" PRIx32 " ",
858 command_print(CMD_CTX, "%s", output);
865 COMMAND_HANDLER(handle_armv4_5_core_state_command)
867 struct target *target = get_current_target(CMD_CTX);
868 struct arm *arm = target_to_arm(target);
871 command_print(CMD_CTX, "current target isn't an ARM");
875 if (arm->core_type == ARM_MODE_THREAD) {
876 /* armv7m not supported */
877 command_print(CMD_CTX, "Unsupported Command");
882 if (strcmp(CMD_ARGV[0], "arm") == 0)
883 arm->core_state = ARM_STATE_ARM;
884 if (strcmp(CMD_ARGV[0], "thumb") == 0)
885 arm->core_state = ARM_STATE_THUMB;
888 command_print(CMD_CTX, "core state: %s", arm_state_strings[arm->core_state]);
893 COMMAND_HANDLER(handle_arm_disassemble_command)
895 int retval = ERROR_OK;
896 struct target *target = get_current_target(CMD_CTX);
898 if (target == NULL) {
899 LOG_ERROR("No target selected");
903 struct arm *arm = target_to_arm(target);
904 target_addr_t address;
909 command_print(CMD_CTX, "current target isn't an ARM");
913 if (arm->core_type == ARM_MODE_THREAD) {
914 /* armv7m is always thumb mode */
920 if (strcmp(CMD_ARGV[2], "thumb") != 0)
925 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], count);
928 COMMAND_PARSE_ADDRESS(CMD_ARGV[0], address);
929 if (address & 0x01) {
931 command_print(CMD_CTX, "Disassemble as Thumb");
940 retval = ERROR_COMMAND_SYNTAX_ERROR;
943 while (count-- > 0) {
944 struct arm_instruction cur_instruction;
947 /* Always use Thumb2 disassembly for best handling
948 * of 32-bit BL/BLX, and to work with newer cores
949 * (some ARMv6, all ARMv7) that use Thumb2.
951 retval = thumb2_opcode(target, address,
953 if (retval != ERROR_OK)
958 retval = target_read_u32(target, address, &opcode);
959 if (retval != ERROR_OK)
961 retval = arm_evaluate_opcode(opcode, address,
962 &cur_instruction) != ERROR_OK;
963 if (retval != ERROR_OK)
966 command_print(CMD_CTX, "%s", cur_instruction.text);
967 address += cur_instruction.instruction_size;
973 static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
975 struct command_context *context;
976 struct target *target;
980 context = current_command_context(interp);
981 assert(context != NULL);
983 target = get_current_target(context);
984 if (target == NULL) {
985 LOG_ERROR("%s: no current target", __func__);
988 if (!target_was_examined(target)) {
989 LOG_ERROR("%s: not yet examined", target_name(target));
992 arm = target_to_arm(target);
994 LOG_ERROR("%s: not an ARM", target_name(target));
998 if ((argc < 6) || (argc > 7)) {
999 /* FIXME use the command name to verify # params... */
1000 LOG_ERROR("%s: wrong number of arguments", __func__);
1012 /* NOTE: parameter sequence matches ARM instruction set usage:
1013 * MCR pNUM, op1, rX, CRn, CRm, op2 ; write CP from rX
1014 * MRC pNUM, op1, rX, CRn, CRm, op2 ; read CP into rX
1015 * The "rX" is necessarily omitted; it uses Tcl mechanisms.
1017 retval = Jim_GetLong(interp, argv[1], &l);
1018 if (retval != JIM_OK)
1021 LOG_ERROR("%s: %s %d out of range", __func__,
1022 "coprocessor", (int) l);
1027 retval = Jim_GetLong(interp, argv[2], &l);
1028 if (retval != JIM_OK)
1031 LOG_ERROR("%s: %s %d out of range", __func__,
1037 retval = Jim_GetLong(interp, argv[3], &l);
1038 if (retval != JIM_OK)
1041 LOG_ERROR("%s: %s %d out of range", __func__,
1047 retval = Jim_GetLong(interp, argv[4], &l);
1048 if (retval != JIM_OK)
1051 LOG_ERROR("%s: %s %d out of range", __func__,
1057 retval = Jim_GetLong(interp, argv[5], &l);
1058 if (retval != JIM_OK)
1061 LOG_ERROR("%s: %s %d out of range", __func__,
1069 /* FIXME don't assume "mrc" vs "mcr" from the number of params;
1070 * that could easily be a typo! Check both...
1072 * FIXME change the call syntax here ... simplest to just pass
1073 * the MRC() or MCR() instruction to be executed. That will also
1074 * let us support the "mrc2" and "mcr2" opcodes (toggling one bit)
1075 * if that's ever needed.
1078 retval = Jim_GetLong(interp, argv[6], &l);
1079 if (retval != JIM_OK)
1083 /* NOTE: parameters reordered! */
1084 /* ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2) */
1085 retval = arm->mcr(target, cpnum, op1, op2, CRn, CRm, value);
1086 if (retval != ERROR_OK)
1089 /* NOTE: parameters reordered! */
1090 /* ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2) */
1091 retval = arm->mrc(target, cpnum, op1, op2, CRn, CRm, &value);
1092 if (retval != ERROR_OK)
1095 Jim_SetResult(interp, Jim_NewIntObj(interp, value));
1101 extern __COMMAND_HANDLER(handle_common_semihosting_command);
1102 extern __COMMAND_HANDLER(handle_common_semihosting_fileio_command);
1103 extern __COMMAND_HANDLER(handle_common_semihosting_resumable_exit_command);
1104 extern __COMMAND_HANDLER(handle_common_semihosting_cmdline);
1106 static const struct command_registration arm_exec_command_handlers[] = {
1109 .handler = handle_armv4_5_reg_command,
1110 .mode = COMMAND_EXEC,
1111 .help = "display ARM core registers",
1115 .name = "core_state",
1116 .handler = handle_armv4_5_core_state_command,
1117 .mode = COMMAND_EXEC,
1118 .usage = "['arm'|'thumb']",
1119 .help = "display/change ARM core state",
1122 .name = "disassemble",
1123 .handler = handle_arm_disassemble_command,
1124 .mode = COMMAND_EXEC,
1125 .usage = "address [count ['thumb']]",
1126 .help = "disassemble instructions ",
1130 .mode = COMMAND_EXEC,
1131 .jim_handler = &jim_mcrmrc,
1132 .help = "write coprocessor register",
1133 .usage = "cpnum op1 CRn CRm op2 value",
1137 .jim_handler = &jim_mcrmrc,
1138 .help = "read coprocessor register",
1139 .usage = "cpnum op1 CRn CRm op2",
1143 .handler = handle_common_semihosting_command,
1144 .mode = COMMAND_EXEC,
1145 .usage = "['enable'|'disable']",
1146 .help = "activate support for semihosting operations",
1149 "semihosting_cmdline",
1150 .handler = handle_common_semihosting_cmdline,
1151 .mode = COMMAND_EXEC,
1152 .usage = "arguments",
1153 .help = "command line arguments to be passed to program",
1156 "semihosting_fileio",
1157 .handler = handle_common_semihosting_fileio_command,
1158 .mode = COMMAND_EXEC,
1159 .usage = "['enable'|'disable']",
1160 .help = "activate support for semihosting fileio operations",
1163 "semihosting_resexit",
1164 .handler = handle_common_semihosting_resumable_exit_command,
1165 .mode = COMMAND_EXEC,
1166 .usage = "['enable'|'disable']",
1167 .help = "activate support for semihosting resumable exit",
1169 COMMAND_REGISTRATION_DONE
1171 const struct command_registration arm_command_handlers[] = {
1174 .mode = COMMAND_ANY,
1175 .help = "ARM command group",
1177 .chain = arm_exec_command_handlers,
1179 COMMAND_REGISTRATION_DONE
1182 int arm_get_gdb_reg_list(struct target *target,
1183 struct reg **reg_list[], int *reg_list_size,
1184 enum target_register_class reg_class)
1186 struct arm *arm = target_to_arm(target);
1189 if (!is_arm_mode(arm->core_mode)) {
1190 LOG_ERROR("not a valid arm core mode - communication failure?");
1194 switch (reg_class) {
1195 case REG_CLASS_GENERAL:
1196 *reg_list_size = 26;
1197 *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
1199 for (i = 0; i < 16; i++)
1200 (*reg_list)[i] = arm_reg_current(arm, i);
1202 /* For GDB compatibility, take FPA registers size into account and zero-fill it*/
1203 for (i = 16; i < 24; i++)
1204 (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
1205 (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
1207 (*reg_list)[25] = arm->cpsr;
1213 *reg_list_size = (arm->core_type != ARM_MODE_MON ? 48 : 51);
1214 unsigned int list_size_core = *reg_list_size;
1215 if (arm->arm_vfp_version == ARM_VFP_V3)
1216 *reg_list_size += 33;
1218 *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
1220 for (i = 0; i < 16; i++)
1221 (*reg_list)[i] = arm_reg_current(arm, i);
1223 for (i = 13; i < ARRAY_SIZE(arm_core_regs); i++) {
1224 int reg_index = arm->core_cache->reg_list[i].number;
1225 if (!(arm_core_regs[i].mode == ARM_MODE_MON
1226 && arm->core_type != ARM_MODE_MON))
1227 (*reg_list)[reg_index] = &(arm->core_cache->reg_list[i]);
1230 /* When we supply the target description, there is no need for fake FPA */
1231 for (i = 16; i < 24; i++) {
1232 (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
1233 (*reg_list)[i]->size = 0;
1235 (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
1236 (*reg_list)[24]->size = 0;
1238 if (arm->arm_vfp_version == ARM_VFP_V3) {
1239 unsigned int num_core_regs = ARRAY_SIZE(arm_core_regs);
1240 for (i = 0; i < 33; i++)
1241 (*reg_list)[list_size_core + i] = &(arm->core_cache->reg_list[num_core_regs + i]);
1248 LOG_ERROR("not a valid register class type in query.");
1254 /* wait for execution to complete and check exit point */
1255 static int armv4_5_run_algorithm_completion(struct target *target,
1256 uint32_t exit_point,
1261 struct arm *arm = target_to_arm(target);
1263 retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
1264 if (retval != ERROR_OK)
1266 if (target->state != TARGET_HALTED) {
1267 retval = target_halt(target);
1268 if (retval != ERROR_OK)
1270 retval = target_wait_state(target, TARGET_HALTED, 500);
1271 if (retval != ERROR_OK)
1273 return ERROR_TARGET_TIMEOUT;
1276 /* fast exit: ARMv5+ code can use BKPT */
1277 if (exit_point && buf_get_u32(arm->pc->value, 0, 32) != exit_point) {
1279 "target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
1280 buf_get_u32(arm->pc->value, 0, 32));
1281 return ERROR_TARGET_TIMEOUT;
1287 int armv4_5_run_algorithm_inner(struct target *target,
1288 int num_mem_params, struct mem_param *mem_params,
1289 int num_reg_params, struct reg_param *reg_params,
1290 uint32_t entry_point, uint32_t exit_point,
1291 int timeout_ms, void *arch_info,
1292 int (*run_it)(struct target *target, uint32_t exit_point,
1293 int timeout_ms, void *arch_info))
1295 struct arm *arm = target_to_arm(target);
1296 struct arm_algorithm *arm_algorithm_info = arch_info;
1297 enum arm_state core_state = arm->core_state;
1298 uint32_t context[17];
1300 int exit_breakpoint_size = 0;
1302 int retval = ERROR_OK;
1304 LOG_DEBUG("Running algorithm");
1306 if (arm_algorithm_info->common_magic != ARM_COMMON_MAGIC) {
1307 LOG_ERROR("current target isn't an ARMV4/5 target");
1308 return ERROR_TARGET_INVALID;
1311 if (target->state != TARGET_HALTED) {
1312 LOG_WARNING("target not halted");
1313 return ERROR_TARGET_NOT_HALTED;
1316 if (!is_arm_mode(arm->core_mode)) {
1317 LOG_ERROR("not a valid arm core mode - communication failure?");
1321 /* armv5 and later can terminate with BKPT instruction; less overhead */
1322 if (!exit_point && arm->is_armv4) {
1323 LOG_ERROR("ARMv4 target needs HW breakpoint location");
1327 /* save r0..pc, cpsr-or-spsr, and then cpsr-for-sure;
1328 * they'll be restored later.
1330 for (i = 0; i <= 16; i++) {
1333 r = &ARMV4_5_CORE_REG_MODE(arm->core_cache,
1334 arm_algorithm_info->core_mode, i);
1336 arm->read_core_reg(target, r, i,
1337 arm_algorithm_info->core_mode);
1338 context[i] = buf_get_u32(r->value, 0, 32);
1340 cpsr = buf_get_u32(arm->cpsr->value, 0, 32);
1342 for (i = 0; i < num_mem_params; i++) {
1343 retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size,
1344 mem_params[i].value);
1345 if (retval != ERROR_OK)
1349 for (i = 0; i < num_reg_params; i++) {
1350 struct reg *reg = register_get_by_name(arm->core_cache, reg_params[i].reg_name, 0);
1352 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1353 return ERROR_COMMAND_SYNTAX_ERROR;
1356 if (reg->size != reg_params[i].size) {
1357 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
1358 reg_params[i].reg_name);
1359 return ERROR_COMMAND_SYNTAX_ERROR;
1362 retval = armv4_5_set_core_reg(reg, reg_params[i].value);
1363 if (retval != ERROR_OK)
1367 arm->core_state = arm_algorithm_info->core_state;
1368 if (arm->core_state == ARM_STATE_ARM)
1369 exit_breakpoint_size = 4;
1370 else if (arm->core_state == ARM_STATE_THUMB)
1371 exit_breakpoint_size = 2;
1373 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1374 return ERROR_COMMAND_SYNTAX_ERROR;
1377 if (arm_algorithm_info->core_mode != ARM_MODE_ANY) {
1378 LOG_DEBUG("setting core_mode: 0x%2.2x",
1379 arm_algorithm_info->core_mode);
1380 buf_set_u32(arm->cpsr->value, 0, 5,
1381 arm_algorithm_info->core_mode);
1382 arm->cpsr->dirty = 1;
1383 arm->cpsr->valid = 1;
1386 /* terminate using a hardware or (ARMv5+) software breakpoint */
1388 retval = breakpoint_add(target, exit_point,
1389 exit_breakpoint_size, BKPT_HARD);
1390 if (retval != ERROR_OK) {
1391 LOG_ERROR("can't add HW breakpoint to terminate algorithm");
1392 return ERROR_TARGET_FAILURE;
1396 retval = target_resume(target, 0, entry_point, 1, 1);
1397 if (retval != ERROR_OK)
1399 retval = run_it(target, exit_point, timeout_ms, arch_info);
1402 breakpoint_remove(target, exit_point);
1404 if (retval != ERROR_OK)
1407 for (i = 0; i < num_mem_params; i++) {
1408 if (mem_params[i].direction != PARAM_OUT) {
1409 int retvaltemp = target_read_buffer(target, mem_params[i].address,
1411 mem_params[i].value);
1412 if (retvaltemp != ERROR_OK)
1413 retval = retvaltemp;
1417 for (i = 0; i < num_reg_params; i++) {
1418 if (reg_params[i].direction != PARAM_OUT) {
1420 struct reg *reg = register_get_by_name(arm->core_cache,
1421 reg_params[i].reg_name,
1424 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1425 retval = ERROR_COMMAND_SYNTAX_ERROR;
1429 if (reg->size != reg_params[i].size) {
1431 "BUG: register '%s' size doesn't match reg_params[i].size",
1432 reg_params[i].reg_name);
1433 retval = ERROR_COMMAND_SYNTAX_ERROR;
1437 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1441 /* restore everything we saved before (17 or 18 registers) */
1442 for (i = 0; i <= 16; i++) {
1444 regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
1445 arm_algorithm_info->core_mode, i).value, 0, 32);
1446 if (regvalue != context[i]) {
1447 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
1448 ARMV4_5_CORE_REG_MODE(arm->core_cache,
1449 arm_algorithm_info->core_mode, i).name, context[i]);
1450 buf_set_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
1451 arm_algorithm_info->core_mode, i).value, 0, 32, context[i]);
1452 ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode,
1454 ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode,
1459 arm_set_cpsr(arm, cpsr);
1460 arm->cpsr->dirty = 1;
1462 arm->core_state = core_state;
1467 int armv4_5_run_algorithm(struct target *target,
1469 struct mem_param *mem_params,
1471 struct reg_param *reg_params,
1472 target_addr_t entry_point,
1473 target_addr_t exit_point,
1477 return armv4_5_run_algorithm_inner(target,
1482 (uint32_t)entry_point,
1483 (uint32_t)exit_point,
1486 armv4_5_run_algorithm_completion);
1490 * Runs ARM code in the target to calculate a CRC32 checksum.
1493 int arm_checksum_memory(struct target *target,
1494 target_addr_t address, uint32_t count, uint32_t *checksum)
1496 struct working_area *crc_algorithm;
1497 struct arm_algorithm arm_algo;
1498 struct arm *arm = target_to_arm(target);
1499 struct reg_param reg_params[2];
1502 uint32_t exit_var = 0;
1504 static const uint8_t arm_crc_code_le[] = {
1505 #include "../../contrib/loaders/checksum/armv4_5_crc.inc"
1508 assert(sizeof(arm_crc_code_le) % 4 == 0);
1510 retval = target_alloc_working_area(target,
1511 sizeof(arm_crc_code_le), &crc_algorithm);
1512 if (retval != ERROR_OK)
1515 /* convert code into a buffer in target endianness */
1516 for (i = 0; i < ARRAY_SIZE(arm_crc_code_le) / 4; i++) {
1517 retval = target_write_u32(target,
1518 crc_algorithm->address + i * sizeof(uint32_t),
1519 le_to_h_u32(&arm_crc_code_le[i * 4]));
1520 if (retval != ERROR_OK)
1524 arm_algo.common_magic = ARM_COMMON_MAGIC;
1525 arm_algo.core_mode = ARM_MODE_SVC;
1526 arm_algo.core_state = ARM_STATE_ARM;
1528 init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT);
1529 init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
1531 buf_set_u32(reg_params[0].value, 0, 32, address);
1532 buf_set_u32(reg_params[1].value, 0, 32, count);
1534 /* 20 second timeout/megabyte */
1535 int timeout = 20000 * (1 + (count / (1024 * 1024)));
1537 /* armv4 must exit using a hardware breakpoint */
1539 exit_var = crc_algorithm->address + sizeof(arm_crc_code_le) - 8;
1541 retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
1542 crc_algorithm->address,
1544 timeout, &arm_algo);
1546 if (retval == ERROR_OK)
1547 *checksum = buf_get_u32(reg_params[0].value, 0, 32);
1549 LOG_ERROR("error executing ARM crc algorithm");
1551 destroy_reg_param(®_params[0]);
1552 destroy_reg_param(®_params[1]);
1555 target_free_working_area(target, crc_algorithm);
1561 * Runs ARM code in the target to check whether a memory block holds
1562 * all ones. NOR flash which has been erased, and thus may be written,
1566 int arm_blank_check_memory(struct target *target,
1567 struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value)
1569 struct working_area *check_algorithm;
1570 struct reg_param reg_params[3];
1571 struct arm_algorithm arm_algo;
1572 struct arm *arm = target_to_arm(target);
1575 uint32_t exit_var = 0;
1577 static const uint8_t check_code_le[] = {
1578 #include "../../contrib/loaders/erase_check/armv4_5_erase_check.inc"
1581 assert(sizeof(check_code_le) % 4 == 0);
1583 if (erased_value != 0xff) {
1584 LOG_ERROR("Erase value 0x%02" PRIx8 " not yet supported for ARMv4/v5 targets",
1589 /* make sure we have a working area */
1590 retval = target_alloc_working_area(target,
1591 sizeof(check_code_le), &check_algorithm);
1592 if (retval != ERROR_OK)
1595 /* convert code into a buffer in target endianness */
1596 for (i = 0; i < ARRAY_SIZE(check_code_le) / 4; i++) {
1597 retval = target_write_u32(target,
1598 check_algorithm->address
1599 + i * sizeof(uint32_t),
1600 le_to_h_u32(&check_code_le[i * 4]));
1601 if (retval != ERROR_OK)
1605 arm_algo.common_magic = ARM_COMMON_MAGIC;
1606 arm_algo.core_mode = ARM_MODE_SVC;
1607 arm_algo.core_state = ARM_STATE_ARM;
1609 init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
1610 buf_set_u32(reg_params[0].value, 0, 32, blocks[0].address);
1612 init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
1613 buf_set_u32(reg_params[1].value, 0, 32, blocks[0].size);
1615 init_reg_param(®_params[2], "r2", 32, PARAM_IN_OUT);
1616 buf_set_u32(reg_params[2].value, 0, 32, erased_value);
1618 /* armv4 must exit using a hardware breakpoint */
1620 exit_var = check_algorithm->address + sizeof(check_code_le) - 4;
1622 retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
1623 check_algorithm->address,
1627 if (retval == ERROR_OK)
1628 blocks[0].result = buf_get_u32(reg_params[2].value, 0, 32);
1630 destroy_reg_param(®_params[0]);
1631 destroy_reg_param(®_params[1]);
1632 destroy_reg_param(®_params[2]);
1635 target_free_working_area(target, check_algorithm);
1637 if (retval != ERROR_OK)
1640 return 1; /* only one block has been checked */
1643 static int arm_full_context(struct target *target)
1645 struct arm *arm = target_to_arm(target);
1646 unsigned num_regs = arm->core_cache->num_regs;
1647 struct reg *reg = arm->core_cache->reg_list;
1648 int retval = ERROR_OK;
1650 for (; num_regs && retval == ERROR_OK; num_regs--, reg++) {
1653 retval = armv4_5_get_core_reg(reg);
1658 static int arm_default_mrc(struct target *target, int cpnum,
1659 uint32_t op1, uint32_t op2,
1660 uint32_t CRn, uint32_t CRm,
1663 LOG_ERROR("%s doesn't implement MRC", target_type_name(target));
1667 static int arm_default_mcr(struct target *target, int cpnum,
1668 uint32_t op1, uint32_t op2,
1669 uint32_t CRn, uint32_t CRm,
1672 LOG_ERROR("%s doesn't implement MCR", target_type_name(target));
1676 int arm_init_arch_info(struct target *target, struct arm *arm)
1678 target->arch_info = arm;
1679 arm->target = target;
1681 arm->common_magic = ARM_COMMON_MAGIC;
1683 /* core_type may be overridden by subtype logic */
1684 if (arm->core_type != ARM_MODE_THREAD) {
1685 arm->core_type = ARM_MODE_ANY;
1686 arm_set_cpsr(arm, ARM_MODE_USR);
1689 /* default full_context() has no core-specific optimizations */
1690 if (!arm->full_context && arm->read_core_reg)
1691 arm->full_context = arm_full_context;
1694 arm->mrc = arm_default_mrc;
1696 arm->mcr = arm_default_mcr;