1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009 by Øyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
31 typedef enum armv4_5_mode
33 ARMV4_5_MODE_USR = 16,
34 ARMV4_5_MODE_FIQ = 17,
35 ARMV4_5_MODE_IRQ = 18,
36 ARMV4_5_MODE_SVC = 19,
37 ARMV4_5_MODE_ABT = 23,
38 ARMV4_5_MODE_UND = 27,
39 ARMV4_5_MODE_SYS = 31,
43 int armv4_5_mode_to_number(enum armv4_5_mode mode);
44 enum armv4_5_mode armv4_5_number_to_mode(int number);
46 extern const char **armv4_5_mode_strings;
48 typedef enum armv4_5_state
52 ARMV4_5_STATE_JAZELLE,
55 extern char* armv4_5_state_strings[];
57 extern int armv4_5_core_reg_map[7][17];
59 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
60 cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
61 #define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \
62 cache->reg_list[armv4_5_core_reg_map[mode][num]]
64 /* offsets into armv4_5 core register cache */
68 ARMV4_5_SPSR_FIQ = 32,
69 ARMV4_5_SPSR_IRQ = 33,
70 ARMV4_5_SPSR_SVC = 34,
71 ARMV4_5_SPSR_ABT = 35,
75 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
77 /* NOTE: this is being morphed into a generic toplevel holder for ARMs. */
78 #define armv4_5_common_s arm
81 * Represents a generic ARM core, with standard application registers.
83 * There are sixteen application registers (including PC, SP, LR) and a PSR.
84 * Cortex-M series cores do not support as many core states or shadowed
85 * registers as traditional ARM cores, and only support Thumb2 instructions.
90 struct reg_cache *core_cache;
92 int /* armv4_5_mode */ core_mode;
93 enum armv4_5_state core_state;
95 /** Flag reporting unavailability of the BKPT instruction. */
98 /** Handle for the Embedded Trace Module, if one is present. */
99 struct etm_context *etm;
101 int (*full_context)(struct target *target);
102 int (*read_core_reg)(struct target *target,
103 int num, enum armv4_5_mode mode);
104 int (*write_core_reg)(struct target *target,
105 int num, enum armv4_5_mode mode, uint32_t value);
109 #define target_to_armv4_5 target_to_arm
111 /** Convert target handle to generic ARM target state handle. */
112 static inline struct arm *target_to_arm(struct target *target)
114 return target->arch_info;
117 static inline bool is_arm(struct arm *arm)
119 return arm && arm->common_magic == ARMV4_5_COMMON_MAGIC;
122 struct armv4_5_algorithm
126 enum armv4_5_mode core_mode;
127 enum armv4_5_state core_state;
130 struct armv4_5_core_reg
133 enum armv4_5_mode mode;
134 struct target *target;
135 struct arm *armv4_5_common;
138 struct reg_cache* armv4_5_build_reg_cache(struct target *target,
139 struct arm *armv4_5_common);
141 int armv4_5_arch_state(struct target *target);
142 int armv4_5_get_gdb_reg_list(struct target *target,
143 struct reg **reg_list[], int *reg_list_size);
145 int armv4_5_register_commands(struct command_context *cmd_ctx);
146 int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5);
148 int armv4_5_run_algorithm(struct target *target,
149 int num_mem_params, struct mem_param *mem_params,
150 int num_reg_params, struct reg_param *reg_params,
151 uint32_t entry_point, uint32_t exit_point,
152 int timeout_ms, void *arch_info);
154 int armv4_5_invalidate_core_regs(struct target *target);
156 int arm_checksum_memory(struct target *target,
157 uint32_t address, uint32_t count, uint32_t *checksum);
158 int arm_blank_check_memory(struct target *target,
159 uint32_t address, uint32_t count, uint32_t *blank);
162 /* ARM mode instructions
165 /* Store multiple increment after
167 * List: for each bit in list: store register
168 * S: in priviledged mode: store user-mode registers
169 * W = 1: update the base register. W = 0: leave the base register untouched
171 #define ARMV4_5_STMIA(Rn, List, S, W) (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
173 /* Load multiple increment after
175 * List: for each bit in list: store register
176 * S: in priviledged mode: store user-mode registers
177 * W = 1: update the base register. W = 0: leave the base register untouched
179 #define ARMV4_5_LDMIA(Rn, List, S, W) (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
182 #define ARMV4_5_NOP (0xe1a08008)
184 /* Move PSR to general purpose register
185 * R = 1: SPSR R = 0: CPSR
186 * Rn: target register
188 #define ARMV4_5_MRS(Rn, R) (0xe10f0000 | ((R) << 22) | ((Rn) << 12))
191 * Rd: register to store
194 #define ARMV4_5_STR(Rd, Rn) (0xe5800000 | ((Rd) << 12) | ((Rn) << 16))
197 * Rd: register to load
200 #define ARMV4_5_LDR(Rd, Rn) (0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
202 /* Move general purpose register to PSR
203 * R = 1: SPSR R = 0: CPSR
205 * 1: control field 2: extension field 4: status field 8: flags field
206 * Rm: source register
208 #define ARMV4_5_MSR_GP(Rm, Field, R) (0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22))
209 #define ARMV4_5_MSR_IM(Im, Rotate, Field, R) (0xe320f000 | (Im) | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
211 /* Load Register Halfword Immediate Post-Index
212 * Rd: register to load
215 #define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16))
217 /* Load Register Byte Immediate Post-Index
218 * Rd: register to load
221 #define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
223 /* Store register Halfword Immediate Post-Index
224 * Rd: register to store
227 #define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16))
229 /* Store register Byte Immediate Post-Index
230 * Rd: register to store
233 #define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | ((Rd) << 12) | ((Rn) << 16))
236 * Im: Branch target (left-shifted by 2 bits, added to PC)
237 * L: 1: branch and link 0: branch only
239 #define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24))
241 /* Branch and exchange (ARM state)
242 * Rm: register holding branch target address
244 #define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
246 /* Move to ARM register from coprocessor
247 * CP: Coprocessor number
248 * op1: Coprocessor opcode
249 * Rd: destination register
250 * CRn: first coprocessor operand
251 * CRm: second coprocessor operand
252 * op2: Second coprocessor opcode
254 #define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
256 /* Move to coprocessor from ARM register
257 * CP: Coprocessor number
258 * op1: Coprocessor opcode
259 * Rd: destination register
260 * CRn: first coprocessor operand
261 * CRm: second coprocessor operand
262 * op2: Second coprocessor opcode
264 #define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
266 /* Breakpoint instruction (ARMv5)
267 * Im: 16-bit immediate
269 #define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf))
272 /* Thumb mode instructions
275 /* Store register (Thumb mode)
276 * Rd: source register
279 #define ARMV4_5_T_STR(Rd, Rn) ((0x6000 | (Rd) | ((Rn) << 3)) | ((0x6000 | (Rd) | ((Rn) << 3)) << 16))
281 /* Load register (Thumb state)
282 * Rd: destination register
285 #define ARMV4_5_T_LDR(Rd, Rn) ((0x6800 | ((Rn) << 3) | (Rd)) | ((0x6800 | ((Rn) << 3) | (Rd)) << 16))
287 /* Load multiple (Thumb state)
289 * List: for each bit in list: store register
291 #define ARMV4_5_T_LDMIA(Rn, List) ((0xc800 | ((Rn) << 8) | (List)) | ((0xc800 | ((Rn) << 8) | List) << 16))
293 /* Load register with PC relative addressing
294 * Rd: register to load
296 #define ARMV4_5_T_LDR_PCREL(Rd) ((0x4800 | ((Rd) << 8)) | ((0x4800 | ((Rd) << 8)) << 16))
298 /* Move hi register (Thumb mode)
299 * Rd: destination register
300 * Rm: source register
302 #define ARMV4_5_T_MOV(Rd, Rm) ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) | ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16))
304 /* No operation (Thumb mode)
306 #define ARMV4_5_T_NOP (0x46c0 | (0x46c0 << 16))
308 /* Move immediate to register (Thumb state)
309 * Rd: destination register
310 * Im: 8-bit immediate value
312 #define ARMV4_5_T_MOV_IM(Rd, Im) ((0x2000 | ((Rd) << 8) | (Im)) | ((0x2000 | ((Rd) << 8) | (Im)) << 16))
314 /* Branch and Exchange
315 * Rm: register containing branch target
317 #define ARMV4_5_T_BX(Rm) ((0x4700 | ((Rm) << 3)) | ((0x4700 | ((Rm) << 3)) << 16))
319 /* Branch (Thumb state)
322 #define ARMV4_5_T_B(Imm) ((0xe000 | (Imm)) | ((0xe000 | (Imm)) << 16))
324 /* Breakpoint instruction (ARMv5) (Thumb state)
325 * Im: 8-bit immediate
327 #define ARMV5_T_BKPT(Im) ((0xbe00 | Im) | ((0xbe00 | Im) << 16))
329 /* build basic mrc/mcr opcode */
331 static inline uint32_t mrc_opcode(int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm)
341 #endif /* ARMV4_5_H */