1 /***************************************************************************
2 * Copyright (C) 2009 by David Brownell *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
18 ***************************************************************************/
23 #include "arm_adi_v5.h"
25 #include "armv4_5_mmu.h"
26 #include "armv4_5_cache.h"
34 #define ARMV7_COMMON_MAGIC 0x0A450999
36 /* VA to PA translation operations opc2 values*/
45 /* L210/L220 cache controller support */
46 struct armv7a_l2x_cache {
51 struct armv7a_cachesize {
53 /* cache dimensionning */
55 uint32_t associativity;
58 /* info for set way operation on cache */
65 struct armv7a_cache_common {
67 struct armv7a_cachesize d_u_size; /* data cache */
68 struct armv7a_cachesize i_size; /* instruction cache */
70 int d_u_cache_enabled;
71 /* l2 external unified cache if some */
73 int (*flush_all_data_cache)(struct target *target);
74 int (*display_cache_info)(struct command_context *cmd_ctx,
75 struct armv7a_cache_common *armv7a_cache);
78 struct armv7a_mmu_common {
79 /* following field mmu working way */
80 int32_t ttbr1_used; /* -1 not initialized, 0 no ttbr1 1 ttbr1 used and */
81 uint32_t ttbr0_mask;/* masked to be used */
84 int (*read_physical_memory)(struct target *target, uint32_t address, uint32_t size,
85 uint32_t count, uint8_t *buffer);
86 struct armv7a_cache_common armv7a_cache;
90 struct armv7a_common {
93 struct reg_cache *core_cache;
102 bool memory_ap_available;
104 uint8_t multi_processor_system;
108 /* cache specific to V7 Memory Management Unit compatible with v4_5*/
109 struct armv7a_mmu_common armv7a_mmu;
111 int (*examine_debug_reason)(struct target *target);
112 int (*post_debug_entry)(struct target *target);
114 void (*pre_restore_context)(struct target *target);
117 static inline struct armv7a_common *
118 target_to_armv7a(struct target *target)
120 return container_of(target->arch_info, struct armv7a_common, arm);
123 /* register offsets from armv7a.debug_base */
125 /* See ARMv7a arch spec section C10.2 */
126 #define CPUDBG_DIDR 0x000
128 /* See ARMv7a arch spec section C10.3 */
129 #define CPUDBG_WFAR 0x018
130 /* PCSR at 0x084 -or- 0x0a0 -or- both ... based on flags in DIDR */
131 #define CPUDBG_DSCR 0x088
132 #define CPUDBG_DRCR 0x090
133 #define CPUDBG_PRCR 0x310
134 #define CPUDBG_PRSR 0x314
136 /* See ARMv7a arch spec section C10.4 */
137 #define CPUDBG_DTRRX 0x080
138 #define CPUDBG_ITR 0x084
139 #define CPUDBG_DTRTX 0x08c
141 /* See ARMv7a arch spec section C10.5 */
142 #define CPUDBG_BVR_BASE 0x100
143 #define CPUDBG_BCR_BASE 0x140
144 #define CPUDBG_WVR_BASE 0x180
145 #define CPUDBG_WCR_BASE 0x1C0
146 #define CPUDBG_VCR 0x01C
148 /* See ARMv7a arch spec section C10.6 */
149 #define CPUDBG_OSLAR 0x300
150 #define CPUDBG_OSLSR 0x304
151 #define CPUDBG_OSSRR 0x308
152 #define CPUDBG_ECR 0x024
154 /* See ARMv7a arch spec section C10.7 */
155 #define CPUDBG_DSCCR 0x028
157 /* See ARMv7a arch spec section C10.8 */
158 #define CPUDBG_AUTHSTATUS 0xFB8
160 int armv7a_arch_state(struct target *target);
161 int armv7a_identify_cache(struct target *target);
162 int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a);
163 int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va,
164 uint32_t *val, int meminfo);
165 int armv7a_mmu_translate_va(struct target *target, uint32_t va, uint32_t *val);
167 int armv7a_handle_cache_info_command(struct command_context *cmd_ctx,
168 struct armv7a_cache_common *armv7a_cache);
170 extern const struct command_registration armv7a_command_handlers[];
172 #endif /* ARMV4_5_H */