1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * Copyright (C) 2007,2008 Øyvind Harboe *
12 * oyvind.harboe@zylin.com *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program; if not, write to the *
26 * Free Software Foundation, Inc., *
27 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
29 * ARMv7-M Architecture, Application Level Reference Manual *
30 * ARM DDI 0405C (September 2008) *
32 ***************************************************************************/
37 #include "breakpoints.h"
40 #include "algorithm.h"
45 #define _DEBUG_INSTRUCTION_EXECUTION_
48 /** Maps from enum armv7m_mode (except ARMV7M_MODE_ANY) to name. */
49 char *armv7m_mode_strings[] =
51 "Thread", "Thread (User)", "Handler",
54 static char *armv7m_exception_strings[] =
56 "", "Reset", "NMI", "HardFault",
57 "MemManage", "BusFault", "UsageFault", "RESERVED",
58 "RESERVED", "RESERVED", "RESERVED", "SVCall",
59 "DebugMonitor", "RESERVED", "PendSV", "SysTick"
62 /* FIXME these dummies are IDENTICAL to the armv4_5, arm11, and armv7a
63 * ones... except for naming/scoping
65 static uint8_t armv7m_gdb_dummy_fp_value[12];
67 static struct reg armv7m_gdb_dummy_fp_reg =
69 .name = "GDB dummy floating-point register",
70 .value = armv7m_gdb_dummy_fp_value,
77 static uint8_t armv7m_gdb_dummy_fps_value[4];
79 static struct reg armv7m_gdb_dummy_fps_reg =
81 .name = "GDB dummy floating-point status register",
82 .value = armv7m_gdb_dummy_fps_value,
89 #ifdef ARMV7_GDB_HACKS
90 uint8_t armv7m_gdb_dummy_cpsr_value[] = {0, 0, 0, 0};
92 struct reg armv7m_gdb_dummy_cpsr_reg =
94 .name = "GDB dummy cpsr register",
95 .value = armv7m_gdb_dummy_cpsr_value,
104 * These registers are not memory-mapped. The ARMv7-M profile includes
105 * memory mapped registers too, such as for the NVIC (interrupt controller)
106 * and SysTick (timer) modules; those can mostly be treated as peripherals.
108 * The ARMv6-M profile is almost identical in this respect, except that it
109 * doesn't include basepri or faultmask registers.
111 static const struct {
116 { ARMV7M_R0, "r0", 32 },
117 { ARMV7M_R1, "r1", 32 },
118 { ARMV7M_R2, "r2", 32 },
119 { ARMV7M_R3, "r3", 32 },
121 { ARMV7M_R4, "r4", 32 },
122 { ARMV7M_R5, "r5", 32 },
123 { ARMV7M_R6, "r6", 32 },
124 { ARMV7M_R7, "r7", 32 },
126 { ARMV7M_R8, "r8", 32 },
127 { ARMV7M_R9, "r9", 32 },
128 { ARMV7M_R10, "r10", 32 },
129 { ARMV7M_R11, "r11", 32 },
131 { ARMV7M_R12, "r12", 32 },
132 { ARMV7M_R13, "sp", 32 },
133 { ARMV7M_R14, "lr", 32 },
134 { ARMV7M_PC, "pc", 32 },
136 { ARMV7M_xPSR, "xPSR", 32 },
137 { ARMV7M_MSP, "msp", 32 },
138 { ARMV7M_PSP, "psp", 32 },
140 { ARMV7M_PRIMASK, "primask", 1 },
141 { ARMV7M_BASEPRI, "basepri", 8 },
142 { ARMV7M_FAULTMASK, "faultmask", 1 },
143 { ARMV7M_CONTROL, "control", 2 },
146 #define ARMV7M_NUM_REGS ARRAY_SIZE(armv7m_regs)
149 * Restores target context using the cache of core registers set up
150 * by armv7m_build_reg_cache(), calling optional core-specific hooks.
152 int armv7m_restore_context(struct target *target)
155 struct armv7m_common *armv7m = target_to_armv7m(target);
159 if (armv7m->pre_restore_context)
160 armv7m->pre_restore_context(target);
162 for (i = ARMV7M_NUM_REGS - 1; i >= 0; i--)
164 if (armv7m->core_cache->reg_list[i].dirty)
166 armv7m->write_core_reg(target, i);
170 if (armv7m->post_restore_context)
171 armv7m->post_restore_context(target);
176 /* Core state functions */
179 * Maps ISR number (from xPSR) to name.
180 * Note that while names and meanings for the first sixteen are standardized
181 * (with zero not a true exception), external interrupts are only numbered.
182 * They are assigned by vendors, which generally assign different numbers to
183 * peripherals (such as UART0 or a USB peripheral controller).
185 char *armv7m_exception_string(int number)
187 static char enamebuf[32];
189 if ((number < 0) | (number > 511))
190 return "Invalid exception";
192 return armv7m_exception_strings[number];
193 sprintf(enamebuf, "External Interrupt(%i)", number - 16);
197 static int armv7m_get_core_reg(struct reg *reg)
200 struct armv7m_core_reg *armv7m_reg = reg->arch_info;
201 struct target *target = armv7m_reg->target;
202 struct armv7m_common *armv7m = target_to_armv7m(target);
204 if (target->state != TARGET_HALTED)
206 return ERROR_TARGET_NOT_HALTED;
209 retval = armv7m->read_core_reg(target, armv7m_reg->num);
214 static int armv7m_set_core_reg(struct reg *reg, uint8_t *buf)
216 struct armv7m_core_reg *armv7m_reg = reg->arch_info;
217 struct target *target = armv7m_reg->target;
218 uint32_t value = buf_get_u32(buf, 0, 32);
220 if (target->state != TARGET_HALTED)
222 return ERROR_TARGET_NOT_HALTED;
225 buf_set_u32(reg->value, 0, 32, value);
232 static int armv7m_read_core_reg(struct target *target, unsigned num)
236 struct armv7m_core_reg * armv7m_core_reg;
237 struct armv7m_common *armv7m = target_to_armv7m(target);
239 if (num >= ARMV7M_NUM_REGS)
240 return ERROR_INVALID_ARGUMENTS;
242 armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
243 retval = armv7m->load_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, ®_value);
244 buf_set_u32(armv7m->core_cache->reg_list[num].value, 0, 32, reg_value);
245 armv7m->core_cache->reg_list[num].valid = 1;
246 armv7m->core_cache->reg_list[num].dirty = 0;
251 static int armv7m_write_core_reg(struct target *target, unsigned num)
255 struct armv7m_core_reg *armv7m_core_reg;
256 struct armv7m_common *armv7m = target_to_armv7m(target);
258 if (num >= ARMV7M_NUM_REGS)
259 return ERROR_INVALID_ARGUMENTS;
261 reg_value = buf_get_u32(armv7m->core_cache->reg_list[num].value, 0, 32);
262 armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
263 retval = armv7m->store_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, reg_value);
264 if (retval != ERROR_OK)
266 LOG_ERROR("JTAG failure");
267 armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
268 return ERROR_JTAG_DEVICE_ERROR;
270 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value);
271 armv7m->core_cache->reg_list[num].valid = 1;
272 armv7m->core_cache->reg_list[num].dirty = 0;
277 /** Invalidates cache of core registers set up by armv7m_build_reg_cache(). */
278 int armv7m_invalidate_core_regs(struct target *target)
280 struct armv7m_common *armv7m = target_to_armv7m(target);
283 for (i = 0; i < armv7m->core_cache->num_regs; i++)
285 armv7m->core_cache->reg_list[i].valid = 0;
286 armv7m->core_cache->reg_list[i].dirty = 0;
293 * Returns generic ARM userspace registers to GDB.
294 * GDB doesn't quite understand that most ARMs don't have floating point
295 * hardware, so this also fakes a set of long-obsolete FPA registers that
296 * are not used in EABI based software stacks.
298 int armv7m_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
300 struct armv7m_common *armv7m = target_to_armv7m(target);
304 *reg_list = malloc(sizeof(struct reg*) * (*reg_list_size));
307 * GDB register packet format for ARM:
308 * - the first 16 registers are r0..r15
309 * - (obsolete) 8 FPA registers
310 * - (obsolete) FPA status
313 for (i = 0; i < 16; i++)
315 (*reg_list)[i] = &armv7m->core_cache->reg_list[i];
318 for (i = 16; i < 24; i++)
320 (*reg_list)[i] = &armv7m_gdb_dummy_fp_reg;
323 (*reg_list)[24] = &armv7m_gdb_dummy_fps_reg;
325 #ifdef ARMV7_GDB_HACKS
326 /* use dummy cpsr reg otherwise gdb may try and set the thumb bit */
327 (*reg_list)[25] = &armv7m_gdb_dummy_cpsr_reg;
329 /* ARMV7M is always in thumb mode, try to make GDB understand this
330 * if it does not support this arch */
331 *((char*)armv7m->core_cache->reg_list[15].value) |= 1;
333 (*reg_list)[25] = &armv7m->core_cache->reg_list[ARMV7M_xPSR];
339 /* run to exit point. return error if exit point was not reached. */
340 static int armv7m_run_and_wait(struct target *target, uint32_t entry_point, int timeout_ms, uint32_t exit_point, struct armv7m_common *armv7m)
344 /* This code relies on the target specific resume() and poll()->debug_entry()
345 * sequence to write register values to the processor and the read them back */
346 if ((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK)
351 retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
352 /* If the target fails to halt due to the breakpoint, force a halt */
353 if (retval != ERROR_OK || target->state != TARGET_HALTED)
355 if ((retval = target_halt(target)) != ERROR_OK)
357 if ((retval = target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK)
361 return ERROR_TARGET_TIMEOUT;
364 armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
365 if (pc != exit_point)
367 LOG_DEBUG("failed algoritm halted at 0x%" PRIx32 " ", pc);
368 return ERROR_TARGET_TIMEOUT;
374 /** Runs a Thumb algorithm in the target. */
375 int armv7m_run_algorithm(struct target *target,
376 int num_mem_params, struct mem_param *mem_params,
377 int num_reg_params, struct reg_param *reg_params,
378 uint32_t entry_point, uint32_t exit_point,
379 int timeout_ms, void *arch_info)
381 struct armv7m_common *armv7m = target_to_armv7m(target);
382 struct armv7m_algorithm *armv7m_algorithm_info = arch_info;
383 enum armv7m_mode core_mode = armv7m->core_mode;
384 int retval = ERROR_OK;
385 uint32_t context[ARMV7M_NUM_REGS];
387 if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC)
389 LOG_ERROR("current target isn't an ARMV7M target");
390 return ERROR_TARGET_INVALID;
393 if (target->state != TARGET_HALTED)
395 LOG_WARNING("target not halted");
396 return ERROR_TARGET_NOT_HALTED;
399 /* refresh core register cache */
400 /* Not needed if core register cache is always consistent with target process state */
401 for (unsigned i = 0; i < ARMV7M_NUM_REGS; i++)
403 if (!armv7m->core_cache->reg_list[i].valid)
404 armv7m->read_core_reg(target, i);
405 context[i] = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
408 for (int i = 0; i < num_mem_params; i++)
410 if ((retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
414 for (int i = 0; i < num_reg_params; i++)
416 struct reg *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
417 // uint32_t regvalue;
421 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
422 return ERROR_INVALID_ARGUMENTS;
425 if (reg->size != reg_params[i].size)
427 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
428 return ERROR_INVALID_ARGUMENTS;
431 // regvalue = buf_get_u32(reg_params[i].value, 0, 32);
432 armv7m_set_core_reg(reg, reg_params[i].value);
435 if (armv7m_algorithm_info->core_mode != ARMV7M_MODE_ANY)
437 LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
438 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value,
439 0, 1, armv7m_algorithm_info->core_mode);
440 armv7m->core_cache->reg_list[ARMV7M_CONTROL].dirty = 1;
441 armv7m->core_cache->reg_list[ARMV7M_CONTROL].valid = 1;
444 /* REVISIT speed things up (3% or so in one case) by requiring
445 * algorithms to include a BKPT instruction at each exit point.
446 * This eliminates overheads of adding/removing a breakpoint.
449 /* ARMV7M always runs in Thumb state */
450 if ((retval = breakpoint_add(target, exit_point, 2, BKPT_SOFT)) != ERROR_OK)
452 LOG_ERROR("can't add breakpoint to finish algorithm execution");
453 return ERROR_TARGET_FAILURE;
456 retval = armv7m_run_and_wait(target, entry_point, timeout_ms, exit_point, armv7m);
458 breakpoint_remove(target, exit_point);
460 if (retval != ERROR_OK)
465 /* Read memory values to mem_params[] */
466 for (int i = 0; i < num_mem_params; i++)
468 if (mem_params[i].direction != PARAM_OUT)
469 if ((retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
475 /* Copy core register values to reg_params[] */
476 for (int i = 0; i < num_reg_params; i++)
478 if (reg_params[i].direction != PARAM_OUT)
480 struct reg *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
484 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
485 return ERROR_INVALID_ARGUMENTS;
488 if (reg->size != reg_params[i].size)
490 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
491 return ERROR_INVALID_ARGUMENTS;
494 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
498 for (int i = ARMV7M_NUM_REGS - 1; i >= 0; i--)
501 regvalue = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
502 if (regvalue != context[i])
504 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
505 armv7m->core_cache->reg_list[i].name, context[i]);
506 buf_set_u32(armv7m->core_cache->reg_list[i].value,
508 armv7m->core_cache->reg_list[i].valid = 1;
509 armv7m->core_cache->reg_list[i].dirty = 1;
513 armv7m->core_mode = core_mode;
518 /** Logs summary of ARMv7-M state for a halted target. */
519 int armv7m_arch_state(struct target *target)
521 struct armv7m_common *armv7m = target_to_armv7m(target);
524 ctrl = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 32);
525 sp = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_R13].value, 0, 32);
527 LOG_USER("target halted due to %s, current mode: %s %s\n"
528 "xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32,
529 Jim_Nvp_value2name_simple(nvp_target_debug_reason,
530 target->debug_reason)->name,
531 armv7m_mode_strings[armv7m->core_mode],
532 armv7m_exception_string(armv7m->exception_number),
533 buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32),
534 buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_PC].value, 0, 32),
535 (ctrl & 0x02) ? 'p' : 'm',
540 static const struct reg_arch_type armv7m_reg_type = {
541 .get = armv7m_get_core_reg,
542 .set = armv7m_set_core_reg,
545 /** Builds cache of architecturally defined registers. */
546 struct reg_cache *armv7m_build_reg_cache(struct target *target)
548 struct armv7m_common *armv7m = target_to_armv7m(target);
549 int num_regs = ARMV7M_NUM_REGS;
550 struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
551 struct reg_cache *cache = malloc(sizeof(struct reg_cache));
552 struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
553 struct armv7m_core_reg *arch_info = calloc(num_regs, sizeof(struct armv7m_core_reg));
556 register_init_dummy(&armv7m_gdb_dummy_fps_reg);
557 #ifdef ARMV7_GDB_HACKS
558 register_init_dummy(&armv7m_gdb_dummy_cpsr_reg);
560 register_init_dummy(&armv7m_gdb_dummy_fp_reg);
562 /* Build the process context cache */
563 cache->name = "arm v7m registers";
565 cache->reg_list = reg_list;
566 cache->num_regs = num_regs;
568 armv7m->core_cache = cache;
570 for (i = 0; i < num_regs; i++)
572 arch_info[i].num = armv7m_regs[i].id;
573 arch_info[i].target = target;
574 arch_info[i].armv7m_common = armv7m;
575 reg_list[i].name = armv7m_regs[i].name;
576 reg_list[i].size = armv7m_regs[i].bits;
577 reg_list[i].value = calloc(1, 4);
578 reg_list[i].dirty = 0;
579 reg_list[i].valid = 0;
580 reg_list[i].type = &armv7m_reg_type;
581 reg_list[i].arch_info = &arch_info[i];
587 /** Sets up target as a generic ARMv7-M core */
588 int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m)
590 /* register arch-specific functions */
592 target->arch_info = armv7m;
593 armv7m->read_core_reg = armv7m_read_core_reg;
594 armv7m->write_core_reg = armv7m_write_core_reg;
599 /** Generates a CRC32 checksum of a memory region. */
600 int armv7m_checksum_memory(struct target *target,
601 uint32_t address, uint32_t count, uint32_t* checksum)
603 struct working_area *crc_algorithm;
604 struct armv7m_algorithm armv7m_info;
605 struct reg_param reg_params[2];
608 static const uint16_t cortex_m3_crc_code[] = {
609 0x4602, /* mov r2, r0 */
610 0xF04F, 0x30FF, /* mov r0, #0xffffffff */
611 0x460B, /* mov r3, r1 */
612 0xF04F, 0x0400, /* mov r4, #0 */
613 0xE013, /* b ncomp */
615 0x5D11, /* ldrb r1, [r2, r4] */
616 0xF8DF, 0x7028, /* ldr r7, CRC32XOR */
617 0xEA80, 0x6001, /* eor r0, r0, r1, asl #24 */
619 0xF04F, 0x0500, /* mov r5, #0 */
621 0x2800, /* cmp r0, #0 */
622 0xEA4F, 0x0640, /* mov r6, r0, asl #1 */
623 0xF105, 0x0501, /* add r5, r5, #1 */
624 0x4630, /* mov r0, r6 */
626 0xEA86, 0x0007, /* eor r0, r6, r7 */
627 0x2D08, /* cmp r5, #8 */
628 0xD1F4, /* bne loop */
630 0xF104, 0x0401, /* add r4, r4, #1 */
632 0x429C, /* cmp r4, r3 */
633 0xD1E9, /* bne nbyte */
636 0x1DB7, 0x04C1 /* CRC32XOR: .word 0x04C11DB7 */
641 if (target_alloc_working_area(target, sizeof(cortex_m3_crc_code), &crc_algorithm) != ERROR_OK)
643 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
646 /* convert flash writing code into a buffer in target endianness */
647 for (i = 0; i < (sizeof(cortex_m3_crc_code)/sizeof(uint16_t)); i++)
648 if ((retval = target_write_u16(target, crc_algorithm->address + i*sizeof(uint16_t), cortex_m3_crc_code[i])) != ERROR_OK)
653 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
654 armv7m_info.core_mode = ARMV7M_MODE_ANY;
656 init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT);
657 init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
659 buf_set_u32(reg_params[0].value, 0, 32, address);
660 buf_set_u32(reg_params[1].value, 0, 32, count);
662 if ((retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
663 crc_algorithm->address, crc_algorithm->address + (sizeof(cortex_m3_crc_code)-6), 20000, &armv7m_info)) != ERROR_OK)
665 LOG_ERROR("error executing cortex_m3 crc algorithm");
666 destroy_reg_param(®_params[0]);
667 destroy_reg_param(®_params[1]);
668 target_free_working_area(target, crc_algorithm);
672 *checksum = buf_get_u32(reg_params[0].value, 0, 32);
674 destroy_reg_param(®_params[0]);
675 destroy_reg_param(®_params[1]);
677 target_free_working_area(target, crc_algorithm);
682 /** Checks whether a memory region is zeroed. */
683 int armv7m_blank_check_memory(struct target *target,
684 uint32_t address, uint32_t count, uint32_t* blank)
686 struct working_area *erase_check_algorithm;
687 struct reg_param reg_params[3];
688 struct armv7m_algorithm armv7m_info;
692 static const uint16_t erase_check_code[] =
695 0xF810, 0x3B01, /* ldrb r3, [r0], #1 */
696 0xEA02, 0x0203, /* and r2, r2, r3 */
697 0x3901, /* subs r1, r1, #1 */
698 0xD1F9, /* bne loop */
703 /* make sure we have a working area */
704 if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK)
706 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
709 /* convert flash writing code into a buffer in target endianness */
710 for (i = 0; i < (sizeof(erase_check_code)/sizeof(uint16_t)); i++)
711 target_write_u16(target, erase_check_algorithm->address + i*sizeof(uint16_t), erase_check_code[i]);
713 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
714 armv7m_info.core_mode = ARMV7M_MODE_ANY;
716 init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
717 buf_set_u32(reg_params[0].value, 0, 32, address);
719 init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
720 buf_set_u32(reg_params[1].value, 0, 32, count);
722 init_reg_param(®_params[2], "r2", 32, PARAM_IN_OUT);
723 buf_set_u32(reg_params[2].value, 0, 32, 0xff);
725 if ((retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
726 erase_check_algorithm->address, erase_check_algorithm->address + (sizeof(erase_check_code)-2), 10000, &armv7m_info)) != ERROR_OK)
728 destroy_reg_param(®_params[0]);
729 destroy_reg_param(®_params[1]);
730 destroy_reg_param(®_params[2]);
731 target_free_working_area(target, erase_check_algorithm);
735 *blank = buf_get_u32(reg_params[2].value, 0, 32);
737 destroy_reg_param(®_params[0]);
738 destroy_reg_param(®_params[1]);
739 destroy_reg_param(®_params[2]);
741 target_free_working_area(target, erase_check_algorithm);
746 /*--------------------------------------------------------------------------*/
749 * Only stuff below this line should need to verify that its target
750 * is an ARMv7-M node.
752 * FIXME yet none of it _does_ verify target types yet!
757 * Return the debug ap baseaddress in hexadecimal;
758 * no extra output to simplify script processing
760 COMMAND_HANDLER(handle_dap_baseaddr_command)
762 struct target *target = get_current_target(cmd_ctx);
763 struct armv7m_common *armv7m = target_to_armv7m(target);
764 struct swjdp_common *swjdp = &armv7m->swjdp_info;
765 uint32_t apsel, apselsave, baseaddr;
768 apselsave = swjdp->apsel;
771 apsel = swjdp->apsel;
774 COMMAND_PARSE_NUMBER(u32, args[0], apsel);
777 return ERROR_COMMAND_SYNTAX_ERROR;
780 if (apselsave != apsel)
781 dap_ap_select(swjdp, apsel);
783 dap_ap_read_reg_u32(swjdp, 0xF8, &baseaddr);
784 retval = swjdp_transaction_endcheck(swjdp);
785 command_print(cmd_ctx, "0x%8.8" PRIx32 "", baseaddr);
787 if (apselsave != apsel)
788 dap_ap_select(swjdp, apselsave);
794 * Return the debug ap id in hexadecimal;
795 * no extra output to simplify script processing
797 COMMAND_HANDLER(handle_dap_apid_command)
799 struct target *target = get_current_target(cmd_ctx);
800 struct armv7m_common *armv7m = target_to_armv7m(target);
801 struct swjdp_common *swjdp = &armv7m->swjdp_info;
803 return CALL_COMMAND_HANDLER(dap_apid_command, swjdp);
806 COMMAND_HANDLER(handle_dap_apsel_command)
808 struct target *target = get_current_target(cmd_ctx);
809 struct armv7m_common *armv7m = target_to_armv7m(target);
810 struct swjdp_common *swjdp = &armv7m->swjdp_info;
812 return CALL_COMMAND_HANDLER(dap_apsel_command, swjdp);
815 COMMAND_HANDLER(handle_dap_memaccess_command)
817 struct target *target = get_current_target(cmd_ctx);
818 struct armv7m_common *armv7m = target_to_armv7m(target);
819 struct swjdp_common *swjdp = &armv7m->swjdp_info;
821 return CALL_COMMAND_HANDLER(dap_memaccess_command, swjdp);
825 COMMAND_HANDLER(handle_dap_info_command)
827 struct target *target = get_current_target(cmd_ctx);
828 struct armv7m_common *armv7m = target_to_armv7m(target);
829 struct swjdp_common *swjdp = &armv7m->swjdp_info;
834 apsel = swjdp->apsel;
837 COMMAND_PARSE_NUMBER(u32, args[0], apsel);
840 return ERROR_COMMAND_SYNTAX_ERROR;
843 return dap_info_command(cmd_ctx, swjdp, apsel);
846 /** Registers commands used to access DAP resources. */
847 int armv7m_register_commands(struct command_context *cmd_ctx)
849 struct command *arm_adi_v5_dap_cmd;
851 arm_adi_v5_dap_cmd = register_command(cmd_ctx, NULL, "dap",
853 "cortex dap specific commands");
855 register_command(cmd_ctx, arm_adi_v5_dap_cmd, "info",
856 handle_dap_info_command, COMMAND_EXEC,
857 "Displays dap info for ap [num],"
858 "default currently selected AP");
859 register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apsel",
860 handle_dap_apsel_command, COMMAND_EXEC,
861 "Select a different AP [num] (default 0)");
862 register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apid",
863 handle_dap_apid_command, COMMAND_EXEC,
864 "Displays id reg from AP [num], "
865 "default currently selected AP");
866 register_command(cmd_ctx, arm_adi_v5_dap_cmd, "baseaddr",
867 handle_dap_baseaddr_command, COMMAND_EXEC,
868 "Displays debug base address from AP [num],"
869 "default currently selected AP");
870 register_command(cmd_ctx, arm_adi_v5_dap_cmd, "memaccess",
871 handle_dap_memaccess_command, COMMAND_EXEC,
872 "set/get number of extra tck for mem-ap "
873 "memory bus access [0-255]");