1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26 #ifndef ARMV7M_COMMON_H
27 #define ARMV7M_COMMON_H
32 #include "arm_adi_v5.h"
34 /* define for enabling armv7 gdb workarounds */
36 #define ARMV7_GDB_HACKS
41 ARMV7M_MODE_THREAD = 0,
42 ARMV7M_MODE_USER_THREAD = 1,
43 ARMV7M_MODE_HANDLER = 2,
47 extern char* armv7m_mode_strings[];
51 ARMV7M_REGISTER_CORE_GP,
52 ARMV7M_REGISTER_CORE_SP,
53 ARMV7M_REGISTER_MEMMAP
56 extern char* armv7m_exception_strings[];
58 extern char *armv7m_exception_string(int number);
60 /* offsets into armv7m core register cache */
74 #define ARMV7M_COMMON_MAGIC 0x2A452A45
76 typedef struct armv7m_common_s
79 reg_cache_t *core_cache;
80 enum armv7m_mode core_mode;
82 swjdp_common_t swjdp_info;
85 /* Direct processor core register read and writes */
86 int (*load_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, u32 num, u32 *value);
87 int (*store_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, u32 num, u32 value);
88 /* register cache to processor synchronization */
89 int (*read_core_reg)(struct target_s *target, int num);
90 int (*write_core_reg)(struct target_s *target, int num);
92 int (*examine_debug_reason)(target_t *target);
93 void (*pre_debug_entry)(target_t *target);
94 void (*post_debug_entry)(target_t *target);
96 void (*pre_restore_context)(target_t *target);
97 void (*post_restore_context)(target_t *target);
102 typedef struct armv7m_algorithm_s
106 enum armv7m_mode core_mode;
107 } armv7m_algorithm_t;
109 typedef struct armv7m_core_reg_s
112 enum armv7m_regtype type;
113 enum armv7m_mode mode;
115 armv7m_common_t *armv7m_common;
118 extern reg_cache_t *armv7m_build_reg_cache(target_t *target);
119 extern enum armv7m_mode armv7m_number_to_mode(int number);
120 extern int armv7m_mode_to_number(enum armv7m_mode mode);
122 extern int armv7m_arch_state(struct target_s *target);
123 extern int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size);
125 extern int armv7m_register_commands(struct command_context_s *cmd_ctx);
126 extern int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m);
128 extern int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info);
130 extern int armv7m_invalidate_core_regs(target_t *target);
132 extern int armv7m_restore_context(target_t *target);
134 extern int armv7m_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum);
135 extern int armv7m_blank_check_memory(struct target_s *target, u32 address, u32 count, u32* blank);
137 /* Thumb mode instructions
140 /* Move to Register from Special Register (Thumb mode) 32 bit Thumb2 instruction
141 * Rd: destination register
142 * SYSm: source special register
144 #define ARMV7M_T_MRS(Rd, SYSm) ((0xF3EF) | ((0x8000 | (Rd<<8) | SYSm) << 16))
146 /* Move from Register from Special Register (Thumb mode) 32 bit Thumb2 instruction
147 * Rd: source register
148 * SYSm: destination special register
150 #define ARMV7M_T_MSR(SYSm, Rn) ((0xF380 | ( Rn<<8 )) | ((0x8800 | SYSm) << 16))
152 /* Change Processor State. The instruction modifies the PRIMASK and FAULTMASK
153 * special-purpose register values (Thumb mode) 16 bit Thumb2 instruction
154 * Rd: source register
159 #define ARMV7M_T_CPSID(IF) ((0xB660 | (1<<8) | (IF&0x3)) | ((0xB660 | (1<<8) | (IF&0x3)) << 16))
160 #define ARMV7M_T_CPSIE(IF) ((0xB660 | (0<<8) | (IF&0x3)) | ((0xB660 | (0<<8) | (IF&0x3)) << 16))
162 /* Breakpoint (Thumb mode) v5 onwards
163 * Im: immediate value used by debugger
165 #define ARMV7M_T_BKPT(Im) ((0xBE00 | Im ) | ((0xBE00 | Im ) << 16))
167 /* Store register (Thumb mode)
168 * Rd: source register
171 #define ARMV7M_T_STR(Rd, Rn) ((0x6000 | Rd | (Rn << 3)) | ((0x6000 | Rd | (Rn << 3)) << 16))
173 /* Load register (Thumb state)
174 * Rd: destination register
177 #define ARMV7M_T_LDR(Rd, Rn) ((0x6800 | (Rn << 3) | Rd) | ((0x6800 | (Rn << 3) | Rd) << 16))
179 /* Load multiple (Thumb state)
181 * List: for each bit in list: store register
183 #define ARMV7M_T_LDMIA(Rn, List) ((0xc800 | (Rn << 8) | List) | ((0xc800 | (Rn << 8) | List) << 16))
185 /* Load register with PC relative addressing
186 * Rd: register to load
188 #define ARMV7M_T_LDR_PCREL(Rd) ((0x4800 | (Rd << 8)) | ((0x4800 | (Rd << 8)) << 16))
190 /* Move hi register (Thumb mode)
191 * Rd: destination register
192 * Rm: source register
194 #define ARMV7M_T_MOV(Rd, Rm) ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) | ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) << 16))
196 /* No operation (Thumb mode)
198 #define ARMV7M_T_NOP (0x46c0 | (0x46c0 << 16))
200 /* Move immediate to register (Thumb state)
201 * Rd: destination register
202 * Im: 8-bit immediate value
204 #define ARMV7M_T_MOV_IM(Rd, Im) ((0x2000 | (Rd << 8) | Im) | ((0x2000 | (Rd << 8) | Im) << 16))
206 /* Branch and Exchange
207 * Rm: register containing branch target
209 #define ARMV7M_T_BX(Rm) ((0x4700 | (Rm << 3)) | ((0x4700 | (Rm << 3)) << 16))
211 /* Branch (Thumb state)
214 #define ARMV7M_T_B(Imm) ((0xe000 | Imm) | ((0xe000 | Imm) << 16))
216 #endif /* ARMV7M_H */