1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * Copyright (C) 2006 by Magnus Lundin *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
22 #ifndef ARMV7M_COMMON_H
23 #define ARMV7M_COMMON_H
31 ARMV7M_MODE_HANDLER = 0,
32 ARMV7M_MODE_THREAD = 1,
36 extern char* armv7m_mode_strings[];
46 ARMV7M_REGISTER_CORE_GP,
47 ARMV7M_REGISTER_CORE_SP,
48 ARMV7M_REGISTER_MEMMAP
51 enum armv7m_runcontext
53 ARMV7M_PROCESS_CONTEXT,
57 extern char* armv7m_state_strings[];
58 extern char* armv7m_exception_strings[];
60 extern char *armv7m_exception_string(int number);
62 /* offsets into armv7m core register cache */
76 #define ARMV7M_COMMON_MAGIC 0x2A452A45
78 typedef struct armv7m_common_s
81 reg_cache_t *core_cache;
82 reg_cache_t *process_context;
83 reg_cache_t *debug_context;
84 enum armv7m_mode core_mode;
85 enum armv7m_state core_state;
87 int (*full_context)(struct target_s *target);
88 /* Direct processor core register read and writes */
89 int (*load_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, u32 num, u32 *value);
90 int (*store_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, u32 num, u32 value);
91 /* register cache to processor synchronization */
92 int (*read_core_reg)(struct target_s *target, int num);
93 int (*write_core_reg)(struct target_s *target, int num);
94 /* get or set register through cache, return error if target is running and synchronisation is impossible */
95 int (*get_core_reg_32)(struct target_s *target, int num, u32* value);
96 int (*set_core_reg_32)(struct target_s *target, int num, u32 value);
99 reg_cache_t *eice_cache;
100 reg_cache_t *etm_cache;
102 int (*examine_debug_reason)(target_t *target);
104 void (*change_to_arm)(target_t *target, u32 *r0, u32 *pc);
106 // void (*read_core_regs)(target_t *target, u32 mask, u32 *core_regs[16]);
107 // void (*read_core_regs_target_buffer)(target_t *target, u32 mask, void *buffer, int size);
108 // void (*write_core_regs)(target_t *target, u32 mask, u32 core_regs[16]);
111 void (*write_xpsr_im8)(target_t *target, u8 xpsr_im, int rot, int spsr);
113 void (*load_word_regs)(target_t *target, u32 mask);
114 void (*load_hword_reg)(target_t *target, int num);
115 void (*load_byte_reg)(target_t *target, int num);
117 void (*store_word_regs)(target_t *target, u32 mask);
118 void (*store_hword_reg)(target_t *target, int num);
119 void (*store_byte_reg)(target_t *target, int num);
121 void (*write_pc)(target_t *target, u32 pc);
122 void (*branch_resume)(target_t *target);
125 void (*pre_debug_entry)(target_t *target);
126 void (*post_debug_entry)(target_t *target);
128 void (*pre_restore_context)(target_t *target);
129 void (*post_restore_context)(target_t *target);
134 typedef struct armv7m_algorithm_s
138 enum armv7m_mode core_mode;
139 enum armv7m_state core_state;
140 } armv7m_algorithm_t;
142 typedef struct armv7m_core_reg_s
145 enum armv7m_regtype type;
146 enum armv7m_mode mode;
148 armv7m_common_t *armv7m_common;
151 extern reg_cache_t *armv7m_build_reg_cache(target_t *target);
152 extern enum armv7m_mode armv7m_number_to_mode(int number);
153 extern int armv7m_mode_to_number(enum armv7m_mode mode);
155 extern int armv7m_arch_state(struct target_s *target, char *buf, int buf_size);
156 extern int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size);
157 extern int armv7m_invalidate_core_regs(target_t *target);
159 extern int armv7m_register_commands(struct command_context_s *cmd_ctx);
160 extern int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m);
162 extern int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info);
164 extern int armv7m_invalidate_core_regs(target_t *target);
166 extern enum armv7m_runcontext armv7m_get_context(target_t *target);
167 extern int armv7m_use_context(target_t *target, enum armv7m_runcontext new_ctx);
168 extern enum armv7m_runcontext armv7m_get_context(target_t *target);
169 extern int armv7m_restore_context(target_t *target);
171 extern int armv7m_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum);
173 /* Thumb mode instructions
176 /* Move to Register from Special Register (Thumb mode) 32 bit Thumb2 instruction
177 * Rd: destination register
178 * SYSm: source special register
180 #define ARMV7M_T_MRS(Rd, SYSm) ((0xF3EF) | ((0x8000 | (Rd<<8) | SYSm) << 16))
182 /* Move from Register from Special Register (Thumb mode) 32 bit Thumb2 instruction
183 * Rd: source register
184 * SYSm: destination special register
186 #define ARMV7M_T_MSR(SYSm, Rn) ((0xF380 | ( Rn<<8 )) | ((0x8800 | SYSm) << 16))
188 /* Change Processor State. The instruction modifies the PRIMASK and FAULTMASK
189 * special-purpose register values (Thumb mode) 16 bit Thumb2 instruction
190 * Rd: source register
195 #define ARMV7M_T_CPSID(IF) ((0xB660 | (1<<8) | (IF&0x3)) | ((0xB660 | (1<<8) | (IF&0x3)) << 16))
196 #define ARMV7M_T_CPSIE(IF) ((0xB660 | (0<<8) | (IF&0x3)) | ((0xB660 | (0<<8) | (IF&0x3)) << 16))
198 /* Breakpoint (Thumb mode) v5 onwards
199 * Im: immediate value used by debugger
201 #define ARMV7M_T_BKPT(Im) ((0xBE00 | Im ) | ((0xBE00 | Im ) << 16))
203 /* Store register (Thumb mode)
204 * Rd: source register
207 #define ARMV7M_T_STR(Rd, Rn) ((0x6000 | Rd | (Rn << 3)) | ((0x6000 | Rd | (Rn << 3)) << 16))
209 /* Load register (Thumb state)
210 * Rd: destination register
213 #define ARMV7M_T_LDR(Rd, Rn) ((0x6800 | (Rn << 3) | Rd) | ((0x6800 | (Rn << 3) | Rd) << 16))
215 /* Load multiple (Thumb state)
217 * List: for each bit in list: store register
219 #define ARMV7M_T_LDMIA(Rn, List) ((0xc800 | (Rn << 8) | List) | ((0xc800 | (Rn << 8) | List) << 16))
221 /* Load register with PC relative addressing
222 * Rd: register to load
224 #define ARMV7M_T_LDR_PCREL(Rd) ((0x4800 | (Rd << 8)) | ((0x4800 | (Rd << 8)) << 16))
226 /* Move hi register (Thumb mode)
227 * Rd: destination register
228 * Rm: source register
230 #define ARMV7M_T_MOV(Rd, Rm) ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) | ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) << 16))
232 /* No operation (Thumb mode)
234 #define ARMV7M_T_NOP (0x46c0 | (0x46c0 << 16))
236 /* Move immediate to register (Thumb state)
237 * Rd: destination register
238 * Im: 8-bit immediate value
240 #define ARMV7M_T_MOV_IM(Rd, Im) ((0x2000 | (Rd << 8) | Im) | ((0x2000 | (Rd << 8) | Im) << 16))
242 /* Branch and Exchange
243 * Rm: register containing branch target
245 #define ARMV7M_T_BX(Rm) ((0x4700 | (Rm << 3)) | ((0x4700 | (Rm << 3)) << 16))
247 /* Branch (Thumb state)
250 #define ARMV7M_T_B(Imm) ((0xe000 | Imm) | ((0xe000 | Imm) << 16))
252 #endif /* ARMV7M_H */