1 /***************************************************************************
2 * Copyright (C) 2015 by David Ung *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 ***************************************************************************/
19 #ifndef OPENOCD_TARGET_ARMV8_H
20 #define OPENOCD_TARGET_ARMV8_H
22 #include "arm_adi_v5.h"
24 #include "armv4_5_mmu.h"
25 #include "armv4_5_cache.h"
26 #include "armv8_dpm.h"
82 #define ARMV8_COMMON_MAGIC 0x0A450AAA
84 /* VA to PA translation operations opc2 values*/
93 /* L210/L220 cache controller support */
94 struct armv8_l2x_cache {
99 struct armv8_cachesize {
101 /* cache dimensionning */
103 uint32_t associativity;
106 /* info for set way operation on cache */
108 uint32_t index_shift;
113 /* information about one architecture cache at any level */
114 struct armv8_arch_cache {
115 int ctype; /* cache type, CLIDR encoding */
116 struct armv8_cachesize d_u_size; /* data cache */
117 struct armv8_cachesize i_size; /* instruction cache */
120 struct armv8_cache_common {
125 struct armv8_arch_cache arch[6]; /* cache info, L1 - L7 */
127 int d_u_cache_enabled;
129 /* l2 external unified cache if some */
131 int (*flush_all_data_cache)(struct target *target);
132 int (*display_cache_info)(struct command_context *cmd_ctx,
133 struct armv8_cache_common *armv8_cache);
136 struct armv8_mmu_common {
137 /* following field mmu working way */
138 int32_t ttbr1_used; /* -1 not initialized, 0 no ttbr1 1 ttbr1 used and */
139 uint64_t ttbr0_mask;/* masked to be used */
141 uint32_t ttbcr; /* cache for ttbcr register */
142 uint32_t ttbr_mask[2];
143 uint32_t ttbr_range[2];
145 int (*read_physical_memory)(struct target *target, target_addr_t address,
146 uint32_t size, uint32_t count, uint8_t *buffer);
147 struct armv8_cache_common armv8_cache;
148 uint32_t mmu_enabled;
151 struct armv8_common {
154 struct reg_cache *core_cache;
156 /* Core Debug Unit */
159 struct adiv5_ap *debug_ap;
161 const uint32_t *opcodes;
164 uint8_t multi_processor_system;
168 /* armv8 aarch64 need below information for page translation */
174 struct armv8_mmu_common armv8_mmu;
178 /* Direct processor core register read and writes */
179 int (*read_reg_u64)(struct armv8_common *armv8, int num, uint64_t *value);
180 int (*write_reg_u64)(struct armv8_common *armv8, int num, uint64_t value);
182 int (*examine_debug_reason)(struct target *target);
183 int (*post_debug_entry)(struct target *target);
185 void (*pre_restore_context)(struct target *target);
188 static inline struct armv8_common *
189 target_to_armv8(struct target *target)
191 return container_of(target->arch_info, struct armv8_common, arm);
194 /* register offsets from armv8.debug_base */
195 #define CPUV8_DBG_MAINID0 0xD00
196 #define CPUV8_DBG_CPUFEATURE0 0xD20
197 #define CPUV8_DBG_DBGFEATURE0 0xD28
198 #define CPUV8_DBG_MEMFEATURE0 0xD38
200 #define CPUV8_DBG_LOCKACCESS 0xFB0
201 #define CPUV8_DBG_LOCKSTATUS 0xFB4
203 #define CPUV8_DBG_EDESR 0x20
204 #define CPUV8_DBG_EDECR 0x24
205 #define CPUV8_DBG_WFAR0 0x30
206 #define CPUV8_DBG_WFAR1 0x34
207 #define CPUV8_DBG_DSCR 0x088
208 #define CPUV8_DBG_DRCR 0x090
209 #define CPUV8_DBG_PRCR 0x310
210 #define CPUV8_DBG_PRSR 0x314
212 #define CPUV8_DBG_DTRRX 0x080
213 #define CPUV8_DBG_ITR 0x084
214 #define CPUV8_DBG_SCR 0x088
215 #define CPUV8_DBG_DTRTX 0x08c
217 #define CPUV8_DBG_BVR_BASE 0x400
218 #define CPUV8_DBG_BCR_BASE 0x408
219 #define CPUV8_DBG_WVR_BASE 0x800
220 #define CPUV8_DBG_WCR_BASE 0x808
221 #define CPUV8_DBG_VCR 0x01C
223 #define CPUV8_DBG_OSLAR 0x300
225 #define CPUV8_DBG_AUTHSTATUS 0xFB8
227 #define PAGE_SIZE_4KB 0x1000
228 #define PAGE_SIZE_4KB_LEVEL0_BITS 39
229 #define PAGE_SIZE_4KB_LEVEL1_BITS 30
230 #define PAGE_SIZE_4KB_LEVEL2_BITS 21
231 #define PAGE_SIZE_4KB_LEVEL3_BITS 12
233 #define PAGE_SIZE_4KB_LEVEL0_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL0_BITS)
234 #define PAGE_SIZE_4KB_LEVEL1_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL1_BITS)
235 #define PAGE_SIZE_4KB_LEVEL2_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL2_BITS)
236 #define PAGE_SIZE_4KB_LEVEL3_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL3_BITS)
238 #define PAGE_SIZE_4KB_TRBBASE_MASK 0xFFFFFFFFF000
240 int armv8_arch_state(struct target *target);
241 int armv8_read_mpidr(struct armv8_common *armv8);
242 int armv8_identify_cache(struct armv8_common *armv8);
243 int armv8_init_arch_info(struct target *target, struct armv8_common *armv8);
244 int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va,
245 target_addr_t *val, int meminfo);
246 int armv8_mmu_translate_va(struct target *target, target_addr_t va, target_addr_t *val);
248 int armv8_handle_cache_info_command(struct command_context *cmd_ctx,
249 struct armv8_cache_common *armv8_cache);
251 void armv8_set_cpsr(struct arm *arm, uint32_t cpsr);
253 static inline unsigned int armv8_curel_from_core_mode(enum arm_mode core_mode)
260 case ARM_MODE_ABT: /* FIXME: EL3? */
261 case ARM_MODE_IRQ: /* FIXME: EL3? */
262 case ARM_MODE_FIQ: /* FIXME: EL3? */
263 case ARM_MODE_UND: /* FIXME: EL3? */
264 case ARM_MODE_SYS: /* FIXME: EL3? */
266 /* case ARM_MODE_HYP:
271 /* all Aarch64 modes */
273 return (core_mode >> 2) & 3;
277 void armv8_select_reg_access(struct armv8_common *armv8, bool is_aarch64);
278 int armv8_set_dbgreg_bits(struct armv8_common *armv8, unsigned int reg, unsigned long mask, unsigned long value);
280 extern const struct command_registration armv8_command_handlers[];
282 #endif /* OPENOCD_TARGET_ARMV8_H */