1 /***************************************************************************
2 * Copyright (C) 2015 by David Ung *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 ***************************************************************************/
19 #ifndef OPENOCD_TARGET_ARMV8_H
20 #define OPENOCD_TARGET_ARMV8_H
22 #include "arm_adi_v5.h"
24 #include "armv4_5_mmu.h"
25 #include "armv4_5_cache.h"
26 #include "armv8_dpm.h"
69 #define ARMV8_COMMON_MAGIC 0x0A450AAA
71 /* VA to PA translation operations opc2 values*/
80 /* L210/L220 cache controller support */
81 struct armv8_l2x_cache {
86 struct armv8_cachesize {
88 /* cache dimensionning */
90 uint32_t associativity;
93 /* info for set way operation on cache */
100 /* information about one architecture cache at any level */
101 struct armv8_arch_cache {
102 int ctype; /* cache type, CLIDR encoding */
103 struct armv8_cachesize d_u_size; /* data cache */
104 struct armv8_cachesize i_size; /* instruction cache */
107 struct armv8_cache_common {
112 struct armv8_arch_cache arch[6]; /* cache info, L1 - L7 */
114 int d_u_cache_enabled;
116 /* l2 external unified cache if some */
118 int (*flush_all_data_cache)(struct target *target);
119 int (*display_cache_info)(struct command_context *cmd_ctx,
120 struct armv8_cache_common *armv8_cache);
123 struct armv8_mmu_common {
124 /* following field mmu working way */
125 int32_t ttbr1_used; /* -1 not initialized, 0 no ttbr1 1 ttbr1 used and */
126 uint64_t ttbr0_mask;/* masked to be used */
128 uint32_t ttbcr; /* cache for ttbcr register */
129 uint32_t ttbr_mask[2];
130 uint32_t ttbr_range[2];
132 int (*read_physical_memory)(struct target *target, target_addr_t address,
133 uint32_t size, uint32_t count, uint8_t *buffer);
134 struct armv8_cache_common armv8_cache;
135 uint32_t mmu_enabled;
138 struct armv8_common {
141 struct reg_cache *core_cache;
143 /* Core Debug Unit */
147 struct adiv5_ap *debug_ap;
149 const uint32_t *opcodes;
152 uint8_t multi_processor_system;
156 /* armv8 aarch64 need below information for page translation */
162 struct armv8_mmu_common armv8_mmu;
164 /* Direct processor core register read and writes */
165 int (*load_core_reg_u64)(struct target *target, uint32_t num, uint64_t *value);
166 int (*store_core_reg_u64)(struct target *target, uint32_t num, uint64_t value);
168 int (*examine_debug_reason)(struct target *target);
169 int (*post_debug_entry)(struct target *target);
171 void (*pre_restore_context)(struct target *target);
174 static inline struct armv8_common *
175 target_to_armv8(struct target *target)
177 return container_of(target->arch_info, struct armv8_common, arm);
180 /* register offsets from armv8.debug_base */
181 #define CPUV8_DBG_MAINID0 0xD00
182 #define CPUV8_DBG_CPUFEATURE0 0xD20
183 #define CPUV8_DBG_DBGFEATURE0 0xD28
184 #define CPUV8_DBG_MEMFEATURE0 0xD38
186 #define CPUV8_DBG_LOCKACCESS 0xFB0
187 #define CPUV8_DBG_LOCKSTATUS 0xFB4
189 #define CPUV8_DBG_EDESR 0x20
190 #define CPUV8_DBG_EDECR 0x24
191 #define CPUV8_DBG_WFAR0 0x30
192 #define CPUV8_DBG_WFAR1 0x34
193 #define CPUV8_DBG_DSCR 0x088
194 #define CPUV8_DBG_DRCR 0x090
195 #define CPUV8_DBG_PRCR 0x310
196 #define CPUV8_DBG_PRSR 0x314
198 #define CPUV8_DBG_DTRRX 0x080
199 #define CPUV8_DBG_ITR 0x084
200 #define CPUV8_DBG_SCR 0x088
201 #define CPUV8_DBG_DTRTX 0x08c
203 #define CPUV8_DBG_BVR_BASE 0x400
204 #define CPUV8_DBG_BCR_BASE 0x408
205 #define CPUV8_DBG_WVR_BASE 0x800
206 #define CPUV8_DBG_WCR_BASE 0x808
207 #define CPUV8_DBG_VCR 0x01C
209 #define CPUV8_DBG_OSLAR 0x300
211 #define CPUV8_DBG_AUTHSTATUS 0xFB8
213 /*define CTI(cross trigger interface)*/
215 #define CTI_INACK 0x10
216 #define CTI_APPSET 0x14
217 #define CTI_APPCLEAR 0x18
218 #define CTI_APPPULSE 0x1C
219 #define CTI_INEN0 0x20
220 #define CTI_INEN1 0x24
221 #define CTI_INEN2 0x28
222 #define CTI_INEN3 0x2C
223 #define CTI_INEN4 0x30
224 #define CTI_INEN5 0x34
225 #define CTI_INEN6 0x38
226 #define CTI_INEN7 0x3C
227 #define CTI_OUTEN0 0xA0
228 #define CTI_OUTEN1 0xA4
229 #define CTI_OUTEN2 0xA8
230 #define CTI_OUTEN3 0xAC
231 #define CTI_OUTEN4 0xB0
232 #define CTI_OUTEN5 0xB4
233 #define CTI_OUTEN6 0xB8
234 #define CTI_OUTEN7 0xBC
235 #define CTI_TRIN_STATUS 0x130
236 #define CTI_TROUT_STATUS 0x134
237 #define CTI_CHIN_STATUS 0x138
238 #define CTI_CHOU_STATUS 0x13C
239 #define CTI_GATE 0x140
240 #define CTI_UNLOCK 0xFB0
242 #define CTI_CHNL(x) (1 << x)
243 #define CTI_TRIG_HALT 0
244 #define CTI_TRIG_RESUME 1
245 #define CTI_TRIG(n) (1 << CTI_TRIG_##n)
247 #define PAGE_SIZE_4KB 0x1000
248 #define PAGE_SIZE_4KB_LEVEL0_BITS 39
249 #define PAGE_SIZE_4KB_LEVEL1_BITS 30
250 #define PAGE_SIZE_4KB_LEVEL2_BITS 21
251 #define PAGE_SIZE_4KB_LEVEL3_BITS 12
253 #define PAGE_SIZE_4KB_LEVEL0_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL0_BITS)
254 #define PAGE_SIZE_4KB_LEVEL1_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL1_BITS)
255 #define PAGE_SIZE_4KB_LEVEL2_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL2_BITS)
256 #define PAGE_SIZE_4KB_LEVEL3_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL3_BITS)
258 #define PAGE_SIZE_4KB_TRBBASE_MASK 0xFFFFFFFFF000
260 int armv8_arch_state(struct target *target);
261 int armv8_read_mpidr(struct armv8_common *armv8);
262 int armv8_identify_cache(struct armv8_common *armv8);
263 int armv8_init_arch_info(struct target *target, struct armv8_common *armv8);
264 int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va,
265 target_addr_t *val, int meminfo);
266 int armv8_mmu_translate_va(struct target *target, target_addr_t va, target_addr_t *val);
268 int armv8_handle_cache_info_command(struct command_context *cmd_ctx,
269 struct armv8_cache_common *armv8_cache);
271 void armv8_set_cpsr(struct arm *arm, uint32_t cpsr);
273 static inline int armv8_curel_from_core_mode(struct arm *arm)
275 return (arm->core_mode >> 6) & 3;
277 extern const struct command_registration armv8_command_handlers[];